[PART1 PATCH 0/8] Introduce a method to get clock gating status dynamically

[PART1 PATCH 0/8] Introduce a method to get clock gating status dynamically

[Huang Rui]

This series patches implement to get the clock gating status
dynamically into debugfs. User will enter profiling mode to runtime
disable clockgating, so it needs an interface to expose clock gating
states. Part 1 works for VI, I will implement it on CI/SI in following
days.

Here is the example on Fiji:

root@jenkins-All-Series:/home/jenkins# cat /sys/kernel/debug/dri/64/amdgpu_pm_info
Clock Gating Flags Mask: 0x3dfff
        Medium Grain Clock Gating: On
        Medium Grain memory Light Sleep: On
        Coarse Grain Clock Gating: On
        Coarse Grain memory Light Sleep: On
        Coarse Grain Tree Shader: On
        Coarse Grain Tree Shader Light Sleep: On
        Command Processor Light Sleep: On
        Run List Controller Light Sleep: On
        Memory Controller Light Sleep: On
        Memory Controller Medium Grain Clock Gating: On
        System Direct Memory Access Light Sleep: On
        System Direct Memory Access Medium Grain Clock Gating: On
        Bus Interface Light Sleep: On
        Universal Video Decoder Medium Grain Clock Gating: Off
        Video Coding Engine Medium Grain Clock Gating: On
        Host Data Path Light Sleep: On
        Host Data Path Medium Grain Clock Gating: On
        Rom Medium Grain Clock Gating: On
...

Thanks,
Rui

Huang Rui (8):
  drm/amdgpu: introduce an interface to get clock gating status
    dynamically
  drm/amdgpu: add parse clock gating state
  drm/amdgpu: add clockgating_state method for gfx v8
  drm/amdgpu: add clockgating_state method for gmc v8
  drm/amdgpu: add clockgating_state method for sdma v3
  drm/amdgpu: add clockgating_state method for vi common
  drm/amdgpu: add clockgating_state method for uvd v5&v6
  drm/amdgpu: add clockgating_state method for vce v3

 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 99 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c      | 40 ++++++++++++
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      | 16 +++++
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c     | 17 +++++
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c      | 12 ++++
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c      | 12 ++++
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c      | 18 ++++++
 drivers/gpu/drm/amd/amdgpu/vi.c            | 27 ++++++++
 drivers/gpu/drm/amd/include/amd_shared.h   |  2 +
 11 files changed, 256 insertions(+)

-- 
2.7.4

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[PART1 PATCH 1/8] drm/amdgpu: introduce an interface to get clock gating status dynamically

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     |  4 ++++
 drivers/gpu/drm/amd/include/amd_shared.h   |  2 ++
 4 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 96eeea7..e12cf04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -207,6 +207,7 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
 				  enum amd_ip_block_type block_type,
 				  enum amd_powergating_state state);
+void amdgpu_clockgating_state(struct amdgpu_device *adev, u32 *flags);
 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
 			 enum amd_ip_block_type block_type);
 bool amdgpu_is_idle(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c398ff6..d7d0998 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1294,6 +1294,18 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev,
 	return r;
 }
 
+void amdgpu_clockgating_state(struct amdgpu_device *adev, u32 *flags)
+{
+	int i;
+
+	for (i = 0; i < adev->num_ip_blocks; i++) {
+		if (!adev->ip_blocks[i].status.valid)
+			continue;
+		if (adev->ip_blocks[i].version->funcs->clockgating_state)
+			adev->ip_blocks[i].version->funcs->clockgating_state((void *)adev, flags);
+	}
+}
+
 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
 			 enum amd_ip_block_type block_type)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index a7c7657..7aa561d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1542,6 +1542,10 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
 	struct drm_device *dev = node->minor->dev;
 	struct amdgpu_device *adev = dev->dev_private;
 	struct drm_device *ddev = adev->ddev;
+	u32 flags = 0;
+
+	amdgpu_clockgating_state(adev, &flags);
+	seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
 
 	if (!adev->pm.dpm_enabled) {
 		seq_printf(m, "dpm not enabled\n");
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 429a82b..9911cd2 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -214,6 +214,8 @@ struct amd_ip_funcs {
 	/* enable/disable pg for the IP block */
 	int (*set_powergating_state)(void *handle,
 				     enum amd_powergating_state state);
+	/* get current clockgating status */
+	void (*clockgating_state)(void *handle, u32 *flags);
 };
 
 #endif /* __AMD_SHARED_H__ */
-- 
2.7.4

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[PART1 PATCH 2/8] drm/amdgpu: add parse clock gating state

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 95 ++++++++++++++++++++++++++++++++++
 1 file changed, 95 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 7aa561d..431bae4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1536,6 +1536,99 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
 	return 0;
 }
 
+static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
+{
+       if (flags & AMD_CG_SUPPORT_GFX_MGCG)
+               seq_printf(m, "\tMedium Grain Clock Gating: On\n");
+       else
+               seq_printf(m, "\tMedium Grain Clock Gating: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_GFX_MGLS)
+               seq_printf(m, "\tMedium Grain memory Light Sleep: On\n");
+       else
+               seq_printf(m, "\tMedium Grain memory Light Sleep: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_GFX_CGCG)
+               seq_printf(m, "\tCoarse Grain Clock Gating: On\n");
+       else
+               seq_printf(m, "\tCoarse Grain Clock Gating: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_GFX_CGLS)
+               seq_printf(m, "\tCoarse Grain memory Light Sleep: On\n");
+       else
+               seq_printf(m, "\tCoarse Grain memory Light Sleep: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_GFX_CGTS)
+               seq_printf(m, "\tCoarse Grain Tree Shader: On\n");
+       else
+               seq_printf(m, "\tCoarse Grain Tree Shader: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_GFX_CGTS_LS)
+               seq_printf(m, "\tCoarse Grain Tree Shader Light Sleep: On\n");
+       else
+               seq_printf(m, "\tCoarse Grain Tree Shader Light Sleep: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_GFX_CP_LS)
+               seq_printf(m, "\tCommand Processor Light Sleep: On\n");
+       else
+               seq_printf(m, "\tCommand Processor Light Sleep: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_GFX_RLC_LS)
+               seq_printf(m, "\tRun List Controller Light Sleep: On\n");
+       else
+               seq_printf(m, "\tRun List Controller Light Sleep: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_MC_LS)
+               seq_printf(m, "\tMemory Controller Light Sleep: On\n");
+       else
+               seq_printf(m, "\tMemory Controller Light Sleep: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_MC_MGCG)
+               seq_printf(m, "\tMemory Controller Medium Grain Clock Gating: On\n");
+       else
+               seq_printf(m, "\tMemory Controller Medium Grain Clock Gating: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_SDMA_LS)
+               seq_printf(m, "\tSystem Direct Memory Access Light Sleep: On\n");
+       else
+               seq_printf(m, "\tSystem Direct Memory Access Light Sleep: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_SDMA_MGCG)
+               seq_printf(m, "\tSystem Direct Memory Access Medium Grain Clock Gating: On\n");
+       else
+               seq_printf(m, "\tSystem Direct Memory Access Medium Grain Clock Gating: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_BIF_LS)
+               seq_printf(m, "\tBus Interface Light Sleep: On\n");
+       else
+               seq_printf(m, "\tBus Interface Light Sleep: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_UVD_MGCG)
+               seq_printf(m, "\tUniversal Video Decoder Medium Grain Clock Gating: On\n");
+       else
+               seq_printf(m, "\tUniversal Video Decoder Medium Grain Clock Gating: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_VCE_MGCG)
+               seq_printf(m, "\tVideo Coding Engine Medium Grain Clock Gating: On\n");
+       else
+               seq_printf(m, "\tVideo Coding Engine Medium Grain Clock Gating: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_HDP_LS)
+               seq_printf(m, "\tHost Data Path Light Sleep: On\n");
+       else
+               seq_printf(m, "\tHost Data Path Light Sleep: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_HDP_MGCG)
+               seq_printf(m, "\tHost Data Path Medium Grain Clock Gating: On\n");
+       else
+               seq_printf(m, "\tHost Data Path Medium Grain Clock Gating: Off\n");
+
+       if (flags & AMD_CG_SUPPORT_ROM_MGCG)
+               seq_printf(m, "\tRom Medium Grain Clock Gating: On\n");
+       else
+               seq_printf(m, "\tRom Medium Grain Clock Gating: Off\n");
+}
+
 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
 {
 	struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -1546,6 +1639,8 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
 
 	amdgpu_clockgating_state(adev, &flags);
 	seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
+	amdgpu_parse_cg_state(m, flags);
+	seq_printf(m, "\n");
 
 	if (!adev->pm.dpm_enabled) {
 		seq_printf(m, "dpm not enabled\n");
-- 
2.7.4

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[PART1 PATCH 3/8] drm/amdgpu: add clockgating_state method for gfx v8

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index c4afa8e..25e5670 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5657,6 +5657,45 @@ static int gfx_v8_0_set_powergating_state(void *handle,
 	return 0;
 }
 
+static void gfx_v8_0_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int data;
+
+	/* AMD_CG_SUPPORT_GFX_MGCG */
+	data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
+	if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK))
+		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
+
+	/* AMD_CG_SUPPORT_GFX_CGLG */
+	data = RREG32(mmRLC_CGCG_CGLS_CTRL);
+	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
+		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
+
+	/* AMD_CG_SUPPORT_GFX_CGLS */
+	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
+		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
+
+	/* AMD_CG_SUPPORT_GFX_CGTS */
+	data = RREG32(mmCGTS_SM_CTRL_REG);
+	if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK))
+		*flags |= AMD_CG_SUPPORT_GFX_CGTS;
+
+	/* AMD_CG_SUPPORT_GFX_CGTS_LS */
+	if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK))
+		*flags |= AMD_CG_SUPPORT_GFX_CGTS_LS;
+
+	/* AMD_CG_SUPPORT_GFX_RLC_LS */
+	data = RREG32(mmRLC_MEM_SLP_CNTL);
+	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
+		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
+
+	/* AMD_CG_SUPPORT_GFX_CP_LS */
+	data = RREG32(mmCP_MEM_SLP_CNTL);
+	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
+		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
+}
+
 static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
 				     uint32_t reg_addr, uint32_t cmd)
 {
@@ -6592,6 +6631,7 @@ static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
 	.post_soft_reset = gfx_v8_0_post_soft_reset,
 	.set_clockgating_state = gfx_v8_0_set_clockgating_state,
 	.set_powergating_state = gfx_v8_0_set_powergating_state,
+	.clockgating_state = gfx_v8_0_clockgating_state,
 };
 
 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
-- 
2.7.4

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[PART1 PATCH 4/8] drm/amdgpu: add clockgating_state method for gmc v8

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 2f36417..6f46562 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1496,6 +1496,21 @@ static int gmc_v8_0_set_powergating_state(void *handle,
 	return 0;
 }
 
+static void gmc_v8_0_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int data;
+
+	/* AMD_CG_SUPPORT_MC_MGCG */
+	data = RREG32(mmMC_HUB_MISC_HUB_CG);
+	if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
+		*flags |= AMD_CG_SUPPORT_MC_MGCG;
+
+	/* AMD_CG_SUPPORT_MC_LS */
+	if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
+		*flags |= AMD_CG_SUPPORT_MC_LS;
+}
+
 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
 	.name = "gmc_v8_0",
 	.early_init = gmc_v8_0_early_init,
@@ -1514,6 +1529,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
 	.post_soft_reset = gmc_v8_0_post_soft_reset,
 	.set_clockgating_state = gmc_v8_0_set_clockgating_state,
 	.set_powergating_state = gmc_v8_0_set_powergating_state,
+	.clockgating_state = gmc_v8_0_clockgating_state,
 };
 
 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
-- 
2.7.4

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[PART1 PATCH 5/8] drm/amdgpu: add clockgating_state method for sdma v3

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 4ca38a1..581f4a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1571,6 +1571,22 @@ static int sdma_v3_0_set_powergating_state(void *handle,
 	return 0;
 }
 
+static void sdma_v3_0_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int data;
+
+	/* AMD_CG_SUPPORT_SDMA_MGCG */
+	data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
+	if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
+		*flags |= AMD_CG_SUPPORT_SDMA_MGCG;
+
+	/* AMD_CG_SUPPORT_SDMA_LS */
+	data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
+	if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
+		*flags |= AMD_CG_SUPPORT_SDMA_LS;
+}
+
 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
 	.name = "sdma_v3_0",
 	.early_init = sdma_v3_0_early_init,
@@ -1589,6 +1605,7 @@ static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
 	.soft_reset = sdma_v3_0_soft_reset,
 	.set_clockgating_state = sdma_v3_0_set_clockgating_state,
 	.set_powergating_state = sdma_v3_0_set_powergating_state,
+	.clockgating_state = sdma_v3_0_clockgating_state,
 };
 
 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
-- 
2.7.4

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[PART1 PATCH 6/8] drm/amdgpu: add clockgating_state method for vi common

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 2523f31..88e3fd7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1243,6 +1243,32 @@ static int vi_common_set_powergating_state(void *handle,
 	return 0;
 }
 
+static void vi_common_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int data;
+
+	/* AMD_CG_SUPPORT_BIF_LS */
+	data = RREG32_PCIE(ixPCIE_CNTL2);
+	if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
+		*flags |= AMD_CG_SUPPORT_BIF_LS;
+
+	/* AMD_CG_SUPPORT_HDP_LS */
+	data = RREG32(mmHDP_MEM_POWER_LS);
+	if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
+		*flags |= AMD_CG_SUPPORT_HDP_LS;
+
+	/* AMD_CG_SUPPORT_HDP_MGCG */
+	data = RREG32(mmHDP_HOST_PATH_CNTL);
+	if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
+		*flags |= AMD_CG_SUPPORT_HDP_MGCG;
+
+	/* AMD_CG_SUPPORT_ROM_MGCG */
+	data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
+	if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
+		*flags |= AMD_CG_SUPPORT_ROM_MGCG;
+}
+
 static const struct amd_ip_funcs vi_common_ip_funcs = {
 	.name = "vi_common",
 	.early_init = vi_common_early_init,
@@ -1258,6 +1284,7 @@ static const struct amd_ip_funcs vi_common_ip_funcs = {
 	.soft_reset = vi_common_soft_reset,
 	.set_clockgating_state = vi_common_set_clockgating_state,
 	.set_powergating_state = vi_common_set_powergating_state,
+	.clockgating_state = vi_common_clockgating_state,
 };
 
 static const struct amdgpu_ip_block_version vi_common_ip_block =
-- 
2.7.4

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[PART1 PATCH 7/8] drm/amdgpu: add clockgating_state method for uvd v5&v6

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 12 ++++++++++++
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 ++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 03a35d9..9f1d8f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -793,6 +793,17 @@ static int uvd_v5_0_set_powergating_state(void *handle,
 	}
 }
 
+static void uvd_v5_0_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int data;
+
+	/* AMD_CG_SUPPORT_UVD_MGCG */
+	data = RREG32(mmUVD_CGC_CTRL);
+	if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
+		*flags |= AMD_CG_SUPPORT_UVD_MGCG;
+}
+
 static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
 	.name = "uvd_v5_0",
 	.early_init = uvd_v5_0_early_init,
@@ -808,6 +819,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
 	.soft_reset = uvd_v5_0_soft_reset,
 	.set_clockgating_state = uvd_v5_0_set_clockgating_state,
 	.set_powergating_state = uvd_v5_0_set_powergating_state,
+	.clockgating_state = uvd_v5_0_clockgating_state,
 };
 
 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 8779d4b..bccf2b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1001,6 +1001,17 @@ static int uvd_v6_0_set_powergating_state(void *handle,
 	}
 }
 
+static void uvd_v6_0_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int data;
+
+	/* AMD_CG_SUPPORT_UVD_MGCG */
+	data = RREG32(mmUVD_CGC_CTRL);
+	if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
+		*flags |= AMD_CG_SUPPORT_UVD_MGCG;
+}
+
 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
 	.name = "uvd_v6_0",
 	.early_init = uvd_v6_0_early_init,
@@ -1019,6 +1030,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
 	.post_soft_reset = uvd_v6_0_post_soft_reset,
 	.set_clockgating_state = uvd_v6_0_set_clockgating_state,
 	.set_powergating_state = uvd_v6_0_set_powergating_state,
+	.clockgating_state = uvd_v6_0_clockgating_state,
 };
 
 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
-- 
2.7.4

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[PART1 PATCH 8/8] drm/amdgpu: add clockgating_state method for vce v3

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 35ff1c3..15742e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -781,6 +781,23 @@ static int vce_v3_0_set_powergating_state(void *handle,
 		return vce_v3_0_start(adev);
 }
 
+static void vce_v3_0_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int data;
+
+	mutex_lock(&adev->grbm_idx_mutex);
+
+	WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
+
+	/* AMD_CG_SUPPORT_VCE_MGCG */
+	data = RREG32(mmVCE_CLOCK_GATING_A);
+	if (data & (0x04 << 4))
+		*flags |= AMD_CG_SUPPORT_VCE_MGCG;
+
+	mutex_unlock(&adev->grbm_idx_mutex);
+}
+
 static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 		struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
 {
@@ -832,6 +849,7 @@ static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
 	.post_soft_reset = vce_v3_0_post_soft_reset,
 	.set_clockgating_state = vce_v3_0_set_clockgating_state,
 	.set_powergating_state = vce_v3_0_set_powergating_state,
+	.clockgating_state = vce_v3_0_clockgating_state,
 };
 
 static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
-- 
2.7.4

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RE: [PART1 PATCH 0/8] Introduce a method to get clock gating status dynamically

[Deucher, Alexander]

> -----Original Message-----
> From: Huang Rui [mailto:ray.huang@amd.com]
> Sent: Thursday, January 05, 2017 8:50 AM
> To: Deucher, Alexander; amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex; Mao, David; Fu, Ping; Zhang, Hawking; Huang, Ray
> Subject: [PART1 PATCH 0/8] Introduce a method to get clock gating status
> dynamically
> 
> This series patches implement to get the clock gating status
> dynamically into debugfs. User will enter profiling mode to runtime
> disable clockgating, so it needs an interface to expose clock gating
> states. Part 1 works for VI, I will implement it on CI/SI in following
> days.

Patches 1-6:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Patches 7, 8:
I'm not sure if the UVD and VCE status registers are available if the blocks are powergated.  Reading them back while powergated can cause a hang.  Might want to check the PG sw state before reading back the registers.

Alex

> 
> Here is the example on Fiji:
> 
> root@jenkins-All-Series:/home/jenkins# cat
> /sys/kernel/debug/dri/64/amdgpu_pm_info
> Clock Gating Flags Mask: 0x3dfff
>         Medium Grain Clock Gating: On
>         Medium Grain memory Light Sleep: On
>         Coarse Grain Clock Gating: On
>         Coarse Grain memory Light Sleep: On
>         Coarse Grain Tree Shader: On
>         Coarse Grain Tree Shader Light Sleep: On
>         Command Processor Light Sleep: On
>         Run List Controller Light Sleep: On
>         Memory Controller Light Sleep: On
>         Memory Controller Medium Grain Clock Gating: On
>         System Direct Memory Access Light Sleep: On
>         System Direct Memory Access Medium Grain Clock Gating: On
>         Bus Interface Light Sleep: On
>         Universal Video Decoder Medium Grain Clock Gating: Off
>         Video Coding Engine Medium Grain Clock Gating: On
>         Host Data Path Light Sleep: On
>         Host Data Path Medium Grain Clock Gating: On
>         Rom Medium Grain Clock Gating: On
> ...
> 
> Thanks,
> Rui
> 
> Huang Rui (8):
>   drm/amdgpu: introduce an interface to get clock gating status
>     dynamically
>   drm/amdgpu: add parse clock gating state
>   drm/amdgpu: add clockgating_state method for gfx v8
>   drm/amdgpu: add clockgating_state method for gmc v8
>   drm/amdgpu: add clockgating_state method for sdma v3
>   drm/amdgpu: add clockgating_state method for vi common
>   drm/amdgpu: add clockgating_state method for uvd v5&v6
>   drm/amdgpu: add clockgating_state method for vce v3
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 99
> ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c      | 40 ++++++++++++
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      | 16 +++++
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c     | 17 +++++
>  drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c      | 12 ++++
>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c      | 12 ++++
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c      | 18 ++++++
>  drivers/gpu/drm/amd/amdgpu/vi.c            | 27 ++++++++
>  drivers/gpu/drm/amd/include/amd_shared.h   |  2 +
>  11 files changed, 256 insertions(+)
> 
> --
> 2.7.4

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Re: [PART1 PATCH 0/8] Introduce a method to get clock gating status dynamically

[StDenis, Tom]

[-- Attachment #1.1: Type: text/plain, Size: 4242 bytes --]

Some of them are part of AON tiles but are unstable during PM switches.  That's why the debugfs mmio entry supports a PM lock.


So they might be readable while powered off but unstable if the firmware is in the middle of a PM switch.


Tom


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, January 5, 2017 10:40
To: Huang, Ray; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Huang, Ray; Zhang, Hawking; Zhu, Rex; Fu, Ping; Mao, David
Subject: RE: [PART1 PATCH 0/8] Introduce a method to get clock gating status dynamically

> -----Original Message-----
> From: Huang Rui [mailto:ray.huang-5C7GfCeVMHo@public.gmane.org]
> Sent: Thursday, January 05, 2017 8:50 AM
> To: Deucher, Alexander; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> Cc: Zhu, Rex; Mao, David; Fu, Ping; Zhang, Hawking; Huang, Ray
> Subject: [PART1 PATCH 0/8] Introduce a method to get clock gating status
> dynamically
>
> This series patches implement to get the clock gating status
> dynamically into debugfs. User will enter profiling mode to runtime
> disable clockgating, so it needs an interface to expose clock gating
> states. Part 1 works for VI, I will implement it on CI/SI in following
> days.

Patches 1-6:
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>

Patches 7, 8:
I'm not sure if the UVD and VCE status registers are available if the blocks are powergated.  Reading them back while powergated can cause a hang.  Might want to check the PG sw state before reading back the registers.

Alex

>
> Here is the example on Fiji:
>
> root@jenkins-All-Series:/home/jenkins# cat
> /sys/kernel/debug/dri/64/amdgpu_pm_info
> Clock Gating Flags Mask: 0x3dfff
>         Medium Grain Clock Gating: On
>         Medium Grain memory Light Sleep: On
>         Coarse Grain Clock Gating: On
>         Coarse Grain memory Light Sleep: On
>         Coarse Grain Tree Shader: On
>         Coarse Grain Tree Shader Light Sleep: On
>         Command Processor Light Sleep: On
>         Run List Controller Light Sleep: On
>         Memory Controller Light Sleep: On
>         Memory Controller Medium Grain Clock Gating: On
>         System Direct Memory Access Light Sleep: On
>         System Direct Memory Access Medium Grain Clock Gating: On
>         Bus Interface Light Sleep: On
>         Universal Video Decoder Medium Grain Clock Gating: Off
>         Video Coding Engine Medium Grain Clock Gating: On
>         Host Data Path Light Sleep: On
>         Host Data Path Medium Grain Clock Gating: On
>         Rom Medium Grain Clock Gating: On
> ...
>
> Thanks,
> Rui
>
> Huang Rui (8):
>   drm/amdgpu: introduce an interface to get clock gating status
>     dynamically
>   drm/amdgpu: add parse clock gating state
>   drm/amdgpu: add clockgating_state method for gfx v8
>   drm/amdgpu: add clockgating_state method for gmc v8
>   drm/amdgpu: add clockgating_state method for sdma v3
>   drm/amdgpu: add clockgating_state method for vi common
>   drm/amdgpu: add clockgating_state method for uvd v5&v6
>   drm/amdgpu: add clockgating_state method for vce v3
>
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 99
> ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c      | 40 ++++++++++++
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      | 16 +++++
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c     | 17 +++++
>  drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c      | 12 ++++
>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c      | 12 ++++
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c      | 18 ++++++
>  drivers/gpu/drm/amd/amdgpu/vi.c            | 27 ++++++++
>  drivers/gpu/drm/amd/include/amd_shared.h   |  2 +
>  11 files changed, 256 insertions(+)
>
> --
> 2.7.4

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Re: [PART1 PATCH 2/8] drm/amdgpu: add parse clock gating state

[Felix Kuehling]

This could be done with much less code duplication:

	static const struct {
		u32 flag;
		const char *name;
	} clocks[] = {
		{AMD_CG_SUPPORT_GFX_MGCG, "Medium Grain Clock Gating"},
		{AMD_CG_SUPPORT_GFX_MGLS, "Medium Grain memory Light Sleep"},
		...
		{0, NULL}
	};

	for (i = 0; clocks[i].flag; i++)
		seq_printf(m, "\t%s: %s\n",
			clocks[i].name,
			(flags & clocks[i].flag) ? "On" : "Off");

Regards,
  Felix

On 17-01-05 08:49 AM, Huang Rui wrote:
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 95 ++++++++++++++++++++++++++++++++++
>  1 file changed, 95 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 7aa561d..431bae4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1536,6 +1536,99 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
>  	return 0;
>  }
>  
> +static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
> +{
> +       if (flags & AMD_CG_SUPPORT_GFX_MGCG)
> +               seq_printf(m, "\tMedium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tMedium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_MGLS)
> +               seq_printf(m, "\tMedium Grain memory Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tMedium Grain memory Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_CGCG)
> +               seq_printf(m, "\tCoarse Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tCoarse Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_CGLS)
> +               seq_printf(m, "\tCoarse Grain memory Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tCoarse Grain memory Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_CGTS)
> +               seq_printf(m, "\tCoarse Grain Tree Shader: On\n");
> +       else
> +               seq_printf(m, "\tCoarse Grain Tree Shader: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_CGTS_LS)
> +               seq_printf(m, "\tCoarse Grain Tree Shader Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tCoarse Grain Tree Shader Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_CP_LS)
> +               seq_printf(m, "\tCommand Processor Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tCommand Processor Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_RLC_LS)
> +               seq_printf(m, "\tRun List Controller Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tRun List Controller Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_MC_LS)
> +               seq_printf(m, "\tMemory Controller Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tMemory Controller Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_MC_MGCG)
> +               seq_printf(m, "\tMemory Controller Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tMemory Controller Medium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_SDMA_LS)
> +               seq_printf(m, "\tSystem Direct Memory Access Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tSystem Direct Memory Access Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_SDMA_MGCG)
> +               seq_printf(m, "\tSystem Direct Memory Access Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tSystem Direct Memory Access Medium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_BIF_LS)
> +               seq_printf(m, "\tBus Interface Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tBus Interface Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_UVD_MGCG)
> +               seq_printf(m, "\tUniversal Video Decoder Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tUniversal Video Decoder Medium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_VCE_MGCG)
> +               seq_printf(m, "\tVideo Coding Engine Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tVideo Coding Engine Medium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_HDP_LS)
> +               seq_printf(m, "\tHost Data Path Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tHost Data Path Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_HDP_MGCG)
> +               seq_printf(m, "\tHost Data Path Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tHost Data Path Medium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_ROM_MGCG)
> +               seq_printf(m, "\tRom Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tRom Medium Grain Clock Gating: Off\n");
> +}
> +
>  static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
>  {
>  	struct drm_info_node *node = (struct drm_info_node *) m->private;
> @@ -1546,6 +1639,8 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
>  
>  	amdgpu_clockgating_state(adev, &flags);
>  	seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
> +	amdgpu_parse_cg_state(m, flags);
> +	seq_printf(m, "\n");
>  
>  	if (!adev->pm.dpm_enabled) {
>  		seq_printf(m, "dpm not enabled\n");

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Re: [PART1 PATCH 2/8] drm/amdgpu: add parse clock gating state

[William Lewis]

Minor nit.

s/Grain/Grained/

Also, amdgpu_clockgating_state as a function name does not seem explicit 
enough as to what it's doing, maybe amdgpu_get_clockgating_state?

On 01/05/17 07:49, Huang Rui wrote:
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 95 ++++++++++++++++++++++++++++++++++
>   1 file changed, 95 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 7aa561d..431bae4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1536,6 +1536,99 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
>   	return 0;
>   }
>   
> +static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
> +{
> +       if (flags & AMD_CG_SUPPORT_GFX_MGCG)
> +               seq_printf(m, "\tMedium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tMedium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_MGLS)
> +               seq_printf(m, "\tMedium Grain memory Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tMedium Grain memory Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_CGCG)
> +               seq_printf(m, "\tCoarse Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tCoarse Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_CGLS)
> +               seq_printf(m, "\tCoarse Grain memory Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tCoarse Grain memory Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_CGTS)
> +               seq_printf(m, "\tCoarse Grain Tree Shader: On\n");
> +       else
> +               seq_printf(m, "\tCoarse Grain Tree Shader: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_CGTS_LS)
> +               seq_printf(m, "\tCoarse Grain Tree Shader Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tCoarse Grain Tree Shader Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_CP_LS)
> +               seq_printf(m, "\tCommand Processor Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tCommand Processor Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_GFX_RLC_LS)
> +               seq_printf(m, "\tRun List Controller Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tRun List Controller Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_MC_LS)
> +               seq_printf(m, "\tMemory Controller Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tMemory Controller Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_MC_MGCG)
> +               seq_printf(m, "\tMemory Controller Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tMemory Controller Medium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_SDMA_LS)
> +               seq_printf(m, "\tSystem Direct Memory Access Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tSystem Direct Memory Access Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_SDMA_MGCG)
> +               seq_printf(m, "\tSystem Direct Memory Access Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tSystem Direct Memory Access Medium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_BIF_LS)
> +               seq_printf(m, "\tBus Interface Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tBus Interface Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_UVD_MGCG)
> +               seq_printf(m, "\tUniversal Video Decoder Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tUniversal Video Decoder Medium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_VCE_MGCG)
> +               seq_printf(m, "\tVideo Coding Engine Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tVideo Coding Engine Medium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_HDP_LS)
> +               seq_printf(m, "\tHost Data Path Light Sleep: On\n");
> +       else
> +               seq_printf(m, "\tHost Data Path Light Sleep: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_HDP_MGCG)
> +               seq_printf(m, "\tHost Data Path Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tHost Data Path Medium Grain Clock Gating: Off\n");
> +
> +       if (flags & AMD_CG_SUPPORT_ROM_MGCG)
> +               seq_printf(m, "\tRom Medium Grain Clock Gating: On\n");
> +       else
> +               seq_printf(m, "\tRom Medium Grain Clock Gating: Off\n");
> +}
> +
>   static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
>   {
>   	struct drm_info_node *node = (struct drm_info_node *) m->private;
> @@ -1546,6 +1639,8 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
>   
>   	amdgpu_clockgating_state(adev, &flags);
>   	seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
> +	amdgpu_parse_cg_state(m, flags);
> +	seq_printf(m, "\n");
>   
>   	if (!adev->pm.dpm_enabled) {
>   		seq_printf(m, "dpm not enabled\n");

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Re: [PART1 PATCH 0/8] Introduce a method to get clock gating status dynamically

[Huang Rui]

On Thu, Jan 05, 2017 at 11:40:33PM +0800, Deucher, Alexander wrote:
> > -----Original Message-----
> > From: Huang Rui [mailto:ray.huang@amd.com]
> > Sent: Thursday, January 05, 2017 8:50 AM
> > To: Deucher, Alexander; amd-gfx@lists.freedesktop.org
> > Cc: Zhu, Rex; Mao, David; Fu, Ping; Zhang, Hawking; Huang, Ray
> > Subject: [PART1 PATCH 0/8] Introduce a method to get clock gating status
> > dynamically
> > 
> > This series patches implement to get the clock gating status
> > dynamically into debugfs. User will enter profiling mode to runtime
> > disable clockgating, so it needs an interface to expose clock gating
> > states. Part 1 works for VI, I will implement it on CI/SI in following
> > days.
> 
> Patches 1-6:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> 
> Patches 7, 8:
> I'm not sure if the UVD and VCE status registers are available if the blocks are powergated.  Reading them back while powergated can cause a hang.  Might want to check the PG sw state before reading back the registers.
> 

OK, so I should check whether UVD/VCE is in AMD_PG_STATE_UNGATE before
reading the registers.

Thanks,
Rui
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Re: [PART1 PATCH 2/8] drm/amdgpu: add parse clock gating state

[Huang Rui]

On Thu, Jan 05, 2017 at 11:33:38AM -0500, Felix Kuehling wrote:
> This could be done with much less code duplication:
> 
> 	static const struct {
> 		u32 flag;
> 		const char *name;
> 	} clocks[] = {
> 		{AMD_CG_SUPPORT_GFX_MGCG, "Medium Grain Clock Gating"},
> 		{AMD_CG_SUPPORT_GFX_MGLS, "Medium Grain memory Light Sleep"},
> 		...
> 		{0, NULL}
> 	};
> 
> 	for (i = 0; clocks[i].flag; i++)
> 		seq_printf(m, "\t%s: %s\n",
> 			clocks[i].name,
> 			(flags & clocks[i].flag) ? "On" : "Off");
> 

Looks better. Thank you.

Thanks,
Rui
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Re: [PART1 PATCH 2/8] drm/amdgpu: add parse clock gating state

[Huang Rui]

On Thu, Jan 05, 2017 at 04:34:45PM +0000, William Lewis wrote:
> Minor nit.
> 
> s/Grain/Grained/
> 
> Also, amdgpu_clockgating_state as a function name does not seem explicit 
> enough as to what it's doing, maybe amdgpu_get_clockgating_state?
> 

Yep, thanks to reminder.

Thanks,
Rui
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