[PATCH v3 0/5] Expand kernel-doc with more generic details and info about ring buffers

[PATCH v3 0/5] Expand kernel-doc with more generic details and info about ring buffers

[Rodrigo Siqueira]

Lately, I have been part of multiple discussions around GPU recovery and
other concepts associated with GFX/Compute. Most of the debate is spread
around GitLab issues, emails, and some meeting conversations. This
patchset aims to consolidate all that information into a single
kernel-doc, which can be collaboratively improved and shared with other
people.

In this series, you will find new amdgpu glossary entries, more details
about the IPs' interconnections, and a description of the ring buffer.
This series includes multiple SVG diagrams; for this reason, it might be
good to apply this series locally. However, if you want to check all the
images quickly, check the links below:

- https://people.igalia.com/siqueira/kernel-doc-imgs/v3/amd_overview_block.svg
- https://people.igalia.com/siqueira/kernel-doc-imgs/v3/gfx_pipeline_seq.svg
- https://people.igalia.com/siqueira/kernel-doc-imgs/v3/no_enforce_isolation.svg
- https://people.igalia.com/siqueira/kernel-doc-imgs/v3/enforce_isolation.svg
- https://people.igalia.com/siqueira/kernel-doc-imgs/v3/ring_buffers.svg

Finally, keep in mind that I tried to fill in some gaps between
information, and hopefully, my description matches the reality.

Changes since V2:
 - Remove the unnecessary diagram.
 - Remove the excessive details about hardware behavior that are not
   useful for a driver developer.
 - Remove some wrong information.
 - Rewrite many parts of the ring buffer description.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>

Thanks

Rodrigo Siqueira (5):
  drm/amdgpu: Expand kernel-doc in amdgpu_ring
  Documentation/gpu: Add new glossary entries from UMR
  Documentation/gpu: Expand generic block information
  Documentation/gpu: Add more information about GC
  Documentation/gpu: Add documentation about ring buffer

 .../gpu/amdgpu/amd_overview_block.svg         |  674 +++++++
 Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   24 +
 Documentation/gpu/amdgpu/driver-core.rst      |   25 +
 .../gpu/amdgpu/enforce_isolation.svg          |  654 +++++++
 Documentation/gpu/amdgpu/gc/index.rst         |   24 +-
 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg |  413 +++++
 Documentation/gpu/amdgpu/index.rst            |    1 +
 .../gpu/amdgpu/no_enforce_isolation.svg       |  707 +++++++
 Documentation/gpu/amdgpu/ring-buffer.rst      |   91 +
 Documentation/gpu/amdgpu/ring_buffers.svg     | 1633 +++++++++++++++++
 Documentation/gpu/amdgpu/userq.rst            |    2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c      |   15 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h      |    2 +
 13 files changed, 4251 insertions(+), 14 deletions(-)
 create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
 create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
 create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
 create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
 create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
 create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg

-- 
2.51.0

[PATCH v3 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring

[Rodrigo Siqueira]

Expand the kernel-doc about amdgpu_ring and add some tiny improvements.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 15 ++++++++++++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  2 ++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 5ec5c3ff22bb..29de8dbe2917 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -75,8 +75,16 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
  * @ring: amdgpu_ring structure holding ring information
  * @ndw: number of dwords to allocate in the ring buffer
  *
- * Allocate @ndw dwords in the ring buffer (all asics).
- * Returns 0 on success, error on failure.
+ * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When
+ * inspecting the code, you may encounter places where this function is invoked
+ * like this: amdgpu_ring_alloc(ring, X + Y + Z), where X, Y, and Z are integer
+ * numbers. The idea of using each integer addition instead of the final result
+ * is to explicitly indicate each block of operation that will be inserted into
+ * the ring.
+ *
+ * Returns:
+ * 0 on success, otherwise -ENOMEM if it tries to allocate more than the
+ * maximum dword allowed for one submission.
  */
 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
 {
@@ -122,7 +130,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
 		ring->funcs->begin_use(ring);
 }
 
-/** amdgpu_ring_insert_nop - insert NOP packets
+/**
+ * amdgpu_ring_insert_nop - insert NOP packets
  *
  * @ring: amdgpu_ring structure holding ring information
  * @count: the number of NOP packets to insert
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 87b962df5460..e83589619a92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
 #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
 #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
+
+/* Ensure the execution in case of preemption or reset */
 #define AMDGPU_FENCE_FLAG_EXEC          (1 << 3)
 
 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
-- 
2.51.0

Re: [PATCH v3 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring

[Alex Deucher]

On Mon, Oct 20, 2025 at 4:06 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> Expand the kernel-doc about amdgpu_ring and add some tiny improvements.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 15 ++++++++++++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  2 ++
>  2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index 5ec5c3ff22bb..29de8dbe2917 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -75,8 +75,16 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
>   * @ring: amdgpu_ring structure holding ring information
>   * @ndw: number of dwords to allocate in the ring buffer
>   *
> - * Allocate @ndw dwords in the ring buffer (all asics).
> - * Returns 0 on success, error on failure.
> + * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When
> + * inspecting the code, you may encounter places where this function is invoked
> + * like this: amdgpu_ring_alloc(ring, X + Y + Z), where X, Y, and Z are integer
> + * numbers. The idea of using each integer addition instead of the final result
> + * is to explicitly indicate each block of operation that will be inserted into
> + * the ring.
> + *
> + * Returns:
> + * 0 on success, otherwise -ENOMEM if it tries to allocate more than the
> + * maximum dword allowed for one submission.
>   */
>  int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
>  {
> @@ -122,7 +130,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
>                 ring->funcs->begin_use(ring);
>  }
>
> -/** amdgpu_ring_insert_nop - insert NOP packets
> +/**
> + * amdgpu_ring_insert_nop - insert NOP packets
>   *
>   * @ring: amdgpu_ring structure holding ring information
>   * @count: the number of NOP packets to insert
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 87b962df5460..e83589619a92 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
>  #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
>  #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
>  #define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
> +
> +/* Ensure the execution in case of preemption or reset */
>  #define AMDGPU_FENCE_FLAG_EXEC          (1 << 3)
>
>  #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
> --
> 2.51.0
>

Re: [PATCH v3 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring

[Timur Kristóf]

On 10/20/25 21:38, Rodrigo Siqueira wrote:
> Expand the kernel-doc about amdgpu_ring and add some tiny improvements.
> 
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 15 ++++++++++++---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  2 ++
>   2 files changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index 5ec5c3ff22bb..29de8dbe2917 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -75,8 +75,16 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
>    * @ring: amdgpu_ring structure holding ring information
>    * @ndw: number of dwords to allocate in the ring buffer
>    *
> - * Allocate @ndw dwords in the ring buffer (all asics).
> - * Returns 0 on success, error on failure.
> + * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When
> + * inspecting the code, you may encounter places where this function is invoked
> + * like this: amdgpu_ring_alloc(ring, X + Y + Z), where X, Y, and Z are integer
> + * numbers. The idea of using each integer addition instead of the final result
> + * is to explicitly indicate each block of operation that will be inserted into
> + * the ring.

To clarify this further, I recommend using the term "packet" instead of 
"block of operation".

> + *
> + * Returns:
> + * 0 on success, otherwise -ENOMEM if it tries to allocate more than the
> + * maximum dword allowed for one submission.
>    */
>   int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
>   {
> @@ -122,7 +130,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
>   		ring->funcs->begin_use(ring);
>   }
>   
> -/** amdgpu_ring_insert_nop - insert NOP packets
> +/**
> + * amdgpu_ring_insert_nop - insert NOP packets
>    *
>    * @ring: amdgpu_ring structure holding ring information
>    * @count: the number of NOP packets to insert
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 87b962df5460..e83589619a92 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
>   #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
>   #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
>   #define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
> +
> +/* Ensure the execution in case of preemption or reset */
>   #define AMDGPU_FENCE_FLAG_EXEC          (1 << 3)
>   
>   #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)

Re: [PATCH v3 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring

[Rodrigo Siqueira]

On 10/21, Timur Kristóf wrote:
> 
> 
> On 10/20/25 21:38, Rodrigo Siqueira wrote:
> > Expand the kernel-doc about amdgpu_ring and add some tiny improvements.
> > 
> > Cc: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Christian König <christian.koenig@amd.com>
> > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 15 ++++++++++++---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  2 ++
> >   2 files changed, 14 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > index 5ec5c3ff22bb..29de8dbe2917 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > @@ -75,8 +75,16 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
> >    * @ring: amdgpu_ring structure holding ring information
> >    * @ndw: number of dwords to allocate in the ring buffer
> >    *
> > - * Allocate @ndw dwords in the ring buffer (all asics).
> > - * Returns 0 on success, error on failure.
> > + * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When
> > + * inspecting the code, you may encounter places where this function is invoked
> > + * like this: amdgpu_ring_alloc(ring, X + Y + Z), where X, Y, and Z are integer
> > + * numbers. The idea of using each integer addition instead of the final result
> > + * is to explicitly indicate each block of operation that will be inserted into
> > + * the ring.
> 
> To clarify this further, I recommend using the term "packet" instead of
> "block of operation".

I'll make this change for the V4 version.

Thanks Alex and Tímur.

> 
> > + *
> > + * Returns:
> > + * 0 on success, otherwise -ENOMEM if it tries to allocate more than the
> > + * maximum dword allowed for one submission.
> >    */
> >   int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
> >   {
> > @@ -122,7 +130,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
> >   		ring->funcs->begin_use(ring);
> >   }
> > -/** amdgpu_ring_insert_nop - insert NOP packets
> > +/**
> > + * amdgpu_ring_insert_nop - insert NOP packets
> >    *
> >    * @ring: amdgpu_ring structure holding ring information
> >    * @count: the number of NOP packets to insert
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > index 87b962df5460..e83589619a92 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > @@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
> >   #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
> >   #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
> >   #define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
> > +
> > +/* Ensure the execution in case of preemption or reset */
> >   #define AMDGPU_FENCE_FLAG_EXEC          (1 << 3)
> >   #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
> 

-- 
Rodrigo Siqueira

Re: [PATCH v3 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring

[Christian König]

On 10/20/25 21:38, Rodrigo Siqueira wrote:
> Expand the kernel-doc about amdgpu_ring and add some tiny improvements.
> 
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 15 ++++++++++++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  2 ++
>  2 files changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index 5ec5c3ff22bb..29de8dbe2917 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -75,8 +75,16 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
>   * @ring: amdgpu_ring structure holding ring information
>   * @ndw: number of dwords to allocate in the ring buffer
>   *
> - * Allocate @ndw dwords in the ring buffer (all asics).
> - * Returns 0 on success, error on failure.
> + * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When

I would ditch the "it works on all ASICs". That's something we did for radeon because we didn't had the seperation between backend (ASIC dependent) and frontend (ASIC independent code).

You could maybe write "applicable" or "used on all ASICs".

> + * inspecting the code, you may encounter places where this function is invoked
> + * like this: amdgpu_ring_alloc(ring, X + Y + Z), where X, Y, and Z are integer
> + * numbers. The idea of using each integer addition instead of the final result
> + * is to explicitly indicate each block of operation that will be inserted into
> + * the ring.

That still sounds like overkill to me.

Maybe instead write something like "The number of dwords should be the sum of all commands written to the ring".

Regards,
Christian.


> + *
> + * Returns:
> + * 0 on success, otherwise -ENOMEM if it tries to allocate more than the
> + * maximum dword allowed for one submission.
>   */
>  int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
>  {
> @@ -122,7 +130,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
>  		ring->funcs->begin_use(ring);
>  }
>  
> -/** amdgpu_ring_insert_nop - insert NOP packets
> +/**
> + * amdgpu_ring_insert_nop - insert NOP packets
>   *
>   * @ring: amdgpu_ring structure holding ring information
>   * @count: the number of NOP packets to insert
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 87b962df5460..e83589619a92 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
>  #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
>  #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
>  #define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
> +
> +/* Ensure the execution in case of preemption or reset */
>  #define AMDGPU_FENCE_FLAG_EXEC          (1 << 3)
>  
>  #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)

[PATCH v3 2/5] Documentation/gpu: Add new glossary entries from UMR

[Rodrigo Siqueira]

When using UMR, a dashboard is available that displays the CPC, CPF,
CPG, TCP, and UTCL utilization. This commit introduces the meanings of
those acronyms (and others) to the glossary to improve the comprehension
of the UMR dashboard.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21 ++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index 30812d9d53c6..eb72e6f6d4f1 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
     CP
       Command Processor
 
+    CPC
+      Command Processor Compute
+
+    CPF
+      Command Processor Fetch
+
+    CPG
+      Command Processor Graphics
+
     CPLIB
       Content Protection Library
 
@@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
     GMC
       Graphic Memory Controller
 
+    GPR
+      General Purpose Register
+
     GPUVM
       GPU Virtual Memory.  This is the GPU's MMU.  The GPU supports multiple
       virtual address spaces that can be in flight at any given time.  These
@@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
       table for use by the kernel driver or into per process GPUVM page tables
       for application usage.
 
+    GWS
+      Global Wave Syncs
+
     IH
       Interrupt Handler
 
@@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core at
     TC
       Texture Cache
 
+    TCP (AMDGPU)
+      Texture Cache Processing
+
     TOC
       Table of Contents
 
     UMSCH
       User Mode Scheduler
 
+    UTCL
+      Universal Texture Cache Line
+
     UVD
       Unified Video Decoder
 
-- 
2.51.0

Re: [PATCH v3 2/5] Documentation/gpu: Add new glossary entries from UMR

[Alex Deucher]

On Mon, Oct 20, 2025 at 3:47 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> When using UMR, a dashboard is available that displays the CPC, CPF,
> CPG, TCP, and UTCL utilization. This commit introduces the meanings of
> those acronyms (and others) to the glossary to improve the comprehension
> of the UMR dashboard.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
>  Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21 ++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> index 30812d9d53c6..eb72e6f6d4f1 100644
> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
>      CP
>        Command Processor
>
> +    CPC
> +      Command Processor Compute
> +
> +    CPF
> +      Command Processor Fetch
> +
> +    CPG
> +      Command Processor Graphics
> +
>      CPLIB
>        Content Protection Library
>
> @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
>      GMC
>        Graphic Memory Controller
>
> +    GPR
> +      General Purpose Register
> +
>      GPUVM
>        GPU Virtual Memory.  This is the GPU's MMU.  The GPU supports multiple
>        virtual address spaces that can be in flight at any given time.  These
> @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
>        table for use by the kernel driver or into per process GPUVM page tables
>        for application usage.
>
> +    GWS
> +      Global Wave Syncs
> +
>      IH
>        Interrupt Handler
>
> @@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core at
>      TC
>        Texture Cache
>
> +    TCP (AMDGPU)
> +      Texture Cache Processing

I don't recall what the P stands for, but it might be worth calling
out that the texture cache (old name) is basically the path to memory
for shaders.  So it's not just related to textures.  The name is left
over from old designs where shader stages had different cache designs.

> +
>      TOC
>        Table of Contents
>
>      UMSCH
>        User Mode Scheduler
>
> +    UTCL
> +      Universal Texture Cache Line

I think the L is Level.  I.e., it's usually referenced as UTCL2 for
example.  Might want to drop the L?  I think the U might also be
Unified.

Alex

> +
>      UVD
>        Unified Video Decoder
>
> --
> 2.51.0
>

Re: [PATCH v3 2/5] Documentation/gpu: Add new glossary entries from UMR

[Lazar, Lijo]

On 10/21/2025 1:08 AM, Rodrigo Siqueira wrote:
> When using UMR, a dashboard is available that displays the CPC, CPF,
> CPG, TCP, and UTCL utilization. This commit introduces the meanings of
> those acronyms (and others) to the glossary to improve the comprehension
> of the UMR dashboard.
> 
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
>   Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21 ++++++++++++++++++++
>   1 file changed, 21 insertions(+)
> 
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> index 30812d9d53c6..eb72e6f6d4f1 100644
> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
>       CP
>         Command Processor
>   
> +    CPC
> +      Command Processor Compute
> +
> +    CPF
> +      Command Processor Fetch
> +
> +    CPG
> +      Command Processor Graphics
> +
>       CPLIB
>         Content Protection Library
>   
> @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
>       GMC
>         Graphic Memory Controller
>   
> +    GPR
> +      General Purpose Register
> +
>       GPUVM
>         GPU Virtual Memory.  This is the GPU's MMU.  The GPU supports multiple
>         virtual address spaces that can be in flight at any given time.  These
> @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
>         table for use by the kernel driver or into per process GPUVM page tables
>         for application usage.
>   
> +    GWS
> +      Global Wave Syncs

Sync (s is not there).
> +
>       IH
>         Interrupt Handler
>   
> @@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core at
>       TC
>         Texture Cache
>   
> +    TCP (AMDGPU)
> +      Texture Cache Processing

Texture Cache per Pipe - terminology used for L1 cache in old architecture.

> +
>       TOC
>         Table of Contents
>   
>       UMSCH
>         User Mode Scheduler
>   
> +    UTCL
> +      Universal Texture Cache Line

Unified Translation Cache - equivalent of TLB. Has multiple levels, 
hence L may be dropped.

Thanks,
Lijo

> +
>       UVD
>         Unified Video Decoder
>   

Re: [PATCH v3 2/5] Documentation/gpu: Add new glossary entries from UMR

[Rodrigo Siqueira]

On 10/21, Lazar, Lijo wrote:
> 
> 
> On 10/21/2025 1:08 AM, Rodrigo Siqueira wrote:
> > When using UMR, a dashboard is available that displays the CPC, CPF,
> > CPG, TCP, and UTCL utilization. This commit introduces the meanings of
> > those acronyms (and others) to the glossary to improve the comprehension
> > of the UMR dashboard.
> > 
> > Cc: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Christian König <christian.koenig@amd.com>
> > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > ---
> >   Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21 ++++++++++++++++++++
> >   1 file changed, 21 insertions(+)
> > 
> > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > index 30812d9d53c6..eb72e6f6d4f1 100644
> > --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
> >       CP
> >         Command Processor
> > +    CPC
> > +      Command Processor Compute
> > +
> > +    CPF
> > +      Command Processor Fetch
> > +
> > +    CPG
> > +      Command Processor Graphics
> > +
> >       CPLIB
> >         Content Protection Library
> > @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
> >       GMC
> >         Graphic Memory Controller
> > +    GPR
> > +      General Purpose Register
> > +
> >       GPUVM
> >         GPU Virtual Memory.  This is the GPU's MMU.  The GPU supports multiple
> >         virtual address spaces that can be in flight at any given time.  These
> > @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
> >         table for use by the kernel driver or into per process GPUVM page tables
> >         for application usage.
> > +    GWS
> > +      Global Wave Syncs
> 
> Sync (s is not there).

I'll fix it in the V4.

> > +
> >       IH
> >         Interrupt Handler
> > @@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core at
> >       TC
> >         Texture Cache
> > +    TCP (AMDGPU)
> > +      Texture Cache Processing
> 
> Texture Cache per Pipe - terminology used for L1 cache in old architecture.

Alex, Lijo,

How about the following modification for the V4:

TCP (AMDGPU)
  Texture Cache per Pipe. Even though the name "Texture" is part of this
  acronym, the TCP represents the path to memory shaders; i.e., it is not
  related to texture. The name is a leftover from older designs where
  shader stages had different cache designs; it refers to the L1 cache in
  older architectures.

> 
> > +
> >       TOC
> >         Table of Contents
> >       UMSCH
> >         User Mode Scheduler
> > +    UTCL
> > +      Universal Texture Cache Line
> 
> Unified Translation Cache - equivalent of TLB. Has multiple levels, hence L
> may be dropped.

How about the following modification for the V4:

UTC (AMDGPU)
  Unified Translation Cache. UTC is equivalent to TLB. You might see a
  variation of this acronym with L at the end, i.e., UTCL followed by a
  number; L means the cache level (e.g., UTCL1 and UTCL2).

The reason that I kept the L explanation is that UTCL appears in some
parts of the code and also in the UMR gui. Keeping this acronym here can
facilitate code searches and also provide some extra background on the L
part. Is it ok for you?

Thanks Alex/Lijo.

> 
> Thanks,
> Lijo
> 
> > +
> >       UVD
> >         Unified Video Decoder
> 

-- 
Rodrigo Siqueira

Re: [PATCH v3 2/5] Documentation/gpu: Add new glossary entries from UMR

[Alex Deucher]

On Tue, Oct 21, 2025 at 9:25 AM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> On 10/21, Lazar, Lijo wrote:
> >
> >
> > On 10/21/2025 1:08 AM, Rodrigo Siqueira wrote:
> > > When using UMR, a dashboard is available that displays the CPC, CPF,
> > > CPG, TCP, and UTCL utilization. This commit introduces the meanings of
> > > those acronyms (and others) to the glossary to improve the comprehension
> > > of the UMR dashboard.
> > >
> > > Cc: Alex Deucher <alexander.deucher@amd.com>
> > > Cc: Christian König <christian.koenig@amd.com>
> > > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > > ---
> > >   Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21 ++++++++++++++++++++
> > >   1 file changed, 21 insertions(+)
> > >
> > > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > index 30812d9d53c6..eb72e6f6d4f1 100644
> > > --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
> > >       CP
> > >         Command Processor
> > > +    CPC
> > > +      Command Processor Compute
> > > +
> > > +    CPF
> > > +      Command Processor Fetch
> > > +
> > > +    CPG
> > > +      Command Processor Graphics
> > > +
> > >       CPLIB
> > >         Content Protection Library
> > > @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
> > >       GMC
> > >         Graphic Memory Controller
> > > +    GPR
> > > +      General Purpose Register
> > > +
> > >       GPUVM
> > >         GPU Virtual Memory.  This is the GPU's MMU.  The GPU supports multiple
> > >         virtual address spaces that can be in flight at any given time.  These
> > > @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
> > >         table for use by the kernel driver or into per process GPUVM page tables
> > >         for application usage.
> > > +    GWS
> > > +      Global Wave Syncs
> >
> > Sync (s is not there).
>
> I'll fix it in the V4.
>
> > > +
> > >       IH
> > >         Interrupt Handler
> > > @@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core at
> > >       TC
> > >         Texture Cache
> > > +    TCP (AMDGPU)
> > > +      Texture Cache Processing
> >
> > Texture Cache per Pipe - terminology used for L1 cache in old architecture.
>
> Alex, Lijo,
>
> How about the following modification for the V4:
>
> TCP (AMDGPU)
>   Texture Cache per Pipe. Even though the name "Texture" is part of this
>   acronym, the TCP represents the path to memory shaders; i.e., it is not
>   related to texture. The name is a leftover from older designs where
>   shader stages had different cache designs; it refers to the L1 cache in
>   older architectures.
>
> >
> > > +
> > >       TOC
> > >         Table of Contents
> > >       UMSCH
> > >         User Mode Scheduler
> > > +    UTCL
> > > +      Universal Texture Cache Line
> >
> > Unified Translation Cache - equivalent of TLB. Has multiple levels, hence L
> > may be dropped.
>
> How about the following modification for the V4:
>
> UTC (AMDGPU)
>   Unified Translation Cache. UTC is equivalent to TLB. You might see a
>   variation of this acronym with L at the end, i.e., UTCL followed by a
>   number; L means the cache level (e.g., UTCL1 and UTCL2).
>
> The reason that I kept the L explanation is that UTCL appears in some
> parts of the code and also in the UMR gui. Keeping this acronym here can
> facilitate code searches and also provide some extra background on the L
> part. Is it ok for you?

Looks good to me.  Thanks!

Alex

>
> Thanks Alex/Lijo.
>
> >
> > Thanks,
> > Lijo
> >
> > > +
> > >       UVD
> > >         Unified Video Decoder
> >
>
> --
> Rodrigo Siqueira

Re: [PATCH v3 2/5] Documentation/gpu: Add new glossary entries from UMR

[Christian König]

On 10/20/25 21:38, Rodrigo Siqueira wrote:
> When using UMR, a dashboard is available that displays the CPC, CPF,
> CPG, TCP, and UTCL utilization. This commit introduces the meanings of
> those acronyms (and others) to the glossary to improve the comprehension
> of the UMR dashboard.
> 
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
>  Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21 ++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> index 30812d9d53c6..eb72e6f6d4f1 100644
> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
>      CP
>        Command Processor
>  
> +    CPC
> +      Command Processor Compute
> +
> +    CPF
> +      Command Processor Fetch
> +
> +    CPG
> +      Command Processor Graphics
> +
>      CPLIB
>        Content Protection Library
>  
> @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
>      GMC
>        Graphic Memory Controller
>  
> +    GPR
> +      General Purpose Register
> +
>      GPUVM
>        GPU Virtual Memory.  This is the GPU's MMU.  The GPU supports multiple
>        virtual address spaces that can be in flight at any given time.  These
> @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
>        table for use by the kernel driver or into per process GPUVM page tables
>        for application usage.
>  
> +    GWS
> +      Global Wave Syncs
> +
>      IH
>        Interrupt Handler
>  

BTW we are missing an entry for "IV Interrupt Vector (the bytes written by the GPU into IH ring buffer)".

> @@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core at
>      TC
>        Texture Cache
>  
> +    TCP (AMDGPU)
> +      Texture Cache Processing
> +
>      TOC
>        Table of Contents
>  
>      UMSCH
>        User Mode Scheduler
>  
> +    UTCL
> +      Universal Texture Cache Line
> +

Mhm, UTCL0 UTCL1 and UTCL2 are usually Universal Translation Cache Layer 0-2.

That is not even remotely related to texturing (well UTC requests also go through the TC on some HW generations, but that's basically it).

Regards,
Christian.

>      UVD
>        Unified Video Decoder
>  

Re: [PATCH v3 2/5] Documentation/gpu: Add new glossary entries from UMR

[Rodrigo Siqueira]

On 10/28, Christian König wrote:
> On 10/20/25 21:38, Rodrigo Siqueira wrote:
> > When using UMR, a dashboard is available that displays the CPC, CPF,
> > CPG, TCP, and UTCL utilization. This commit introduces the meanings of
> > those acronyms (and others) to the glossary to improve the comprehension
> > of the UMR dashboard.
> > 
> > Cc: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Christian König <christian.koenig@amd.com>
> > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > ---
> >  Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21 ++++++++++++++++++++
> >  1 file changed, 21 insertions(+)
> > 
> > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > index 30812d9d53c6..eb72e6f6d4f1 100644
> > --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
> >      CP
> >        Command Processor
> >  
> > +    CPC
> > +      Command Processor Compute
> > +
> > +    CPF
> > +      Command Processor Fetch
> > +
> > +    CPG
> > +      Command Processor Graphics
> > +
> >      CPLIB
> >        Content Protection Library
> >  
> > @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
> >      GMC
> >        Graphic Memory Controller
> >  
> > +    GPR
> > +      General Purpose Register
> > +
> >      GPUVM
> >        GPU Virtual Memory.  This is the GPU's MMU.  The GPU supports multiple
> >        virtual address spaces that can be in flight at any given time.  These
> > @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
> >        table for use by the kernel driver or into per process GPUVM page tables
> >        for application usage.
> >  
> > +    GWS
> > +      Global Wave Syncs
> > +
> >      IH
> >        Interrupt Handler
> >  
> 
> BTW we are missing an entry for "IV Interrupt Vector (the bytes written by the GPU into IH ring buffer)".
> 
> > @@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core at
> >      TC
> >        Texture Cache
> >  
> > +    TCP (AMDGPU)
> > +      Texture Cache Processing
> > +
> >      TOC
> >        Table of Contents
> >  
> >      UMSCH
> >        User Mode Scheduler
> >  
> > +    UTCL
> > +      Universal Texture Cache Line
> > +
> 
> Mhm, UTCL0 UTCL1 and UTCL2 are usually Universal Translation Cache Layer 0-2.
> 
> That is not even remotely related to texturing (well UTC requests also go through the TC on some HW generations, but that's basically it).

Hi Christian,

I addressed this issue in the V4 version of this series:

https://patchwork.freedesktop.org/patch/683171/?series=153014&rev=4

Thanks

> 
> Regards,
> Christian.
> 
> >      UVD
> >        Unified Video Decoder
> >  
> 

-- 
Rodrigo Siqueira

[PATCH v3 3/5] Documentation/gpu: Expand generic block information

[Rodrigo Siqueira]

This commit expands the overall explanation about AMD GPU IPs by adding
more details about their interconnection. Note that this commit includes
a diagram that provides additional information.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 .../gpu/amdgpu/amd_overview_block.svg         | 674 ++++++++++++++++++
 Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   3 +
 Documentation/gpu/amdgpu/driver-core.rst      |  25 +
 3 files changed, 702 insertions(+)
 create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg

diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg
new file mode 100644
index 000000000000..8d9ae95bd9a5
--- /dev/null
+++ b/Documentation/gpu/amdgpu/amd_overview_block.svg
@@ -0,0 +1,674 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!-- Created with Inkscape (http://www.inkscape.org/) -->
+
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+   sodipodi:docname="amd_overview_block.svg"
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diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index eb72e6f6d4f1..a3f9565d655b 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -227,6 +227,9 @@ we have a dedicated glossary for Display Core at
     TOC
       Table of Contents
 
+    UMC
+      Unified Memory Controller
+
     UMSCH
       User Mode Scheduler
 
diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
index 3ce276272171..13f13e2e5497 100644
--- a/Documentation/gpu/amdgpu/driver-core.rst
+++ b/Documentation/gpu/amdgpu/driver-core.rst
@@ -77,6 +77,31 @@ VCN (Video Core Next)
     decode.  It's exposed to userspace for user mode drivers (VA-API,
     OpenMAX, etc.)
 
+It is important to note that these blocks can interact with each other. The
+picture below illustrates some of the components and their interconnection:
+
+.. kernel-figure:: amd_overview_block.svg
+
+In the diagram, memory-related blocks are represented by a green color. Notice
+that specific IPs have a green block that represents a small hardware block
+named 'hub', which is responsible for interfacing with memory (pre-vega devices
+have a dedicated block for that, named GMC). In the driver code, you can
+identify this component by looking for the suffix hub, for example: gfxhub,
+dchub, mmhub, vmhub, etc. All memory hubs are connected in the UMC, which in
+turn is connected to memory blocks.
+
+There is some level of protection for certain elements in memory, and the PSP
+plays an essential role in this area. For example, when a specific firmware is
+loaded into the memory, PSP takes an action to ensure that the firmware has a
+valid signature. Another use of PSP is to support the TA (e.g., HDCP) and
+encrypted memory via TMZ.
+
+Another IP that deserves attention is the SMU, as it is connected to all the
+other IPs. SMU will help put the GPU in optimal utilization by taking into
+account performance and power consumption. SMU helps other blocks to set up a
+proper clock configuration. Another feature of SMU is the support for resetting
+every component.
+
 .. _pipes-and-queues-description:
 
 GFX, Compute, and SDMA Overall Behavior
-- 
2.51.0

Re: [PATCH v3 3/5] Documentation/gpu: Expand generic block information

[Alex Deucher]

On Mon, Oct 20, 2025 at 3:56 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> This commit expands the overall explanation about AMD GPU IPs by adding
> more details about their interconnection. Note that this commit includes
> a diagram that provides additional information.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
>  .../gpu/amdgpu/amd_overview_block.svg         | 674 ++++++++++++++++++
>  Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   3 +
>  Documentation/gpu/amdgpu/driver-core.rst      |  25 +
>  3 files changed, 702 insertions(+)
>  create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
>
> diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg
> new file mode 100644
> index 000000000000..8d9ae95bd9a5
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/amd_overview_block.svg

Got a link to the diagram anywhere?  These looked good at XDC.

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> +       style="font-style:normal;font-weight:normal;font-size:6.35px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.0690111"
> +       x="4.5742564"
> +       y="165.33046"
> +       id="text43"><tspan
> +         sodipodi:role="line"
> +         x="4.5742559"
> +         y="165.33046"
> +         style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:6.35px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle;fill:#1c241c;stroke-width:0.0690111"
> +         id="tspan43">Memory</tspan></text>
> +    <text
> +       xml:space="preserve"
> +       style="font-style:normal;font-weight:normal;font-size:6.35px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.0690111"
> +       x="212.40446"
> +       y="165.33046"
> +       id="text44"><tspan
> +         sodipodi:role="line"
> +         x="212.40446"
> +         y="165.33046"
> +         style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:6.35px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle;fill:#1c241c;stroke-width:0.0690111"
> +         id="tspan44">Memory</tspan></text>
> +    <text
> +       xml:space="preserve"
> +       style="font-style:normal;font-weight:normal;font-size:6.35px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.0690111"
> +       x="212.40446"
> +       y="84.897125"
> +       id="text45"><tspan
> +         sodipodi:role="line"
> +         x="212.40446"
> +         y="84.897125"
> +         style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:6.35px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle;fill:#1c241c;stroke-width:0.0690111"
> +         id="tspan45">Memory</tspan></text>
> +    <path
> +       style="fill:none;stroke:#00d455;stroke-width:1;stroke-dasharray:1, 1;stroke-dashoffset:0"
> +       d="m 171.56123,77.957755 13.99852,0"
> +       id="path45"
> +       sodipodi:nodetypes="cc" />
> +    <path
> +       style="fill:none;stroke:#00d455;stroke-width:1;stroke-dasharray:1, 1;stroke-dashoffset:0"
> +       d="m 34.639355,77.957755 h 13.99852"
> +       id="path46"
> +       sodipodi:nodetypes="cc" />
> +  </g>
> +</svg>
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> index eb72e6f6d4f1..a3f9565d655b 100644
> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -227,6 +227,9 @@ we have a dedicated glossary for Display Core at
>      TOC
>        Table of Contents
>
> +    UMC
> +      Unified Memory Controller
> +
>      UMSCH
>        User Mode Scheduler
>
> diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
> index 3ce276272171..13f13e2e5497 100644
> --- a/Documentation/gpu/amdgpu/driver-core.rst
> +++ b/Documentation/gpu/amdgpu/driver-core.rst
> @@ -77,6 +77,31 @@ VCN (Video Core Next)
>      decode.  It's exposed to userspace for user mode drivers (VA-API,
>      OpenMAX, etc.)
>
> +It is important to note that these blocks can interact with each other. The
> +picture below illustrates some of the components and their interconnection:
> +
> +.. kernel-figure:: amd_overview_block.svg
> +
> +In the diagram, memory-related blocks are represented by a green color. Notice
> +that specific IPs have a green block that represents a small hardware block
> +named 'hub', which is responsible for interfacing with memory (pre-vega devices
> +have a dedicated block for that, named GMC). In the driver code, you can
> +identify this component by looking for the suffix hub, for example: gfxhub,
> +dchub, mmhub, vmhub, etc. All memory hubs are connected in the UMC, which in

All memory hubs are connected to the UMCs, which in

> +turn is connected to memory blocks.
> +
> +There is some level of protection for certain elements in memory, and the PSP
> +plays an essential role in this area. For example, when a specific firmware is
> +loaded into the memory, PSP takes an action to ensure that the firmware has a
> +valid signature.

It also stores the firmware images in a protected memory area (TMR =
Trusted Memory Area) so the OS or driver can't corrupt it at runtime
after it's been validated.

> Another use of PSP is to support the TA (e.g., HDCP) and

TA = Trusted Application
Basically small application that runs on the trusted processor and
handles a trusted operation.

> +encrypted memory via TMZ.

TMZ (Trusted Memory Zone -- encrypted memory for content protection).

> +
> +Another IP that deserves attention is the SMU, as it is connected to all the
> +other IPs. SMU will help put the GPU in optimal utilization by taking into
> +account performance and power consumption. SMU helps other blocks to set up a
> +proper clock configuration. Another feature of SMU is the support for resetting
> +every component.

How about something like:

Another important IP is the SMU.  It handles reset distribution as
well as clock and power management for all of the IPs on the SoC.

Alex

> +
>  .. _pipes-and-queues-description:
>
>  GFX, Compute, and SDMA Overall Behavior
> --
> 2.51.0
>

Re: [PATCH v3 3/5] Documentation/gpu: Expand generic block information

[Timur Kristóf]

On 10/20/25 22:28, Alex Deucher wrote:
> On Mon, Oct 20, 2025 at 3:56 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>>
>> This commit expands the overall explanation about AMD GPU IPs by adding
>> more details about their interconnection. Note that this commit includes
>> a diagram that provides additional information.
>>
>> Cc: Alex Deucher <alexander.deucher@amd.com>
>> Cc: Christian König <christian.koenig@amd.com>
>> Cc: Timur Kristóf <timur.kristof@gmail.com>
>> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
>> ---
>>   .../gpu/amdgpu/amd_overview_block.svg         | 674 ++++++++++++++++++
>>   Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   3 +
>>   Documentation/gpu/amdgpu/driver-core.rst      |  25 +
>>   3 files changed, 702 insertions(+)
>>   create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
>>
>> diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg
>> new file mode 100644
>> index 000000000000..8d9ae95bd9a5
>> --- /dev/null
>> +++ b/Documentation/gpu/amdgpu/amd_overview_block.svg
> 
> Got a link to the diagram anywhere?  These looked good at XDC.
> 
The cover letter of the series has links to all the diagrams.

Re: [PATCH v3 3/5] Documentation/gpu: Expand generic block information

[Rodrigo Siqueira]

Hi Alex/Lijo,

On 10/20, Alex Deucher wrote:
> On Mon, Oct 20, 2025 at 3:56 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
> >
> > This commit expands the overall explanation about AMD GPU IPs by adding
> > more details about their interconnection. Note that this commit includes
> > a diagram that provides additional information.
> >
> > Cc: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Christian König <christian.koenig@amd.com>
> > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > ---
> >  .../gpu/amdgpu/amd_overview_block.svg         | 674 ++++++++++++++++++
> >  Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   3 +
> >  Documentation/gpu/amdgpu/driver-core.rst      |  25 +
> >  3 files changed, 702 insertions(+)
> >  create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
> >
> > diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg
> > new file mode 100644
> > index 000000000000..8d9ae95bd9a5
> > --- /dev/null
> > +++ b/Documentation/gpu/amdgpu/amd_overview_block.svg
> 
> Got a link to the diagram anywhere?  These looked good at XDC.

After reading your comment in the cover-letter about this diagram, I
made the following modifications:

1. Connect PSP to UMC.
2. Connect PSP to GC.
3. Connect GC to UMC.
4. To avoid confusion, I moved the green block outside each specific IP.
I also changed the explanation about these parts in the text, see it
below.

Here is the new version:

https://people.igalia.com/siqueira/kernel-doc-imgs/v4/amd_overview_block.svg

What do you think?

> 
> > @@ -0,0 +1,674 @@
> > +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
> > +<!-- Created with Inkscape (http://www.inkscape.org/) -->
> > +
> > +<svg

<snip>

> > +</svg>
> > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > index eb72e6f6d4f1..a3f9565d655b 100644
> > --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > @@ -227,6 +227,9 @@ we have a dedicated glossary for Display Core at
> >      TOC
> >        Table of Contents
> >
> > +    UMC
> > +      Unified Memory Controller
> > +
> >      UMSCH
> >        User Mode Scheduler
> >
> > diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
> > index 3ce276272171..13f13e2e5497 100644
> > --- a/Documentation/gpu/amdgpu/driver-core.rst
> > +++ b/Documentation/gpu/amdgpu/driver-core.rst
> > @@ -77,6 +77,31 @@ VCN (Video Core Next)
> >      decode.  It's exposed to userspace for user mode drivers (VA-API,
> >      OpenMAX, etc.)
> >
> > +It is important to note that these blocks can interact with each other. The
> > +picture below illustrates some of the components and their interconnection:
> > +
> > +.. kernel-figure:: amd_overview_block.svg
> > +
> > +In the diagram, memory-related blocks are represented by a green color. Notice
> > +that specific IPs have a green block that represents a small hardware block
> > +named 'hub', which is responsible for interfacing with memory (pre-vega devices
> > +have a dedicated block for that, named GMC). In the driver code, you can
> > +identify this component by looking for the suffix hub, for example: gfxhub,
> > +dchub, mmhub, vmhub, etc. All memory hubs are connected in the UMC, which in
> 
> All memory hubs are connected to the UMCs, which in

Based on Lijo's comment and Alex's comment in the cover-latter, I
rewrote this paragraph to:

In the diagram, memory-related blocks are shown in green. Notice that
specific IPs have a green square that represents a small hardware block
named 'hub', which is responsible for interfacing with memory. All
memory hubs are connected in the UMCs, which in turn are connected to
memory blocks. As a note, pre-vega devices have a dedicated block for
the Graphic Memory Controller (GMC), which was replaced by UMC in new
architectures. In the driver code, you can identify this component by
looking for the suffix hub, for example: gfxhub, dchub, mmhub, vmhub,
etc. Keep in mind that the component's interaction with the memory block
may vary across architectures. For example, on Navi and newer, GC and
SDMA are both attached to GCHUB; on pre-Navi, SDMA goes through MMHUB;
VCN, JPEG, and VPE go through MMHUB; DCN goes through DCHUB.

What do you think?

Also, keep in mind that this text is part of the below page that already
have some comments about GMC.

https://origin.kernel.org/doc/html/latest/gpu/amdgpu/driver-core.html

> 
> > +turn is connected to memory blocks.
> > +
> > +There is some level of protection for certain elements in memory, and the PSP
> > +plays an essential role in this area. For example, when a specific firmware is
> > +loaded into the memory, PSP takes an action to ensure that the firmware has a
> > +valid signature.
> 
> It also stores the firmware images in a protected memory area (TMR =
> Trusted Memory Area) so the OS or driver can't corrupt it at runtime
> after it's been validated.
> 
> > Another use of PSP is to support the TA (e.g., HDCP) and
> 
> TA = Trusted Application
> Basically small application that runs on the trusted processor and
> handles a trusted operation.
> 
> > +encrypted memory via TMZ.
> 
> TMZ (Trusted Memory Zone -- encrypted memory for content protection).
> 

I also rewrote this paragraph to address both of your comments:

There is some protection for certain memory elements, and the PSP plays
an essential role in this area. When a specific firmware is loaded into
memory, the PSP takes steps to ensure it has a valid signature. It also
stores firmware images in a protected memory area named Trusted
Memory Area (TMR), so the OS or driver can't corrupt them at runtime. Another
use of PSP is to support the Trusted Application (TA), which is
basically a small application that runs on the trusted processor and
handles a trusted operation (e.g., HDCP). PSP is also used for encrypted
memory for content protection via Trusted Memory Zone (TMZ).

Does it looks good for a v4?

> > +
> > +Another IP that deserves attention is the SMU, as it is connected to all the
> > +other IPs. SMU will help put the GPU in optimal utilization by taking into
> > +account performance and power consumption. SMU helps other blocks to set up a
> > +proper clock configuration. Another feature of SMU is the support for resetting
> > +every component.
> 
> How about something like:
> 
> Another important IP is the SMU.  It handles reset distribution as
> well as clock and power management for all of the IPs on the SoC.

Ok, how about this paragraph for the v4:

Another critical IP is the SMU. It handles reset distribution as well as
clock and power management for all of the IPs on the SoC. SMU also helps
to optimize GPU utilization by balancing performance and power
consumption. Finally, SMU also supports thermal management.

Thanks
Siqueira

> 
> Alex
> 
> > +
> >  .. _pipes-and-queues-description:
> >
> >  GFX, Compute, and SDMA Overall Behavior
> > --
> > 2.51.0
> >

-- 
Rodrigo Siqueira

Re: [PATCH v3 3/5] Documentation/gpu: Expand generic block information

[Alex Deucher]

On Tue, Oct 21, 2025 at 10:55 AM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> Hi Alex/Lijo,
>
> On 10/20, Alex Deucher wrote:
> > On Mon, Oct 20, 2025 at 3:56 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
> > >
> > > This commit expands the overall explanation about AMD GPU IPs by adding
> > > more details about their interconnection. Note that this commit includes
> > > a diagram that provides additional information.
> > >
> > > Cc: Alex Deucher <alexander.deucher@amd.com>
> > > Cc: Christian König <christian.koenig@amd.com>
> > > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > > ---
> > >  .../gpu/amdgpu/amd_overview_block.svg         | 674 ++++++++++++++++++
> > >  Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   3 +
> > >  Documentation/gpu/amdgpu/driver-core.rst      |  25 +
> > >  3 files changed, 702 insertions(+)
> > >  create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
> > >
> > > diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg
> > > new file mode 100644
> > > index 000000000000..8d9ae95bd9a5
> > > --- /dev/null
> > > +++ b/Documentation/gpu/amdgpu/amd_overview_block.svg
> >
> > Got a link to the diagram anywhere?  These looked good at XDC.
>
> After reading your comment in the cover-letter about this diagram, I
> made the following modifications:
>
> 1. Connect PSP to UMC.
> 2. Connect PSP to GC.
> 3. Connect GC to UMC.
> 4. To avoid confusion, I moved the green block outside each specific IP.
> I also changed the explanation about these parts in the text, see it
> below.
>
> Here is the new version:
>
> https://people.igalia.com/siqueira/kernel-doc-imgs/v4/amd_overview_block.svg
>
> What do you think?

Looks good!

>
> >
> > > @@ -0,0 +1,674 @@
> > > +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
> > > +<!-- Created with Inkscape (http://www.inkscape.org/) -->
> > > +
> > > +<svg
>
> <snip>
>
> > > +</svg>
> > > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > index eb72e6f6d4f1..a3f9565d655b 100644
> > > --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > > @@ -227,6 +227,9 @@ we have a dedicated glossary for Display Core at
> > >      TOC
> > >        Table of Contents
> > >
> > > +    UMC
> > > +      Unified Memory Controller
> > > +
> > >      UMSCH
> > >        User Mode Scheduler
> > >
> > > diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
> > > index 3ce276272171..13f13e2e5497 100644
> > > --- a/Documentation/gpu/amdgpu/driver-core.rst
> > > +++ b/Documentation/gpu/amdgpu/driver-core.rst
> > > @@ -77,6 +77,31 @@ VCN (Video Core Next)
> > >      decode.  It's exposed to userspace for user mode drivers (VA-API,
> > >      OpenMAX, etc.)
> > >
> > > +It is important to note that these blocks can interact with each other. The
> > > +picture below illustrates some of the components and their interconnection:
> > > +
> > > +.. kernel-figure:: amd_overview_block.svg
> > > +
> > > +In the diagram, memory-related blocks are represented by a green color. Notice
> > > +that specific IPs have a green block that represents a small hardware block
> > > +named 'hub', which is responsible for interfacing with memory (pre-vega devices
> > > +have a dedicated block for that, named GMC). In the driver code, you can
> > > +identify this component by looking for the suffix hub, for example: gfxhub,
> > > +dchub, mmhub, vmhub, etc. All memory hubs are connected in the UMC, which in
> >
> > All memory hubs are connected to the UMCs, which in
>
> Based on Lijo's comment and Alex's comment in the cover-latter, I
> rewrote this paragraph to:
>
> In the diagram, memory-related blocks are shown in green. Notice that
> specific IPs have a green square that represents a small hardware block
> named 'hub', which is responsible for interfacing with memory. All
> memory hubs are connected in the UMCs, which in turn are connected to
> memory blocks. As a note, pre-vega devices have a dedicated block for
> the Graphic Memory Controller (GMC), which was replaced by UMC in new
> architectures. In the driver code, you can identify this component by

GMC was replaced by UMC + hubs.

> looking for the suffix hub, for example: gfxhub, dchub, mmhub, vmhub,
> etc. Keep in mind that the component's interaction with the memory block
> may vary across architectures. For example, on Navi and newer, GC and
> SDMA are both attached to GCHUB; on pre-Navi, SDMA goes through MMHUB;
> VCN, JPEG, and VPE go through MMHUB; DCN goes through DCHUB.
>
> What do you think?

Looks good to me.

>
> Also, keep in mind that this text is part of the below page that already
> have some comments about GMC.
>
> https://origin.kernel.org/doc/html/latest/gpu/amdgpu/driver-core.html
>
> >
> > > +turn is connected to memory blocks.
> > > +
> > > +There is some level of protection for certain elements in memory, and the PSP
> > > +plays an essential role in this area. For example, when a specific firmware is
> > > +loaded into the memory, PSP takes an action to ensure that the firmware has a
> > > +valid signature.
> >
> > It also stores the firmware images in a protected memory area (TMR =
> > Trusted Memory Area) so the OS or driver can't corrupt it at runtime
> > after it's been validated.
> >
> > > Another use of PSP is to support the TA (e.g., HDCP) and
> >
> > TA = Trusted Application
> > Basically small application that runs on the trusted processor and
> > handles a trusted operation.
> >
> > > +encrypted memory via TMZ.
> >
> > TMZ (Trusted Memory Zone -- encrypted memory for content protection).
> >
>
> I also rewrote this paragraph to address both of your comments:
>
> There is some protection for certain memory elements, and the PSP plays
> an essential role in this area. When a specific firmware is loaded into
> memory, the PSP takes steps to ensure it has a valid signature. It also
> stores firmware images in a protected memory area named Trusted
> Memory Area (TMR), so the OS or driver can't corrupt them at runtime. Another
> use of PSP is to support the Trusted Application (TA), which is
> basically a small application that runs on the trusted processor and

use of PSP is to support Trusted Applications (TA), which are
basically small applications that run on the trusted processor and

> handles a trusted operation (e.g., HDCP). PSP is also used for encrypted
> memory for content protection via Trusted Memory Zone (TMZ).
>
> Does it looks good for a v4?
>
> > > +
> > > +Another IP that deserves attention is the SMU, as it is connected to all the
> > > +other IPs. SMU will help put the GPU in optimal utilization by taking into
> > > +account performance and power consumption. SMU helps other blocks to set up a
> > > +proper clock configuration. Another feature of SMU is the support for resetting
> > > +every component.
> >
> > How about something like:
> >
> > Another important IP is the SMU.  It handles reset distribution as
> > well as clock and power management for all of the IPs on the SoC.
>
> Ok, how about this paragraph for the v4:
>
> Another critical IP is the SMU. It handles reset distribution as well as
> clock and power management for all of the IPs on the SoC. SMU also helps
> to optimize GPU utilization by balancing performance and power
> consumption. Finally, SMU also supports thermal management.

I would include thermal in the first sentence.  E.g., "clock, thermal,
and power management"

Also, the use of "utilization" seems weird.  I think of utilization as
the resources used on the GPU.  Use of the GPU resources is managed by
the scheduler and the driver.  The SMU tries to align performance with
demand.

Thanks,

Alex

>
> Thanks
> Siqueira
>
> >
> > Alex
> >
> > > +
> > >  .. _pipes-and-queues-description:
> > >
> > >  GFX, Compute, and SDMA Overall Behavior
> > > --
> > > 2.51.0
> > >
>
> --
> Rodrigo Siqueira

Re: [PATCH v3 3/5] Documentation/gpu: Expand generic block information

[Lazar, Lijo]

On 10/21/2025 1:08 AM, Rodrigo Siqueira wrote:
> This commit expands the overall explanation about AMD GPU IPs by adding
> more details about their interconnection. Note that this commit includes
> a diagram that provides additional information.
> 
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
>   .../gpu/amdgpu/amd_overview_block.svg         | 674 ++++++++++++++++++
>   Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   3 +
>   Documentation/gpu/amdgpu/driver-core.rst      |  25 +
>   3 files changed, 702 insertions(+)
>   create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
> 
> diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg
> new file mode 100644
> index 000000000000..8d9ae95bd9a5
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/amd_overview_block.svg
> @@ -0,0 +1,674 @@
> +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
> +<!-- Created with Inkscape (http://www.inkscape.org/) -->
> +
> +<svg
> +   width="237.4014mm"
> +   height="160.98259mm"
> +   viewBox="0 0 237.4014 160.98259"
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> +         id="tspan26">PSP Interaction</tspan></text>
> +    <path
> +       style="fill:none;stroke:#ffd42a;stroke-width:1;stroke-dasharray:8, 1;stroke-dashoffset:0"
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> +         id="tspan34">UMC</tspan></text>
> +    <text
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> +         id="tspan35">UMC</tspan></text>
> +    <path
> +       style="fill:none;stroke:#00d455;stroke-width:1;stroke-dasharray:1, 1;stroke-dashoffset:0"
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> +           id="tspan40">Firmware</tspan></text>
> +    </g>
> +    <path
> +       style="fill:none;stroke:#ffd42a;stroke-width:1;stroke-dasharray:8, 1;stroke-dashoffset:0"
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> +    <text
> +       xml:space="preserve"
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> +         id="tspan43">Memory</tspan></text>
> +    <text
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> +         id="tspan45">Memory</tspan></text>
> +    <path
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> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> index eb72e6f6d4f1..a3f9565d655b 100644
> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -227,6 +227,9 @@ we have a dedicated glossary for Display Core at
>       TOC
>         Table of Contents
>   
> +    UMC
> +      Unified Memory Controller
> +
>       UMSCH
>         User Mode Scheduler
>   
> diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
> index 3ce276272171..13f13e2e5497 100644
> --- a/Documentation/gpu/amdgpu/driver-core.rst
> +++ b/Documentation/gpu/amdgpu/driver-core.rst
> @@ -77,6 +77,31 @@ VCN (Video Core Next)
>       decode.  It's exposed to userspace for user mode drivers (VA-API,
>       OpenMAX, etc.)
>   
> +It is important to note that these blocks can interact with each other. The
> +picture below illustrates some of the components and their interconnection:
> +
> +.. kernel-figure:: amd_overview_block.svg
> +
> +In the diagram, memory-related blocks are represented by a green color. Notice
> +that specific IPs have a green block that represents a small hardware block
> +named 'hub', which is responsible for interfacing with memory (pre-vega devices
> +have a dedicated block for that, named GMC). In the driver code, you can

GMC is replaced by UMC and it's not a hub.

> +identify this component by looking for the suffix hub, for example: gfxhub,
> +dchub, mmhub, vmhub, etc. All memory hubs are connected in the UMC, which in
> +turn is connected to memory blocks.
> +
> +There is some level of protection for certain elements in memory, and the PSP
> +plays an essential role in this area. For example, when a specific firmware is
> +loaded into the memory, PSP takes an action to ensure that the firmware has a
> +valid signature. Another use of PSP is to support the TA (e.g., HDCP) and
> +encrypted memory via TMZ.
> +

Overall, you may summarize as PSP takes care of security features - 
authenticating firmware, hardware access protection, content protection etc.

> +Another IP that deserves attention is the SMU, as it is connected to all the
> +other IPs. SMU will help put the GPU in optimal utilization by taking into
> +account performance and power consumption. SMU helps other blocks to set up a
> +proper clock configuration. Another feature of SMU is the support for resetting
> +every component.

SMU has a broader meaning. What is referred to as SMU in driver stands 
for power management controller which is responsible for resets, power 
and thermal management.

Thanks,
Lijo

> +
>   .. _pipes-and-queues-description:
>   
>   GFX, Compute, and SDMA Overall Behavior

[PATCH v3 4/5] Documentation/gpu: Add more information about GC

[Rodrigo Siqueira]

This commit introduces a diagram and a set of information that details
the different sets of schedulers available in the SE.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 Documentation/gpu/amdgpu/gc/index.rst | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/Documentation/gpu/amdgpu/gc/index.rst b/Documentation/gpu/amdgpu/gc/index.rst
index ff6e9ef5cbee..b6b583c9dc6a 100644
--- a/Documentation/gpu/amdgpu/gc/index.rst
+++ b/Documentation/gpu/amdgpu/gc/index.rst
@@ -7,19 +7,21 @@
 The relationship between the CPU and GPU can be described as the
 producer-consumer problem, where the CPU fills out a buffer with operations
 (producer) to be executed by the GPU (consumer). The requested operations in
-the buffer are called Command Packets, which can be summarized as a compressed
-way of transmitting command information to the graphics controller.
+the buffer are called **Command Packets**, which can be summarized as a
+compressed way of transmitting command information to the graphics controller.
 
 The component that acts as the front end between the CPU and the GPU is called
-the Command Processor (CP). This component is responsible for providing greater
-flexibility to the GC since CP makes it possible to program various aspects of
-the GPU pipeline. CP also coordinates the communication between the CPU and GPU
-via a mechanism named **Ring Buffers**, where the CPU appends information to
-the buffer while the GPU removes operations. It is relevant to highlight that a
-CPU can add a pointer to the Ring Buffer that points to another region of
-memory outside the Ring Buffer, and CP can handle it; this mechanism is called
-**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and
-writes the operations to the correct hardware blocks.
+**Command Processor (CP)**. This component is responsible for providing greater
+flexibility to the **Graphics and Compute (GC)** since CP makes it possible to
+program various aspects of the GPU pipeline. CP also coordinates the
+communication between the CPU and GPU via a mechanism named **Ring Buffers**,
+where the CPU appends information to the buffer while the GPU removes
+operations. CP is also responsible for handling **Indirect Buffers (IB)**.
+
+For reference, internally the CP consists of several sub-blocks (CPC - CP
+compute, CPG - CP graphics, and CPF - CP fetcher). Some of these acronyms
+appear in register names, but this is more of an implementation detail and not
+something that directly impacts driver programming or debugging.
 
 Graphics (GFX) and Compute Microcontrollers
 -------------------------------------------
-- 
2.51.0

Re: [PATCH v3 4/5] Documentation/gpu: Add more information about GC

[Alex Deucher]

On Mon, Oct 20, 2025 at 3:47 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> This commit introduces a diagram and a set of information that details
> the different sets of schedulers available in the SE.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  Documentation/gpu/amdgpu/gc/index.rst | 24 +++++++++++++-----------
>  1 file changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/gpu/amdgpu/gc/index.rst b/Documentation/gpu/amdgpu/gc/index.rst
> index ff6e9ef5cbee..b6b583c9dc6a 100644
> --- a/Documentation/gpu/amdgpu/gc/index.rst
> +++ b/Documentation/gpu/amdgpu/gc/index.rst
> @@ -7,19 +7,21 @@
>  The relationship between the CPU and GPU can be described as the
>  producer-consumer problem, where the CPU fills out a buffer with operations
>  (producer) to be executed by the GPU (consumer). The requested operations in
> -the buffer are called Command Packets, which can be summarized as a compressed
> -way of transmitting command information to the graphics controller.
> +the buffer are called **Command Packets**, which can be summarized as a
> +compressed way of transmitting command information to the graphics controller.
>
>  The component that acts as the front end between the CPU and the GPU is called
> -the Command Processor (CP). This component is responsible for providing greater
> -flexibility to the GC since CP makes it possible to program various aspects of
> -the GPU pipeline. CP also coordinates the communication between the CPU and GPU
> -via a mechanism named **Ring Buffers**, where the CPU appends information to
> -the buffer while the GPU removes operations. It is relevant to highlight that a
> -CPU can add a pointer to the Ring Buffer that points to another region of
> -memory outside the Ring Buffer, and CP can handle it; this mechanism is called
> -**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and
> -writes the operations to the correct hardware blocks.
> +**Command Processor (CP)**. This component is responsible for providing greater
> +flexibility to the **Graphics and Compute (GC)** since CP makes it possible to
> +program various aspects of the GPU pipeline. CP also coordinates the
> +communication between the CPU and GPU via a mechanism named **Ring Buffers**,
> +where the CPU appends information to the buffer while the GPU removes
> +operations. CP is also responsible for handling **Indirect Buffers (IB)**.
> +
> +For reference, internally the CP consists of several sub-blocks (CPC - CP
> +compute, CPG - CP graphics, and CPF - CP fetcher). Some of these acronyms
> +appear in register names, but this is more of an implementation detail and not
> +something that directly impacts driver programming or debugging.
>
>  Graphics (GFX) and Compute Microcontrollers
>  -------------------------------------------
> --
> 2.51.0
>

[PATCH v3 5/5] Documentation/gpu: Add documentation about ring buffer

[Rodrigo Siqueira]

AMDGPU heavily relies on ring buffers to manage its components; as a
result, it has an elaborate mechanism of operation with multiple details
around it. This commit introduces new documentation on ring buffers,
detailing their management and expanding the explanation of Enforce
isolation. Finally, this commit also adds the documentation available in
the amdgpu_ring.c file to it.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 .../gpu/amdgpu/enforce_isolation.svg          |  654 +++++++
 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg |  413 +++++
 Documentation/gpu/amdgpu/index.rst            |    1 +
 .../gpu/amdgpu/no_enforce_isolation.svg       |  707 +++++++
 Documentation/gpu/amdgpu/ring-buffer.rst      |   91 +
 Documentation/gpu/amdgpu/ring_buffers.svg     | 1633 +++++++++++++++++
 Documentation/gpu/amdgpu/userq.rst            |    2 +
 7 files changed, 3501 insertions(+)
 create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
 create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
 create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
 create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
 create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg

diff --git a/Documentation/gpu/amdgpu/enforce_isolation.svg b/Documentation/gpu/amdgpu/enforce_isolation.svg
new file mode 100644
index 000000000000..2630681f1cb9
--- /dev/null
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diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
index 45523e9860fc..8732084186a4 100644
--- a/Documentation/gpu/amdgpu/index.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -8,6 +8,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
 .. toctree::
 
    driver-core
+   ring-buffer
    amd-hardware-list-info
    module-parameters
    gc/index
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new file mode 100644
index 000000000000..b224615e1611
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diff --git a/Documentation/gpu/amdgpu/ring-buffer.rst b/Documentation/gpu/amdgpu/ring-buffer.rst
new file mode 100644
index 000000000000..015d803541fe
--- /dev/null
+++ b/Documentation/gpu/amdgpu/ring-buffer.rst
@@ -0,0 +1,91 @@
+=============
+ Ring Buffer
+=============
+
+To handle communication between user space and kernel space, amdgpu adopts a
+strategy based on a ring buffer, which is used by GFX, Compute, SDMA, UVD, VCE,
+VCN, VPE, KIQ, MES, UMSCH, and CPER. See the figure below that illustrates how
+this communication works:
+
+.. kernel-figure:: ring_buffers.svg
+
+Ring buffers in the amdgpu work as a producer-consumer problem, where userspace
+acts as the producer, constantly filling the ring buffer with GPU commands to
+be executed. Meanwhile, the GPU retrieves the information from the ring, parses
+it, and distributes the specific set of instructions between the different
+amdgpu blocks. Notice from the diagram that the ring has a Read Pointer (rptr)
+that indicates where the GPU is currently reading, and there is a Write Pointer
+(wptr) that indicates where the host has written the message. Note that every
+time something is written to the ring, the wptr is incremented. Meanwhile, the
+GPU constantly updates the rptr pointer, chasing the wptr until both pointers
+are equal. The User space or the driver can utilize the rptr pointer to roughly
+estimate how many instructions are still pending completion.
+
+Usually, ring buffers in the driver have a limited size (search for occurrences
+of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is
+that CP (Command Processor) is capable of following addresses inserted into the
+ring; this is illustrated in the image by the reference to the IB (Indirect
+Buffer). The IB gives userspace the possibility to have an area in memory that
+CP can read and feed the hardware with extra instructions.
+
+All ASICs pre-GFX11 use what is called a kernel queue, which means
+the ring is allocated in kernel space and has some restrictions, such as not
+being able to be :ref:`preempted directly by the scheduler<amdgpu-mes>`. GFX11
+and newer support kernel queues, but also provide a new mechanism named
+:ref:`user queues<amdgpu-userq>`, where the queue is moved to the user space
+and can be mapped and unmapped via the scheduler. In practice, both queues
+insert user-space-generated GPU commands from different jobs into the requested
+component ring.
+
+Enforce Isolation
+=================
+
+Before examining the Enforce Isolation mechanism in the ring buffer context, it
+is helpful to briefly discuss how instructions from the ring buffer are
+processed in the graphics pipeline. Let’s expand on this topic by checking the
+diagram below that illustrates the graphics pipeline:
+
+.. kernel-figure:: gfx_pipeline_seq.svg
+
+In terms of executing instructions, the GFX pipeline follows the sequence:
+Shader Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan
+Converter (SC), Primitive Assembler (PA), and cache manipulation (which may
+vary across ASICs). Another common way to describe the pipeline is to use Pixel
+Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader stages.
+Now, with this pipeline in mind, let's assume that Job B causes a hang issue,
+but Job C's instruction might already be executing, leading developers to
+incorrectly identify Job C as the problematic one. This problem can be
+mitigated on multiple levels; the diagram below illustrates how to minimize
+part of this problem:
+
+.. kernel-figure:: no_enforce_isolation.svg
+
+Note from the diagram that there is no guarantee of order or a clear separation
+between instructions, which is not a problem most of the time, and is also good
+for performance. Furthermore, notice some circles between jobs in the diagram
+that represent a **fence wait** used to avoid overlapping work in the ring. At
+the end of the fence, a cache flush occurs, ensuring that when the next job
+starts, it begins in a clean state and, if issues arise, the developer can
+pinpoint the problematic process more precisely.
+
+To increase the level of isolation between jobs, there is the "Enforce
+Isolation" method described in the picture below:
+
+.. kernel-figure:: enforce_isolation.svg
+
+As shown in the diagram, enforcing isolation introduces ordering between
+submissions, since the access to GFX/Compute/Other is serialized.   Notice that
+this approach has a significant performance impact, as it allows only one job
+to submit commands at a time. However, this option can help pinpoint the job
+that caused the problem. Although enforcing isolation improves the situation,
+it does not fully resolve the issue of precisely pinpointing bad jobs, since
+isolation might mask the problem. In summary, identifying which job caused the
+issue may not be precise, but enforcing isolation might help with the
+debugging.
+
+Ring Operations
+===============
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+   :internal:
+
diff --git a/Documentation/gpu/amdgpu/ring_buffers.svg b/Documentation/gpu/amdgpu/ring_buffers.svg
new file mode 100644
index 000000000000..7a6fcb19e151
--- /dev/null
+++ b/Documentation/gpu/amdgpu/ring_buffers.svg
@@ -0,0 +1,1633 @@
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diff --git a/Documentation/gpu/amdgpu/userq.rst b/Documentation/gpu/amdgpu/userq.rst
index ca3ea71f7888..88f54393b220 100644
--- a/Documentation/gpu/amdgpu/userq.rst
+++ b/Documentation/gpu/amdgpu/userq.rst
@@ -1,3 +1,5 @@
+.. _amdgpu-userq:
+
 ==================
  User Mode Queues
 ==================
-- 
2.51.0

Re: [PATCH v3 5/5] Documentation/gpu: Add documentation about ring buffer

[Alex Deucher]

On Mon, Oct 20, 2025 at 3:47 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> AMDGPU heavily relies on ring buffers to manage its components; as a
> result, it has an elaborate mechanism of operation with multiple details
> around it. This commit introduces new documentation on ring buffers,
> detailing their management and expanding the explanation of Enforce
> isolation. Finally, this commit also adds the documentation available in
> the amdgpu_ring.c file to it.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
>  .../gpu/amdgpu/enforce_isolation.svg          |  654 +++++++
>  Documentation/gpu/amdgpu/gfx_pipeline_seq.svg |  413 +++++
>  Documentation/gpu/amdgpu/index.rst            |    1 +
>  .../gpu/amdgpu/no_enforce_isolation.svg       |  707 +++++++
>  Documentation/gpu/amdgpu/ring-buffer.rst      |   91 +
>  Documentation/gpu/amdgpu/ring_buffers.svg     | 1633 +++++++++++++++++
>  Documentation/gpu/amdgpu/userq.rst            |    2 +
>  7 files changed, 3501 insertions(+)
>  create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
>  create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
>  create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
>  create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
>  create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg

Got a link to the images?

<snip>

> diff --git a/Documentation/gpu/amdgpu/ring-buffer.rst b/Documentation/gpu/amdgpu/ring-buffer.rst
> new file mode 100644
> index 000000000000..015d803541fe
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/ring-buffer.rst
> @@ -0,0 +1,91 @@
> +=============
> + Ring Buffer
> +=============
> +
> +To handle communication between user space and kernel space, amdgpu adopts a
> +strategy based on a ring buffer, which is used by GFX, Compute, SDMA, UVD, VCE,
> +VCN, VPE, KIQ, MES, UMSCH, and CPER.

To handle communication between user space and kernel space, AMD GPUs
use a ring buffer design to feed the engines (GFX, Compute, SDMA, UVD,
VCE, VCN, VPE, etc.).

> See the figure below that illustrates how
> +this communication works:
> +
> +.. kernel-figure:: ring_buffers.svg
> +
> +Ring buffers in the amdgpu work as a producer-consumer problem, where userspace

Ring buffers in the amdgpu work as a producer-consumer model, where software

> +acts as the producer, constantly filling the ring buffer with GPU commands to
> +be executed. Meanwhile, the GPU retrieves the information from the ring, parses
> +it, and distributes the specific set of instructions between the different
> +amdgpu blocks.

> Notice from the diagram that the ring has a Read Pointer (rptr)
> +that indicates where the GPU is currently reading, and there is a Write Pointer
> +(wptr) that indicates where the host has written the message. Note that every
> +time something is written to the ring, the wptr is incremented. Meanwhile, the
> +GPU constantly updates the rptr pointer, chasing the wptr until both pointers
> +are equal. The User space or the driver can utilize the rptr pointer to roughly
> +estimate how many instructions are still pending completion.

The ring has a Read Pointer (rptr), which indicates where the engine
is currently reading packets from the ring, and a Write Pointer which
indicates how many packets software has added to the ring.  When the
rptr and wptr are equal, the ring is idle.  When software adds packets
to the ring, it updates the wptr, this causes the engine to start
fetching and processing packets.  As the engine processes packets, the
rptr gets updates until the rptr catches up to the wptr and they are
equal again.

> +
> +Usually, ring buffers in the driver have a limited size (search for occurrences
> +of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is
> +that CP (Command Processor) is capable of following addresses inserted into the
> +ring; this is illustrated in the image by the reference to the IB (Indirect
> +Buffer). The IB gives userspace the possibility to have an area in memory that
> +CP can read and feed the hardware with extra instructions.
> +
> +All ASICs pre-GFX11 use what is called a kernel queue, which means
> +the ring is allocated in kernel space and has some restrictions, such as not
> +being able to be :ref:`preempted directly by the scheduler<amdgpu-mes>`. GFX11
> +and newer support kernel queues, but also provide a new mechanism named
> +:ref:`user queues<amdgpu-userq>`, where the queue is moved to the user space
> +and can be mapped and unmapped via the scheduler. In practice, both queues
> +insert user-space-generated GPU commands from different jobs into the requested
> +component ring.
> +
> +Enforce Isolation
> +=================
> +

Might want to cross link to the other process isolation documentation
at Documentation/gpu/amdgpu/process-isolation.rst

> +Before examining the Enforce Isolation mechanism in the ring buffer context, it
> +is helpful to briefly discuss how instructions from the ring buffer are
> +processed in the graphics pipeline. Let’s expand on this topic by checking the
> +diagram below that illustrates the graphics pipeline:
> +
> +.. kernel-figure:: gfx_pipeline_seq.svg
> +
> +In terms of executing instructions, the GFX pipeline follows the sequence:
> +Shader Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan
> +Converter (SC), Primitive Assembler (PA), and cache manipulation (which may
> +vary across ASICs). Another common way to describe the pipeline is to use Pixel
> +Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader stages.
> +Now, with this pipeline in mind, let's assume that Job B causes a hang issue,
> +but Job C's instruction might already be executing, leading developers to
> +incorrectly identify Job C as the problematic one. This problem can be
> +mitigated on multiple levels; the diagram below illustrates how to minimize
> +part of this problem:
> +
> +.. kernel-figure:: no_enforce_isolation.svg
> +
> +Note from the diagram that there is no guarantee of order or a clear separation
> +between instructions, which is not a problem most of the time, and is also good
> +for performance. Furthermore, notice some circles between jobs in the diagram
> +that represent a **fence wait** used to avoid overlapping work in the ring. At
> +the end of the fence, a cache flush occurs, ensuring that when the next job
> +starts, it begins in a clean state and, if issues arise, the developer can
> +pinpoint the problematic process more precisely.
> +
> +To increase the level of isolation between jobs, there is the "Enforce
> +Isolation" method described in the picture below:
> +
> +.. kernel-figure:: enforce_isolation.svg
> +
> +As shown in the diagram, enforcing isolation introduces ordering between
> +submissions, since the access to GFX/Compute/Other is serialized.   Notice that

enforce isolation only affects GFX and compute.  It's probably easier
to think about it as single process at a time mode for gfx/compute.

Alex

> +this approach has a significant performance impact, as it allows only one job
> +to submit commands at a time. However, this option can help pinpoint the job
> +that caused the problem. Although enforcing isolation improves the situation,
> +it does not fully resolve the issue of precisely pinpointing bad jobs, since
> +isolation might mask the problem. In summary, identifying which job caused the
> +issue may not be precise, but enforcing isolation might help with the
> +debugging.
> +
> +Ring Operations
> +===============
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +   :internal:
> +

Re: [PATCH v3 0/5] Expand kernel-doc with more generic details and info about ring buffers

[Alex Deucher]

On Mon, Oct 20, 2025 at 3:47 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> Lately, I have been part of multiple discussions around GPU recovery and
> other concepts associated with GFX/Compute. Most of the debate is spread
> around GitLab issues, emails, and some meeting conversations. This
> patchset aims to consolidate all that information into a single
> kernel-doc, which can be collaboratively improved and shared with other
> people.
>
> In this series, you will find new amdgpu glossary entries, more details
> about the IPs' interconnections, and a description of the ring buffer.
> This series includes multiple SVG diagrams; for this reason, it might be
> good to apply this series locally. However, if you want to check all the
> images quickly, check the links below:
>
> - https://people.igalia.com/siqueira/kernel-doc-imgs/v3/amd_overview_block.svg

Looks good.  For completeness, maybe add a path from PSP to the UMC on
the right side?
Also, I'm not sure it matters for the sake of the drawing, but the
memory hubs are not really part of the IPs per se.  For example, on
navi and newer, GC and SDMA are both attached to GCHUB.  On pre-Navi,
SDMA goes through MMHUB.  VCN, JPEG, and VPE go through MMHUB.  DCN
goes through DCHUB.

> - https://people.igalia.com/siqueira/kernel-doc-imgs/v3/gfx_pipeline_seq.svg
> - https://people.igalia.com/siqueira/kernel-doc-imgs/v3/no_enforce_isolation.svg
> - https://people.igalia.com/siqueira/kernel-doc-imgs/v3/enforce_isolation.svg
> - https://people.igalia.com/siqueira/kernel-doc-imgs/v3/ring_buffers.svg

These look good.

Thanks!

>
> Finally, keep in mind that I tried to fill in some gaps between
> information, and hopefully, my description matches the reality.
>
> Changes since V2:
>  - Remove the unnecessary diagram.
>  - Remove the excessive details about hardware behavior that are not
>    useful for a driver developer.
>  - Remove some wrong information.
>  - Rewrite many parts of the ring buffer description.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
>
> Thanks
>
> Rodrigo Siqueira (5):
>   drm/amdgpu: Expand kernel-doc in amdgpu_ring
>   Documentation/gpu: Add new glossary entries from UMR
>   Documentation/gpu: Expand generic block information
>   Documentation/gpu: Add more information about GC
>   Documentation/gpu: Add documentation about ring buffer
>
>  .../gpu/amdgpu/amd_overview_block.svg         |  674 +++++++
>  Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   24 +
>  Documentation/gpu/amdgpu/driver-core.rst      |   25 +
>  .../gpu/amdgpu/enforce_isolation.svg          |  654 +++++++
>  Documentation/gpu/amdgpu/gc/index.rst         |   24 +-
>  Documentation/gpu/amdgpu/gfx_pipeline_seq.svg |  413 +++++
>  Documentation/gpu/amdgpu/index.rst            |    1 +
>  .../gpu/amdgpu/no_enforce_isolation.svg       |  707 +++++++
>  Documentation/gpu/amdgpu/ring-buffer.rst      |   91 +
>  Documentation/gpu/amdgpu/ring_buffers.svg     | 1633 +++++++++++++++++
>  Documentation/gpu/amdgpu/userq.rst            |    2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c      |   15 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h      |    2 +
>  13 files changed, 4251 insertions(+), 14 deletions(-)
>  create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
>  create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
>  create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
>  create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
>  create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
>  create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg
>
> --
> 2.51.0
>