[PATCH i-g-t v7 00/14] Intel Xe OA IGT's

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* [PATCH i-g-t v7 00/14] Intel Xe OA IGT's
@ 2024-07-01  2:52 Ashutosh Dixit
  2024-07-01  2:52 ` [PATCH i-g-t 01/14] lib/xe/oa: Add PVC support Ashutosh Dixit
                   ` (17 more replies)
  0 siblings, 18 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:52 UTC (permalink / raw)
  To: igt-dev

The Xe OA lib's and tools have already been merged. This series now
contains the remaining Xe OA IGT's which are yet to be merged.

v7: Add PVC support in IGT lib

Ashutosh Dixit (14):
  lib/xe/oa: Add PVC support
  tests/intel/xe_oa: Add first tests
  tests/intel/xe_oa: Add some negative tests
  tests/intel/xe_oa: Add "oa-formats" subtest
  tests/intel/xe_oa: Add oa exponent tests
  tests/intel/xe_oa: buffer-fill, non-zero-reason, enable-disable
  tests/intel/xe_oa: blocking and polling tests
  tests/intel/xe_oa: OAR/OAC tests
  tests/intel/xe_oa: Exclusive/concurrent access, rc6 and stress open
    close
  tests/intel/xe_oa: add remove OA config tests
  tests/intel/xe_oa: OA buffer mmap tests
  tests/intel/xe_oa: Register whitelisting and MMIO trigger tests
  tests/intel/xe_oa: Drop "xe-ref-count" subtest
  HAX: Add Xe OA tests to xe-fast-feedback.testlist

 lib/meson.build                          |    5 +-
 lib/xe/oa-configs/oa-pvc.xml             | 1018 +++++
 lib/xe/xe_oa.c                           |    4 +
 lib/xe/xe_oa.h                           |    2 +-
 tests/intel-ci/xe-fast-feedback.testlist |   40 +
 tests/intel/xe_oa.c                      | 4707 ++++++++++++++++++++++
 tests/meson.build                        |    2 +
 7 files changed, 5774 insertions(+), 4 deletions(-)
 create mode 100644 lib/xe/oa-configs/oa-pvc.xml
 create mode 100644 tests/intel/xe_oa.c

-- 
2.41.0


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 01/14] lib/xe/oa: Add PVC support
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
@ 2024-07-01  2:52 ` Ashutosh Dixit
  2024-07-01 19:52   ` Umesh Nerlige Ramappa
  2024-07-01  2:52 ` [PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests Ashutosh Dixit
                   ` (16 subsequent siblings)
  17 siblings, 1 reply; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:52 UTC (permalink / raw)
  To: igt-dev

Add oa-pvc.xml and enable support for PVC.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 lib/meson.build              |    5 +-
 lib/xe/oa-configs/oa-pvc.xml | 1018 ++++++++++++++++++++++++++++++++++
 lib/xe/xe_oa.c               |    4 +
 3 files changed, 1024 insertions(+), 3 deletions(-)
 create mode 100644 lib/xe/oa-configs/oa-pvc.xml

diff --git a/lib/meson.build b/lib/meson.build
index 4d51402163..c70ca89602 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -385,10 +385,9 @@ xe_oa_files = [
 
 xe_oa_hardware = [
   'tglgt1', 'tglgt2',
-  'dg1',
-  'rkl',
-  'adl',
+  'dg1', 'rkl', 'adl',
   'acmgt1', 'acmgt2', 'acmgt3',
+  'pvc',
   'mtlgt2', 'mtlgt3',
   'lnl',
 ]
diff --git a/lib/xe/oa-configs/oa-pvc.xml b/lib/xe/oa-configs/oa-pvc.xml
new file mode 100644
index 0000000000..9d212e65ad
--- /dev/null
+++ b/lib/xe/oa-configs/oa-pvc.xml
@@ -0,0 +1,1018 @@
+<?xml version="1.0"?>
+<metrics version="1619079818" merge_md5="">
+  <set name="Compute Metrics Basic"
+       chipset="PVC"
+       symbol_name="ComputeBasic"
+       underscore_name="compute_basic"
+       mdapi_supported_apis="VK OGL OCL IO"
+       hw_config_guid="8d637649-e8f5-4f80-83a4-6575b05d52d8"
+       >
+    <counter name="GPU Time Elapsed"
+             symbol_name="GpuTime"
+             underscore_name="gpu_time"
+             description="Time elapsed on the GPU during the measurement."
+             data_type="uint64"
+             units="ns"
+             semantic_type="duration"
+             equation="GPU_TIME 0 READ 1000000000 UMUL $GpuTimestampFrequency UDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU Core Clocks"
+             symbol_name="GpuCoreClocks"
+             underscore_name="gpu_core_clocks"
+             description="The total number of GPU core clocks elapsed during the measurement."
+             data_type="uint64"
+             units="cycles"
+             semantic_type="event"
+             equation="GPU_CLOCK 0 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Tier1 Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="AVG GPU Core Frequency"
+             symbol_name="AvgGpuCoreFrequency"
+             underscore_name="avg_gpu_core_frequency"
+             description="Average GPU Core Frequency in the measurement."
+             data_type="uint64"
+             max_equation="$GpuMaxFrequency"
+             units="hz"
+             semantic_type="event"
+             equation="$GpuCoreClocks 1000000000 UMUL $GpuTime UDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU Busy"
+             symbol_name="GpuBusy"
+             underscore_name="gpu_busy"
+             description="The percentage of time in which the GPU has been processing GPU commands."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 0 READ 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Tier1 Overview System Frame"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="CS Threads Dispatched"
+             symbol_name="CsThreads"
+             underscore_name="cs_threads"
+             description="The total number of compute shader hardware threads dispatched."
+             data_type="uint64"
+             units="threads"
+             semantic_type="event"
+             equation="A 4 READ"
+             mdapi_group="EU Array/Compute Shader"
+             mdapi_usage_flags="Tier3 Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="Shader Memory Accesses"
+             symbol_name="ShaderMemoryAccesses"
+             underscore_name="shader_memory_accesses"
+             description="The total number of shader memory accesses to L3."
+             data_type="uint64"
+             units="messages"
+             semantic_type="event"
+             equation="A 32 READ"
+             mdapi_group="L3/Data Port"
+             mdapi_usage_flags="Tier3 Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="Shader Atomic Memory Accesses"
+             symbol_name="ShaderAtomics"
+             underscore_name="shader_atomics"
+             description="The total number of shader atomic memory accesses."
+             data_type="uint64"
+             units="messages"
+             semantic_type="event"
+             equation="A 34 READ"
+             mdapi_group="L3/Data Port/Atomics"
+             mdapi_usage_flags="Tier3 Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="Shader Barrier Messages"
+             symbol_name="ShaderBarriers"
+             underscore_name="shader_barriers"
+             description="The total number of shader barrier messages."
+             data_type="uint64"
+             units="messages"
+             semantic_type="event"
+             equation="A 35 READ"
+             mdapi_group="EU Array/Barrier"
+             mdapi_usage_flags="Tier3 Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="SLM Reads"
+             symbol_name="SlmReads"
+             underscore_name="slm_reads"
+             description="The total number of reads from shared local memory."
+             data_type="uint64"
+             max_equation="$GpuCoreClocks $EuSubslicesTotalCount UMUL"
+             units="events"
+             semantic_type="event"
+             equation="A 30 READ"
+             mdapi_group="L3/Data Port/SLM"
+             mdapi_usage_flags="Tier3 Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="SLM Writes"
+             symbol_name="SlmWrites"
+             underscore_name="slm_writes"
+             description="The total number of writes to shared local memory."
+             data_type="uint64"
+             max_equation="$GpuCoreClocks $EuSubslicesTotalCount UMUL"
+             units="events"
+             semantic_type="event"
+             equation="A 31 READ"
+             mdapi_group="L3/Data Port/SLM"
+             mdapi_usage_flags="Tier3 Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GTI Read Throughput"
+             symbol_name="GtiReadThroughput"
+             underscore_name="gti_read_throughput"
+             description="The total number of GPU memory bytes read from GTI."
+             data_type="uint64"
+             max_equation="$GpuCoreClocks 64 UMUL"
+             units="bytes"
+             semantic_type="throughput"
+             equation="128  A 36 READ UMUL"
+             mdapi_group="GTI"
+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GTI Write Throughput"
+             symbol_name="GtiWriteThroughput"
+             underscore_name="gti_write_throughput"
+             description="The total number of GPU memory bytes written to GTI."
+             data_type="uint64"
+             max_equation="$GpuCoreClocks 64 UMUL"
+             units="bytes"
+             semantic_type="throughput"
+             equation="128  A 37 READ UMUL"
+             mdapi_group="GTI"
+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EU Active"
+             symbol_name="EU_ACTIVE_CYCLES"
+             underscore_name="eu_active_cycles"
+             description="The percentage of time in which the Execution Units were actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array"
+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EU Stall"
+             symbol_name="EU_STALL_CYCLES"
+             underscore_name="eu_stall_cycles"
+             description="The percentage of time in which the Execution Units were stalled."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array"
+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EU FPU Pipe Active"
+             symbol_name="EU_INST_EXECUTED_ALU0_ALL"
+             underscore_name="eu_inst_executed_alu0_all"
+             description="The percentage of time in which EU FPU INT64 pipeline was actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 9 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EM Pipe Active"
+             symbol_name="EU_INST_EXECUTED_ALU1_ALL"
+             underscore_name="eu_inst_executed_alu1_all"
+             description="The percentage of time in which EU EM INT pipeline was actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 10 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="SYS Pipe Active"
+             symbol_name="EU_INST_EXECUTED_SYSTOLIC_ALL"
+             underscore_name="eu_inst_executed_systolic_all"
+             description="The percentage of time in which EU SYS pipeline was actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="Send Pipe Active"
+             symbol_name="EU_INST_EXECUTED_SEND_ALL"
+             underscore_name="eu_inst_executed_send_all"
+             description="The percentage of time in which EU send pipeline was actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 11 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EM JEU Instruction"
+             symbol_name="EU_INST_EXECUTED_CONTROL_ALL"
+             underscore_name="eu_inst_executed_control_all"
+             description="The percentage of time in which JEU instruction were processed actively on EM INT pipeline."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EM And FPU Pipes Active"
+             symbol_name="EU_PIPE_ALU0_AND_ALU1_ACTIVE_CYCLES"
+             underscore_name="eu_pipe_alu0_and_alu1_active_cycles"
+             description="The percentage of time in which EU EM INT and FPU INT64 pipelines were actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 15 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="SYS And FPU Pipes Active"
+             symbol_name="EU_PIPE_ALU0_AND_SYSTOLIC_ACTIVE_CYCLES"
+             underscore_name="eu_pipe_alu0_and_systolic_active_cycles"
+             description="The percentage of time in which EU Systolic and FPU INT64 pipelines were actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 14 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EU Thread Occupancy"
+             symbol_name="EU_THREADS_OCCUPANCY_ALL"
+             underscore_name="eu_threads_occupancy_all"
+             description="The percentage of time in which hardware threads occupied EUs."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="8 A 16 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array"
+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="SYSMEM_TRANSACTION_READ"
+             symbol_name="SYSMEM_TRANSACTION_READ"
+             underscore_name="sysmem_transaction_read"
+             description="The number of system memory reads (upstream)"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="C 7 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="SYSMEM_TRANSACTION_WRITE"
+             symbol_name="SYSMEM_TRANSACTION_WRITE"
+             underscore_name="sysmem_transaction_write"
+             description="The number of system memory writes  (upstream)"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="C 6 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="HOST_TO_GPUMEM_TRANSACTION_READ"
+             symbol_name="HOST_TO_GPUMEM_TRANSACTION_READ"
+             underscore_name="host_to_gpumem_transaction_read"
+             description="Host reads to GPU local (HBM) memory (downstream)"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="C 5 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="HOST_TO_GPUMEM_TRANSACTION_WRITE"
+             symbol_name="HOST_TO_GPUMEM_TRANSACTION_WRITE"
+             underscore_name="host_to_gpumem_transaction_write"
+             description="Host writes to GPU local (HBM) memory (downstream)"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="C 4 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI0"
+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI0"
+             underscore_name="gpu_memory_request_queue_full_sqidi0"
+             description="The The percentage of time in which SQ 0 is filled above a threshold (usually 48 entries)"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="C 3 READ 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI1"
+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI1"
+             underscore_name="gpu_memory_request_queue_full_sqidi1"
+             description="The The percentage of time in which SQ 1 is filled above a threshold (usually 48 entries)"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="C 2 READ 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI2"
+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI2"
+             underscore_name="gpu_memory_request_queue_full_sqidi2"
+             description="The The percentage of time in which SQ 2 is filled above a threshold (usually 48 entries)"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="C 1 READ 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI3"
+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI3"
+             underscore_name="gpu_memory_request_queue_full_sqidi3"
+             description="The The percentage of time in which SQ 3 is filled above a threshold (usually 48 entries)"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="C 0 READ 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI4"
+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI4"
+             underscore_name="gpu_memory_request_queue_full_sqidi4"
+             description="The The percentage of time in which SQ 4 is filled above a threshold (usually 48 entries)"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="B 7 READ 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI8"
+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI8"
+             underscore_name="gpu_memory_request_queue_full_sqidi8"
+             description="The The percentage of time in which SQ 8 is filled above a threshold (usually 48 entries)"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="B 6 READ 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI12"
+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI12"
+             underscore_name="gpu_memory_request_queue_full_sqidi12"
+             description="The The percentage of time in which SQ 12 is filled above a threshold (usually 48 entries)"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="B 5 READ 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <register_config type="NOA">
+        <register type="NOA" address="0x00000D04" value="0x00000200" />
+        <register type="NOA" address="0x00009884" value="0x0000000C" />
+        <register type="NOA" address="0x00009888" value="0x14307FC0" />
+        <register type="NOA" address="0x00009888" value="0x04306000" />
+        <register type="NOA" address="0x00009888" value="0x14003400" />
+        <register type="NOA" address="0x00009888" value="0x14013400" />
+        <register type="NOA" address="0x00009888" value="0x14023400" />
+        <register type="NOA" address="0x00009888" value="0x14033400" />
+        <register type="NOA" address="0x00009888" value="0x14083400" />
+        <register type="NOA" address="0x00009888" value="0x140C3400" />
+        <register type="NOA" address="0x00009888" value="0x14043400" />
+        <register type="NOA" address="0x00009888" value="0x1A100090" />
+        <register type="NOA" address="0x00009888" value="0x1A110009" />
+        <register type="NOA" address="0x00009888" value="0x00142000" />
+        <register type="NOA" address="0x00009888" value="0x0050FFE0" />
+        <register type="NOA" address="0x00009888" value="0x00300240" />
+        <register type="NOA" address="0x00009888" value="0x0E300695" />
+        <register type="NOA" address="0x00009888" value="0x10300824" />
+        <register type="NOA" address="0x00009888" value="0x02300000" />
+        <register type="NOA" address="0x00009888" value="0x00000002" />
+        <register type="NOA" address="0x00009888" value="0x0E000080" />
+        <register type="NOA" address="0x00009888" value="0x04000000" />
+        <register type="NOA" address="0x00009888" value="0x00010002" />
+        <register type="NOA" address="0x00009888" value="0x0E010002" />
+        <register type="NOA" address="0x00009888" value="0x04010000" />
+        <register type="NOA" address="0x00009888" value="0x00020002" />
+        <register type="NOA" address="0x00009888" value="0x0C020080" />
+        <register type="NOA" address="0x00009888" value="0x04020000" />
+        <register type="NOA" address="0x00009888" value="0x00030002" />
+        <register type="NOA" address="0x00009888" value="0x0C030002" />
+        <register type="NOA" address="0x00009888" value="0x04030000" />
+        <register type="NOA" address="0x00009888" value="0x00080002" />
+        <register type="NOA" address="0x00009888" value="0x0A080002" />
+        <register type="NOA" address="0x00009888" value="0x04080000" />
+        <register type="NOA" address="0x00009888" value="0x00128000" />
+        <register type="NOA" address="0x00009888" value="0x00160800" />
+        <register type="NOA" address="0x00009888" value="0x000C0002" />
+        <register type="NOA" address="0x00009888" value="0x080C0080" />
+        <register type="NOA" address="0x00009888" value="0x040C0000" />
+        <register type="NOA" address="0x00009888" value="0x00040002" />
+        <register type="NOA" address="0x00009888" value="0x0A040080" />
+        <register type="NOA" address="0x00009888" value="0x04040000" />
+        <register type="NOA" address="0x00009888" value="0x2C500000" />
+        <register type="NOA" address="0x00009888" value="0x2E500400" />
+        <register type="NOA" address="0x00009888" value="0x30500000" />
+        <register type="NOA" address="0x00009888" value="0x18500000" />
+        <register type="NOA" address="0x00009888" value="0x32500A05" />
+        <register type="NOA" address="0x00009888" value="0x20500030" />
+        <register type="NOA" address="0x00009888" value="0x22500603" />
+        <register type="NOA" address="0x00009888" value="0x24500030" />
+        <register type="NOA" address="0x00009888" value="0x26500603" />
+        <register type="NOA" address="0x00009884" value="0x00000008" />
+        <register type="NOA" address="0x00009888" value="0x01404400" />
+        <register type="NOA" address="0x00009888" value="0x01414400" />
+        <register type="NOA" address="0x00009888" value="0x030755A0" />
+        <register type="NOA" address="0x00009888" value="0x0308AA00" />
+        <register type="NOA" address="0x00009888" value="0x01000040" />
+        <register type="NOA" address="0x00009888" value="0x01010040" />
+        <register type="NOA" address="0x00009888" value="0x01021000" />
+        <register type="NOA" address="0x00009888" value="0x01036400" />
+        <register type="NOA" address="0x00009888" value="0x0104A800" />
+        <register type="NOA" address="0x00009888" value="0x03045555" />
+        <register type="NOA" address="0x00009888" value="0x0305555A" />
+        <register type="NOA" address="0x00009888" value="0x0106FC00" />
+        <register type="NOA" address="0x00009888" value="0x01190400" />
+        <register type="NOA" address="0x00009888" value="0x011B0400" />
+        <register type="NOA" address="0x00009888" value="0x011C4800" />
+        <register type="NOA" address="0x00009888" value="0x011E4000" />
+        <register type="NOA" address="0x00009888" value="0x01108000" />
+    </register_config>
+    <register_config type="OA">
+        <register type="OA" address="0x0000D920" value="0x00000000" />
+        <register type="OA" address="0x0000D900" value="0x00000000" />
+        <register type="OA" address="0x0000D904" value="0x00800000" />
+        <register type="OA" address="0x0000D910" value="0x00000000" />
+        <register type="OA" address="0x0000D914" value="0x00800000" />
+        <register type="OA" address="0x0000DC40" value="0x00000000" />
+        <register type="OA" address="0x00002B2C" value="0x00000000" />
+    </register_config>
+    <register_config type="FLEX">
+        <register type="FLEX" address="0x0000E458" value="0x00005004" />
+        <register type="FLEX" address="0x0000E558" value="0x00001000" />
+        <register type="FLEX" address="0x0000E658" value="0x00001002" />
+        <register type="FLEX" address="0x0000E758" value="0x0000A009" />
+        <register type="FLEX" address="0x0000E45C" value="0x00008003" />
+    </register_config>
+  </set>
+
+  <set name="TestOa"
+       chipset="PVC"
+       symbol_name="TestOa"
+       underscore_name="test_oa"
+       mdapi_supported_apis="VK OGL OCL IO"
+       hw_config_guid="339a376a-4696-4e0d-812a-5fd13b0e1aa8"
+       >
+    <counter name="GPU Time Elapsed"
+             symbol_name="GpuTime"
+             underscore_name="gpu_time"
+             description="Time elapsed on the GPU during the measurement."
+             data_type="uint64"
+             units="ns"
+             semantic_type="duration"
+             equation="GPU_TIME 0 READ 1000000000 UMUL $GpuTimestampFrequency UDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU Core Clocks"
+             symbol_name="GpuCoreClocks"
+             underscore_name="gpu_core_clocks"
+             description="The total number of GPU core clocks elapsed during the measurement."
+             data_type="uint64"
+             units="cycles"
+             semantic_type="event"
+             equation="GPU_CLOCK 0 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Tier1 Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="TestCounter0"
+             symbol_name="Counter0"
+             underscore_name="counter0"
+             description="HW test counter 0. Factor: 0.0"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="B 0 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="TestCounter1"
+             symbol_name="Counter1"
+             underscore_name="counter1"
+             description="HW test counter 1. Factor: 1.0"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="B 1 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="TestCounter3"
+             symbol_name="Counter3"
+             underscore_name="counter3"
+             description="HW test counter 3. Factor: 0.5"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="B 2 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="TestCounter4"
+             symbol_name="Counter4"
+             underscore_name="counter4"
+             description="HW test counter 4. Factor: 0.3333"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="B 3 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="TestCounter5"
+             symbol_name="Counter5"
+             underscore_name="counter5"
+             description="HW test counter 5. Factor: 0.3333"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="B 4 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="TestCounter8"
+             symbol_name="Counter8"
+             underscore_name="counter8"
+             description="HW test counter 8. Should be equal to 1 in IOStream or in OAG query mode"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="C 7 READ"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="L3_BANK_INPUT_AVAILABLE _L3BANK0"
+             symbol_name="L3_BANK_INPUT_AVAILABLE_L3BANK0"
+             underscore_name="l3_bank_input_available_l3_bank0"
+             description="The percentage of time in which l3 bank 0 input is available"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="C 6 READ 100 UMUL $GpuCoreClocks FDIV"
+             availability="1"
+             mdapi_group="GTI/L3"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="subslice_bank"
+             />
+    <counter name="L3_OUTPUT_READY _L3BANK0"
+             symbol_name="L3_OUTPUT_READY_L3BANK0"
+             underscore_name="l3_output_ready_l3_bank0"
+             description="The percentage of time in which l3 bank 0 output is ready"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="C 3 READ 100 UMUL $GpuCoreClocks FDIV"
+             availability="1"
+             mdapi_group="GTI/L3"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="subslice_bank"
+             />
+    <counter name="L3_READ _L3BANK0"
+             symbol_name="L3_READ_L3BANK0"
+             underscore_name="l3_read_l3_bank0"
+             description="The number of L3 bank 0 read requests"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="C 5 READ"
+             availability="1"
+             mdapi_group="GTI/L3"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="subslice_bank"
+             />
+    <counter name="L3_WRITE _L3BANK0"
+             symbol_name="L3_WRITE_L3BANK0"
+             underscore_name="l3_write_l3_bank0"
+             description="The number of L3 Bank 0 write requests"
+             data_type="uint64"
+             units="events"
+             semantic_type="event"
+             equation="C 4 READ"
+             availability="1"
+             mdapi_group="GTI/L3"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="subslice_bank"
+             />
+    <counter name="THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES _DUALSUBSLICE0"
+             symbol_name="THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_DUALSUBSLICE0"
+             underscore_name="threadgroup_dispatch_queue0_active_cycles_dualsubslice0"
+             description="The percentage of time in which non-PS thread is ready for dispatch in thread dispatcher 0 queue 0"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="B 5 READ 100 UMUL $GpuCoreClocks FDIV"
+             availability="$DualSubsliceMask 1 AND"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="dualsubslice"
+             />
+    <counter name="THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES _DUALSUBSLICE0"
+             symbol_name="THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_DUALSUBSLICE0"
+             underscore_name="threadgroup_dispatch_queue1_active_cycles_dualsubslice0"
+             description="The percentage of time in which non-PS thread is ready for dispatch in thread dispatcher 0 queue 1"
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="B 6 READ 100 UMUL $GpuCoreClocks FDIV"
+             availability="$DualSubsliceMask 1 AND"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="dualsubslice"
+             />
+    <counter name="EU Active"
+             symbol_name="EuActive"
+             underscore_name="eu_active"
+             description="The percentage of time in which the Execution Units were actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array"
+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EU Stall"
+             symbol_name="EuStall"
+             underscore_name="eu_stall"
+             description="The percentage of time in which the Execution Units were stalled."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array"
+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EU Thread Occupancy"
+             symbol_name="EuThreadOccupancy"
+             underscore_name="eu_thread_occupancy"
+             description="The percentage of time in which hardware threads occupied EUs."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="8 A 10 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array"
+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EU FPU Pipe Active"
+             symbol_name="FpuActive"
+             underscore_name="fpu_active"
+             description="The percentage of time in which EU FPU INT64 pipeline was actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 11 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EM Pipe Active"
+             symbol_name="EmActive"
+             underscore_name="em_active"
+             description="The percentage of time in which EU EM INT pipeline was actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="SYS Pipe Active"
+             symbol_name="SysActive"
+             underscore_name="sys_active"
+             description="The percentage of time in which EU SYS pipeline was actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="EM And FPU Pipes Active"
+             symbol_name="EmFpuActive"
+             underscore_name="em_fpu_active"
+             description="The percentage of time in which EU EM INT and FPU INT64 pipelines were actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 9 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="SYS And FPU Pipes Active"
+             symbol_name="SysFpuActive"
+             underscore_name="sys_fpu_active"
+             description="The percentage of time in which EU Systolic and FPU INT64 pipelines were actively processing."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 14 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="EU Array/Pipes"
+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="CS Threads Dispatched"
+             symbol_name="CsThreads"
+             underscore_name="cs_threads"
+             description="The total number of compute shader hardware threads dispatched."
+             data_type="uint64"
+             units="threads"
+             semantic_type="event"
+             equation="A 4 READ"
+             mdapi_group="EU Array/Compute Shader"
+             mdapi_usage_flags="Tier3 Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GPU Busy"
+             symbol_name="GpuBusy"
+             underscore_name="gpu_busy"
+             description="The percentage of time in which the GPU has been processing GPU commands."
+             data_type="float"
+             max_equation="100"
+             units="percent"
+             semantic_type="duration"
+             equation="A 0 READ 100 UMUL $GpuCoreClocks FDIV"
+             mdapi_group="GPU"
+             mdapi_usage_flags="Tier1 Overview System Frame"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="Gti Read Transactions"
+             symbol_name="GtiReadTransactions"
+             underscore_name="gti_read_transactions"
+             description="The total number of read transactions sent to GTI interfaces"
+             data_type="uint64"
+             max_equation="$GpuCoreClocks $EuSlicesTotalCount 4 UGT 8 UMUL $EuSlicesTotalCount 4 ULTE $EuSlicesTotalCount 1 UADD 0x6 AND UMUL UADD UMUL"
+             units="messages"
+             semantic_type="event"
+             equation="A 36 READ"
+             mdapi_group="GTI"
+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <counter name="GTI Write Transactions"
+             symbol_name="GtiWriteTransactions"
+             underscore_name="gti_write_transactions"
+             description="The total number of write transactions sent to GTI interfaces"
+             data_type="uint64"
+             max_equation="$GpuCoreClocks $EuSlicesTotalCount 4 UGT 8 UMUL $EuSlicesTotalCount 4 ULTE $EuSlicesTotalCount 1 UADD 0x6 AND UMUL UADD UMUL"
+             units="messages"
+             semantic_type="event"
+             equation="A 37 READ"
+             mdapi_group="GTI"
+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
+             mdapi_supported_apis=""
+             mdapi_hw_unit_type="gpu"
+             />
+    <register_config type="NOA">
+        <register type="NOA" address="0x00000D04" value="0x00000200" />
+        <register type="NOA" address="0x00009884" value="0x00000008" />
+        <register type="NOA" address="0x00009888" value="0x3B410000" />
+        <register type="NOA" address="0x00009888" value="0x0140000A" />
+        <register type="NOA" address="0x00009888" value="0x33406A80" />
+        <register type="NOA" address="0x00009888" value="0x07410006" />
+        <register type="NOA" address="0x00009888" value="0x17410033" />
+        <register type="NOA" address="0x00009888" value="0x03410000" />
+        <register type="NOA" address="0x00009888" value="0x4F410000" />
+        <register type="NOA" address="0x00009888" value="0x01030005" />
+        <register type="NOA" address="0x00009888" value="0x03035540" />
+        <register type="NOA" address="0x00009888" value="0x0104000A" />
+        <register type="NOA" address="0x00009888" value="0x0304AA80" />
+        <register type="NOA" address="0x00009888" value="0x1D500003" />
+        <register type="NOA" address="0x00009888" value="0x02E71540" />
+        <register type="NOA" address="0x00009888" value="0x02EA2A80" />
+        <register type="NOA" address="0x00009888" value="0x02E82A80" />
+        <register type="NOA" address="0x00009888" value="0x00F07803" />
+        <register type="NOA" address="0x00009888" value="0x00F10005" />
+        <register type="NOA" address="0x00009888" value="0x02F12A80" />
+        <register type="NOA" address="0x00009888" value="0x00F20003" />
+        <register type="NOA" address="0x00009888" value="0x22F30012" />
+        <register type="NOA" address="0x00009888" value="0x26F32490" />
+        <register type="NOA" address="0x00009888" value="0x00F4000A" />
+        <register type="NOA" address="0x00009888" value="0x22D3003F" />
+        <register type="NOA" address="0x00009884" value="0x00000004" />
+        <register type="NOA" address="0x00009888" value="0x044C2000" />
+        <register type="NOA" address="0x00009888" value="0x064C6000" />
+        <register type="NOA" address="0x00009888" value="0x004C0010" />
+        <register type="NOA" address="0x00009888" value="0x0E4C0180" />
+        <register type="NOA" address="0x00009888" value="0x104C0305" />
+        <register type="NOA" address="0x00009888" value="0x124C0007" />
+        <register type="NOA" address="0x00009884" value="0x0000000C" />
+        <register type="NOA" address="0x00009888" value="0x0050F803" />
+        <register type="NOA" address="0x00009888" value="0x1C500000" />
+        <register type="NOA" address="0x00009888" value="0x1E500000" />
+        <register type="NOA" address="0x00009888" value="0x28500000" />
+        <register type="NOA" address="0x00009888" value="0x18500000" />
+        <register type="NOA" address="0x00009888" value="0x20500000" />
+        <register type="NOA" address="0x00009888" value="0x22500C06" />
+        <register type="NOA" address="0x00009888" value="0x24500060" />
+        <register type="NOA" address="0x00009888" value="0x26501606" />
+        <register type="NOA" address="0x00009884" value="0x00000000" />
+        <register type="NOA" address="0x00009888" value="0x28036400" />
+        <register type="NOA" address="0x00009888" value="0x2A030080" />
+        <register type="NOA" address="0x00009888" value="0x06031300" />
+        <register type="NOA" address="0x00009888" value="0x08030FB0" />
+        <register type="NOA" address="0x00009888" value="0x00030000" />
+        <register type="NOA" address="0x00009888" value="0x00C00005" />
+        <register type="NOA" address="0x00009888" value="0x00C1000F" />
+        <register type="NOA" address="0x00009888" value="0x00C2000F" />
+        <register type="NOA" address="0x00009888" value="0x00C3001B" />
+        <register type="NOA" address="0x00009884" value="0x00000000" />
+        <register type="NOA" address="0x00009888" value="0x5C030002" />
+    </register_config>
+    <register_config type="OA">
+        <register type="OA" address="0x0000D920" value="0x00000000" />
+        <register type="OA" address="0x0000D900" value="0x00000000" />
+        <register type="OA" address="0x0000D904" value="0xF0800000" />
+        <register type="OA" address="0x0000D910" value="0x00000000" />
+        <register type="OA" address="0x0000D914" value="0x70800000" />
+        <register type="OA" address="0x0000DC40" value="0x007F0000" />
+        <register type="OA" address="0x0000D940" value="0x00000004" />
+        <register type="OA" address="0x0000D944" value="0x0000FFFF" />
+        <register type="OA" address="0x0000DC00" value="0x00000004" />
+        <register type="OA" address="0x0000DC04" value="0x0000FFFF" />
+        <register type="OA" address="0x0000D948" value="0x00000003" />
+        <register type="OA" address="0x0000D94C" value="0x0000FFFF" />
+        <register type="OA" address="0x0000DC08" value="0x00000003" />
+        <register type="OA" address="0x0000DC0C" value="0x0000FFFF" />
+        <register type="OA" address="0x0000D950" value="0x00100002" />
+        <register type="OA" address="0x0000D954" value="0x0000FFFB" />
+        <register type="OA" address="0x0000DC10" value="0x00100002" />
+        <register type="OA" address="0x0000DC14" value="0x0000FFFB" />
+        <register type="OA" address="0x0000D958" value="0x00100002" />
+        <register type="OA" address="0x0000D95C" value="0x0000FFE7" />
+        <register type="OA" address="0x0000DC18" value="0x00100002" />
+        <register type="OA" address="0x0000DC1C" value="0x0000FFE7" />
+        <register type="OA" address="0x0000D960" value="0x00100042" />
+        <register type="OA" address="0x0000D964" value="0x0000FFF7" />
+        <register type="OA" address="0x0000DC20" value="0x00100042" />
+        <register type="OA" address="0x0000DC24" value="0x0000FFF7" />
+        <register type="OA" address="0x0000D968" value="0x00000002" />
+        <register type="OA" address="0x0000D96C" value="0x0000FFFE" />
+        <register type="OA" address="0x0000DC28" value="0x00000002" />
+        <register type="OA" address="0x0000DC2C" value="0x0000FFFE" />
+        <register type="OA" address="0x0000D970" value="0x00000002" />
+        <register type="OA" address="0x0000D974" value="0x0000FFFD" />
+        <register type="OA" address="0x0000DC30" value="0x00000002" />
+        <register type="OA" address="0x0000DC34" value="0x0000FFFD" />
+        <register type="OA" address="0x00002B2C" value="0x00000000" />
+    </register_config>
+    <register_config type="FLEX">
+        <register type="FLEX" address="0x0000E458" value="0x00005004" />
+        <register type="FLEX" address="0x0000E558" value="0x00008003" />
+        <register type="FLEX" address="0x0000E658" value="0x00001000" />
+        <register type="FLEX" address="0x0000E758" value="0x0000A009" />
+    </register_config>
+  </set>
+
+</metrics>
diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c
index 576358fe22..d2d0687d9a 100644
--- a/lib/xe/xe_oa.c
+++ b/lib/xe/xe_oa.c
@@ -36,6 +36,7 @@
 #include "xe_oa_metrics_acmgt3.h"
 #include "xe_oa_metrics_mtlgt2.h"
 #include "xe_oa_metrics_mtlgt3.h"
+#include "xe_oa_metrics_pvc.h"
 #include "xe_oa_metrics_lnl.h"
 
 static struct intel_xe_perf_logical_counter_group *
@@ -296,6 +297,9 @@ intel_xe_perf_for_devinfo(uint32_t device_id,
 			intel_xe_perf_load_metrics_acmgt3(perf);
 		else
 			return unsupported_xe_oa_platform(perf);
+	} else if (devinfo->is_pontevecchio) {
+		perf->devinfo.eu_threads_count = 8;
+		intel_xe_perf_load_metrics_pvc(perf);
 	} else if (intel_graphics_ver(device_id) >= IP_VER(20, 0)) {
 		intel_xe_perf_load_metrics_lnl(perf);
 	} else {
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* Re: [PATCH i-g-t 01/14] lib/xe/oa: Add PVC support
  2024-07-01  2:52 ` [PATCH i-g-t 01/14] lib/xe/oa: Add PVC support Ashutosh Dixit
@ 2024-07-01 19:52   ` Umesh Nerlige Ramappa
  0 siblings, 0 replies; 26+ messages in thread
From: Umesh Nerlige Ramappa @ 2024-07-01 19:52 UTC (permalink / raw)
  To: Ashutosh Dixit; +Cc: igt-dev

On Sun, Jun 30, 2024 at 07:52:56PM -0700, Ashutosh Dixit wrote:
>Add oa-pvc.xml and enable support for PVC.
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

>---
> lib/meson.build              |    5 +-
> lib/xe/oa-configs/oa-pvc.xml | 1018 ++++++++++++++++++++++++++++++++++
> lib/xe/xe_oa.c               |    4 +
> 3 files changed, 1024 insertions(+), 3 deletions(-)
> create mode 100644 lib/xe/oa-configs/oa-pvc.xml
>
>diff --git a/lib/meson.build b/lib/meson.build
>index 4d51402163..c70ca89602 100644
>--- a/lib/meson.build
>+++ b/lib/meson.build
>@@ -385,10 +385,9 @@ xe_oa_files = [
>
> xe_oa_hardware = [
>   'tglgt1', 'tglgt2',
>-  'dg1',
>-  'rkl',
>-  'adl',
>+  'dg1', 'rkl', 'adl',
>   'acmgt1', 'acmgt2', 'acmgt3',
>+  'pvc',
>   'mtlgt2', 'mtlgt3',
>   'lnl',
> ]
>diff --git a/lib/xe/oa-configs/oa-pvc.xml b/lib/xe/oa-configs/oa-pvc.xml
>new file mode 100644
>index 0000000000..9d212e65ad
>--- /dev/null
>+++ b/lib/xe/oa-configs/oa-pvc.xml
>@@ -0,0 +1,1018 @@
>+<?xml version="1.0"?>
>+<metrics version="1619079818" merge_md5="">
>+  <set name="Compute Metrics Basic"
>+       chipset="PVC"
>+       symbol_name="ComputeBasic"
>+       underscore_name="compute_basic"
>+       mdapi_supported_apis="VK OGL OCL IO"
>+       hw_config_guid="8d637649-e8f5-4f80-83a4-6575b05d52d8"
>+       >
>+    <counter name="GPU Time Elapsed"
>+             symbol_name="GpuTime"
>+             underscore_name="gpu_time"
>+             description="Time elapsed on the GPU during the measurement."
>+             data_type="uint64"
>+             units="ns"
>+             semantic_type="duration"
>+             equation="GPU_TIME 0 READ 1000000000 UMUL $GpuTimestampFrequency UDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU Core Clocks"
>+             symbol_name="GpuCoreClocks"
>+             underscore_name="gpu_core_clocks"
>+             description="The total number of GPU core clocks elapsed during the measurement."
>+             data_type="uint64"
>+             units="cycles"
>+             semantic_type="event"
>+             equation="GPU_CLOCK 0 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Tier1 Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="AVG GPU Core Frequency"
>+             symbol_name="AvgGpuCoreFrequency"
>+             underscore_name="avg_gpu_core_frequency"
>+             description="Average GPU Core Frequency in the measurement."
>+             data_type="uint64"
>+             max_equation="$GpuMaxFrequency"
>+             units="hz"
>+             semantic_type="event"
>+             equation="$GpuCoreClocks 1000000000 UMUL $GpuTime UDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU Busy"
>+             symbol_name="GpuBusy"
>+             underscore_name="gpu_busy"
>+             description="The percentage of time in which the GPU has been processing GPU commands."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 0 READ 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Tier1 Overview System Frame"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="CS Threads Dispatched"
>+             symbol_name="CsThreads"
>+             underscore_name="cs_threads"
>+             description="The total number of compute shader hardware threads dispatched."
>+             data_type="uint64"
>+             units="threads"
>+             semantic_type="event"
>+             equation="A 4 READ"
>+             mdapi_group="EU Array/Compute Shader"
>+             mdapi_usage_flags="Tier3 Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="Shader Memory Accesses"
>+             symbol_name="ShaderMemoryAccesses"
>+             underscore_name="shader_memory_accesses"
>+             description="The total number of shader memory accesses to L3."
>+             data_type="uint64"
>+             units="messages"
>+             semantic_type="event"
>+             equation="A 32 READ"
>+             mdapi_group="L3/Data Port"
>+             mdapi_usage_flags="Tier3 Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="Shader Atomic Memory Accesses"
>+             symbol_name="ShaderAtomics"
>+             underscore_name="shader_atomics"
>+             description="The total number of shader atomic memory accesses."
>+             data_type="uint64"
>+             units="messages"
>+             semantic_type="event"
>+             equation="A 34 READ"
>+             mdapi_group="L3/Data Port/Atomics"
>+             mdapi_usage_flags="Tier3 Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="Shader Barrier Messages"
>+             symbol_name="ShaderBarriers"
>+             underscore_name="shader_barriers"
>+             description="The total number of shader barrier messages."
>+             data_type="uint64"
>+             units="messages"
>+             semantic_type="event"
>+             equation="A 35 READ"
>+             mdapi_group="EU Array/Barrier"
>+             mdapi_usage_flags="Tier3 Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="SLM Reads"
>+             symbol_name="SlmReads"
>+             underscore_name="slm_reads"
>+             description="The total number of reads from shared local memory."
>+             data_type="uint64"
>+             max_equation="$GpuCoreClocks $EuSubslicesTotalCount UMUL"
>+             units="events"
>+             semantic_type="event"
>+             equation="A 30 READ"
>+             mdapi_group="L3/Data Port/SLM"
>+             mdapi_usage_flags="Tier3 Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="SLM Writes"
>+             symbol_name="SlmWrites"
>+             underscore_name="slm_writes"
>+             description="The total number of writes to shared local memory."
>+             data_type="uint64"
>+             max_equation="$GpuCoreClocks $EuSubslicesTotalCount UMUL"
>+             units="events"
>+             semantic_type="event"
>+             equation="A 31 READ"
>+             mdapi_group="L3/Data Port/SLM"
>+             mdapi_usage_flags="Tier3 Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GTI Read Throughput"
>+             symbol_name="GtiReadThroughput"
>+             underscore_name="gti_read_throughput"
>+             description="The total number of GPU memory bytes read from GTI."
>+             data_type="uint64"
>+             max_equation="$GpuCoreClocks 64 UMUL"
>+             units="bytes"
>+             semantic_type="throughput"
>+             equation="128  A 36 READ UMUL"
>+             mdapi_group="GTI"
>+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GTI Write Throughput"
>+             symbol_name="GtiWriteThroughput"
>+             underscore_name="gti_write_throughput"
>+             description="The total number of GPU memory bytes written to GTI."
>+             data_type="uint64"
>+             max_equation="$GpuCoreClocks 64 UMUL"
>+             units="bytes"
>+             semantic_type="throughput"
>+             equation="128  A 37 READ UMUL"
>+             mdapi_group="GTI"
>+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EU Active"
>+             symbol_name="EU_ACTIVE_CYCLES"
>+             underscore_name="eu_active_cycles"
>+             description="The percentage of time in which the Execution Units were actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array"
>+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EU Stall"
>+             symbol_name="EU_STALL_CYCLES"
>+             underscore_name="eu_stall_cycles"
>+             description="The percentage of time in which the Execution Units were stalled."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array"
>+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EU FPU Pipe Active"
>+             symbol_name="EU_INST_EXECUTED_ALU0_ALL"
>+             underscore_name="eu_inst_executed_alu0_all"
>+             description="The percentage of time in which EU FPU INT64 pipeline was actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 9 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EM Pipe Active"
>+             symbol_name="EU_INST_EXECUTED_ALU1_ALL"
>+             underscore_name="eu_inst_executed_alu1_all"
>+             description="The percentage of time in which EU EM INT pipeline was actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 10 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="SYS Pipe Active"
>+             symbol_name="EU_INST_EXECUTED_SYSTOLIC_ALL"
>+             underscore_name="eu_inst_executed_systolic_all"
>+             description="The percentage of time in which EU SYS pipeline was actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="Send Pipe Active"
>+             symbol_name="EU_INST_EXECUTED_SEND_ALL"
>+             underscore_name="eu_inst_executed_send_all"
>+             description="The percentage of time in which EU send pipeline was actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 11 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EM JEU Instruction"
>+             symbol_name="EU_INST_EXECUTED_CONTROL_ALL"
>+             underscore_name="eu_inst_executed_control_all"
>+             description="The percentage of time in which JEU instruction were processed actively on EM INT pipeline."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EM And FPU Pipes Active"
>+             symbol_name="EU_PIPE_ALU0_AND_ALU1_ACTIVE_CYCLES"
>+             underscore_name="eu_pipe_alu0_and_alu1_active_cycles"
>+             description="The percentage of time in which EU EM INT and FPU INT64 pipelines were actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 15 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="SYS And FPU Pipes Active"
>+             symbol_name="EU_PIPE_ALU0_AND_SYSTOLIC_ACTIVE_CYCLES"
>+             underscore_name="eu_pipe_alu0_and_systolic_active_cycles"
>+             description="The percentage of time in which EU Systolic and FPU INT64 pipelines were actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 14 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EU Thread Occupancy"
>+             symbol_name="EU_THREADS_OCCUPANCY_ALL"
>+             underscore_name="eu_threads_occupancy_all"
>+             description="The percentage of time in which hardware threads occupied EUs."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="8 A 16 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array"
>+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="SYSMEM_TRANSACTION_READ"
>+             symbol_name="SYSMEM_TRANSACTION_READ"
>+             underscore_name="sysmem_transaction_read"
>+             description="The number of system memory reads (upstream)"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="C 7 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="SYSMEM_TRANSACTION_WRITE"
>+             symbol_name="SYSMEM_TRANSACTION_WRITE"
>+             underscore_name="sysmem_transaction_write"
>+             description="The number of system memory writes  (upstream)"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="C 6 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="HOST_TO_GPUMEM_TRANSACTION_READ"
>+             symbol_name="HOST_TO_GPUMEM_TRANSACTION_READ"
>+             underscore_name="host_to_gpumem_transaction_read"
>+             description="Host reads to GPU local (HBM) memory (downstream)"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="C 5 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="HOST_TO_GPUMEM_TRANSACTION_WRITE"
>+             symbol_name="HOST_TO_GPUMEM_TRANSACTION_WRITE"
>+             underscore_name="host_to_gpumem_transaction_write"
>+             description="Host writes to GPU local (HBM) memory (downstream)"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="C 4 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI0"
>+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI0"
>+             underscore_name="gpu_memory_request_queue_full_sqidi0"
>+             description="The The percentage of time in which SQ 0 is filled above a threshold (usually 48 entries)"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="C 3 READ 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI1"
>+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI1"
>+             underscore_name="gpu_memory_request_queue_full_sqidi1"
>+             description="The The percentage of time in which SQ 1 is filled above a threshold (usually 48 entries)"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="C 2 READ 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI2"
>+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI2"
>+             underscore_name="gpu_memory_request_queue_full_sqidi2"
>+             description="The The percentage of time in which SQ 2 is filled above a threshold (usually 48 entries)"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="C 1 READ 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI3"
>+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI3"
>+             underscore_name="gpu_memory_request_queue_full_sqidi3"
>+             description="The The percentage of time in which SQ 3 is filled above a threshold (usually 48 entries)"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="C 0 READ 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI4"
>+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI4"
>+             underscore_name="gpu_memory_request_queue_full_sqidi4"
>+             description="The The percentage of time in which SQ 4 is filled above a threshold (usually 48 entries)"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="B 7 READ 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI8"
>+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI8"
>+             underscore_name="gpu_memory_request_queue_full_sqidi8"
>+             description="The The percentage of time in which SQ 8 is filled above a threshold (usually 48 entries)"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="B 6 READ 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU_MEMORY_REQUEST_QUEUE_FULL _SQIDI12"
>+             symbol_name="GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI12"
>+             underscore_name="gpu_memory_request_queue_full_sqidi12"
>+             description="The The percentage of time in which SQ 12 is filled above a threshold (usually 48 entries)"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="B 5 READ 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <register_config type="NOA">
>+        <register type="NOA" address="0x00000D04" value="0x00000200" />
>+        <register type="NOA" address="0x00009884" value="0x0000000C" />
>+        <register type="NOA" address="0x00009888" value="0x14307FC0" />
>+        <register type="NOA" address="0x00009888" value="0x04306000" />
>+        <register type="NOA" address="0x00009888" value="0x14003400" />
>+        <register type="NOA" address="0x00009888" value="0x14013400" />
>+        <register type="NOA" address="0x00009888" value="0x14023400" />
>+        <register type="NOA" address="0x00009888" value="0x14033400" />
>+        <register type="NOA" address="0x00009888" value="0x14083400" />
>+        <register type="NOA" address="0x00009888" value="0x140C3400" />
>+        <register type="NOA" address="0x00009888" value="0x14043400" />
>+        <register type="NOA" address="0x00009888" value="0x1A100090" />
>+        <register type="NOA" address="0x00009888" value="0x1A110009" />
>+        <register type="NOA" address="0x00009888" value="0x00142000" />
>+        <register type="NOA" address="0x00009888" value="0x0050FFE0" />
>+        <register type="NOA" address="0x00009888" value="0x00300240" />
>+        <register type="NOA" address="0x00009888" value="0x0E300695" />
>+        <register type="NOA" address="0x00009888" value="0x10300824" />
>+        <register type="NOA" address="0x00009888" value="0x02300000" />
>+        <register type="NOA" address="0x00009888" value="0x00000002" />
>+        <register type="NOA" address="0x00009888" value="0x0E000080" />
>+        <register type="NOA" address="0x00009888" value="0x04000000" />
>+        <register type="NOA" address="0x00009888" value="0x00010002" />
>+        <register type="NOA" address="0x00009888" value="0x0E010002" />
>+        <register type="NOA" address="0x00009888" value="0x04010000" />
>+        <register type="NOA" address="0x00009888" value="0x00020002" />
>+        <register type="NOA" address="0x00009888" value="0x0C020080" />
>+        <register type="NOA" address="0x00009888" value="0x04020000" />
>+        <register type="NOA" address="0x00009888" value="0x00030002" />
>+        <register type="NOA" address="0x00009888" value="0x0C030002" />
>+        <register type="NOA" address="0x00009888" value="0x04030000" />
>+        <register type="NOA" address="0x00009888" value="0x00080002" />
>+        <register type="NOA" address="0x00009888" value="0x0A080002" />
>+        <register type="NOA" address="0x00009888" value="0x04080000" />
>+        <register type="NOA" address="0x00009888" value="0x00128000" />
>+        <register type="NOA" address="0x00009888" value="0x00160800" />
>+        <register type="NOA" address="0x00009888" value="0x000C0002" />
>+        <register type="NOA" address="0x00009888" value="0x080C0080" />
>+        <register type="NOA" address="0x00009888" value="0x040C0000" />
>+        <register type="NOA" address="0x00009888" value="0x00040002" />
>+        <register type="NOA" address="0x00009888" value="0x0A040080" />
>+        <register type="NOA" address="0x00009888" value="0x04040000" />
>+        <register type="NOA" address="0x00009888" value="0x2C500000" />
>+        <register type="NOA" address="0x00009888" value="0x2E500400" />
>+        <register type="NOA" address="0x00009888" value="0x30500000" />
>+        <register type="NOA" address="0x00009888" value="0x18500000" />
>+        <register type="NOA" address="0x00009888" value="0x32500A05" />
>+        <register type="NOA" address="0x00009888" value="0x20500030" />
>+        <register type="NOA" address="0x00009888" value="0x22500603" />
>+        <register type="NOA" address="0x00009888" value="0x24500030" />
>+        <register type="NOA" address="0x00009888" value="0x26500603" />
>+        <register type="NOA" address="0x00009884" value="0x00000008" />
>+        <register type="NOA" address="0x00009888" value="0x01404400" />
>+        <register type="NOA" address="0x00009888" value="0x01414400" />
>+        <register type="NOA" address="0x00009888" value="0x030755A0" />
>+        <register type="NOA" address="0x00009888" value="0x0308AA00" />
>+        <register type="NOA" address="0x00009888" value="0x01000040" />
>+        <register type="NOA" address="0x00009888" value="0x01010040" />
>+        <register type="NOA" address="0x00009888" value="0x01021000" />
>+        <register type="NOA" address="0x00009888" value="0x01036400" />
>+        <register type="NOA" address="0x00009888" value="0x0104A800" />
>+        <register type="NOA" address="0x00009888" value="0x03045555" />
>+        <register type="NOA" address="0x00009888" value="0x0305555A" />
>+        <register type="NOA" address="0x00009888" value="0x0106FC00" />
>+        <register type="NOA" address="0x00009888" value="0x01190400" />
>+        <register type="NOA" address="0x00009888" value="0x011B0400" />
>+        <register type="NOA" address="0x00009888" value="0x011C4800" />
>+        <register type="NOA" address="0x00009888" value="0x011E4000" />
>+        <register type="NOA" address="0x00009888" value="0x01108000" />
>+    </register_config>
>+    <register_config type="OA">
>+        <register type="OA" address="0x0000D920" value="0x00000000" />
>+        <register type="OA" address="0x0000D900" value="0x00000000" />
>+        <register type="OA" address="0x0000D904" value="0x00800000" />
>+        <register type="OA" address="0x0000D910" value="0x00000000" />
>+        <register type="OA" address="0x0000D914" value="0x00800000" />
>+        <register type="OA" address="0x0000DC40" value="0x00000000" />
>+        <register type="OA" address="0x00002B2C" value="0x00000000" />
>+    </register_config>
>+    <register_config type="FLEX">
>+        <register type="FLEX" address="0x0000E458" value="0x00005004" />
>+        <register type="FLEX" address="0x0000E558" value="0x00001000" />
>+        <register type="FLEX" address="0x0000E658" value="0x00001002" />
>+        <register type="FLEX" address="0x0000E758" value="0x0000A009" />
>+        <register type="FLEX" address="0x0000E45C" value="0x00008003" />
>+    </register_config>
>+  </set>
>+
>+  <set name="TestOa"
>+       chipset="PVC"
>+       symbol_name="TestOa"
>+       underscore_name="test_oa"
>+       mdapi_supported_apis="VK OGL OCL IO"
>+       hw_config_guid="339a376a-4696-4e0d-812a-5fd13b0e1aa8"
>+       >
>+    <counter name="GPU Time Elapsed"
>+             symbol_name="GpuTime"
>+             underscore_name="gpu_time"
>+             description="Time elapsed on the GPU during the measurement."
>+             data_type="uint64"
>+             units="ns"
>+             semantic_type="duration"
>+             equation="GPU_TIME 0 READ 1000000000 UMUL $GpuTimestampFrequency UDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU Core Clocks"
>+             symbol_name="GpuCoreClocks"
>+             underscore_name="gpu_core_clocks"
>+             description="The total number of GPU core clocks elapsed during the measurement."
>+             data_type="uint64"
>+             units="cycles"
>+             semantic_type="event"
>+             equation="GPU_CLOCK 0 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Tier1 Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="TestCounter0"
>+             symbol_name="Counter0"
>+             underscore_name="counter0"
>+             description="HW test counter 0. Factor: 0.0"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="B 0 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="TestCounter1"
>+             symbol_name="Counter1"
>+             underscore_name="counter1"
>+             description="HW test counter 1. Factor: 1.0"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="B 1 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="TestCounter3"
>+             symbol_name="Counter3"
>+             underscore_name="counter3"
>+             description="HW test counter 3. Factor: 0.5"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="B 2 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="TestCounter4"
>+             symbol_name="Counter4"
>+             underscore_name="counter4"
>+             description="HW test counter 4. Factor: 0.3333"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="B 3 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="TestCounter5"
>+             symbol_name="Counter5"
>+             underscore_name="counter5"
>+             description="HW test counter 5. Factor: 0.3333"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="B 4 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="TestCounter8"
>+             symbol_name="Counter8"
>+             underscore_name="counter8"
>+             description="HW test counter 8. Should be equal to 1 in IOStream or in OAG query mode"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="C 7 READ"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="L3_BANK_INPUT_AVAILABLE _L3BANK0"
>+             symbol_name="L3_BANK_INPUT_AVAILABLE_L3BANK0"
>+             underscore_name="l3_bank_input_available_l3_bank0"
>+             description="The percentage of time in which l3 bank 0 input is available"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="C 6 READ 100 UMUL $GpuCoreClocks FDIV"
>+             availability="1"
>+             mdapi_group="GTI/L3"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="subslice_bank"
>+             />
>+    <counter name="L3_OUTPUT_READY _L3BANK0"
>+             symbol_name="L3_OUTPUT_READY_L3BANK0"
>+             underscore_name="l3_output_ready_l3_bank0"
>+             description="The percentage of time in which l3 bank 0 output is ready"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="C 3 READ 100 UMUL $GpuCoreClocks FDIV"
>+             availability="1"
>+             mdapi_group="GTI/L3"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="subslice_bank"
>+             />
>+    <counter name="L3_READ _L3BANK0"
>+             symbol_name="L3_READ_L3BANK0"
>+             underscore_name="l3_read_l3_bank0"
>+             description="The number of L3 bank 0 read requests"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="C 5 READ"
>+             availability="1"
>+             mdapi_group="GTI/L3"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="subslice_bank"
>+             />
>+    <counter name="L3_WRITE _L3BANK0"
>+             symbol_name="L3_WRITE_L3BANK0"
>+             underscore_name="l3_write_l3_bank0"
>+             description="The number of L3 Bank 0 write requests"
>+             data_type="uint64"
>+             units="events"
>+             semantic_type="event"
>+             equation="C 4 READ"
>+             availability="1"
>+             mdapi_group="GTI/L3"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="subslice_bank"
>+             />
>+    <counter name="THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES _DUALSUBSLICE0"
>+             symbol_name="THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_DUALSUBSLICE0"
>+             underscore_name="threadgroup_dispatch_queue0_active_cycles_dualsubslice0"
>+             description="The percentage of time in which non-PS thread is ready for dispatch in thread dispatcher 0 queue 0"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="B 5 READ 100 UMUL $GpuCoreClocks FDIV"
>+             availability="$DualSubsliceMask 1 AND"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="dualsubslice"
>+             />
>+    <counter name="THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES _DUALSUBSLICE0"
>+             symbol_name="THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_DUALSUBSLICE0"
>+             underscore_name="threadgroup_dispatch_queue1_active_cycles_dualsubslice0"
>+             description="The percentage of time in which non-PS thread is ready for dispatch in thread dispatcher 0 queue 1"
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="B 6 READ 100 UMUL $GpuCoreClocks FDIV"
>+             availability="$DualSubsliceMask 1 AND"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="dualsubslice"
>+             />
>+    <counter name="EU Active"
>+             symbol_name="EuActive"
>+             underscore_name="eu_active"
>+             description="The percentage of time in which the Execution Units were actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array"
>+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EU Stall"
>+             symbol_name="EuStall"
>+             underscore_name="eu_stall"
>+             description="The percentage of time in which the Execution Units were stalled."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array"
>+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EU Thread Occupancy"
>+             symbol_name="EuThreadOccupancy"
>+             underscore_name="eu_thread_occupancy"
>+             description="The percentage of time in which hardware threads occupied EUs."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="8 A 10 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array"
>+             mdapi_usage_flags="Tier2 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EU FPU Pipe Active"
>+             symbol_name="FpuActive"
>+             underscore_name="fpu_active"
>+             description="The percentage of time in which EU FPU INT64 pipeline was actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 11 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EM Pipe Active"
>+             symbol_name="EmActive"
>+             underscore_name="em_active"
>+             description="The percentage of time in which EU EM INT pipeline was actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="SYS Pipe Active"
>+             symbol_name="SysActive"
>+             underscore_name="sys_active"
>+             description="The percentage of time in which EU SYS pipeline was actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="EM And FPU Pipes Active"
>+             symbol_name="EmFpuActive"
>+             underscore_name="em_fpu_active"
>+             description="The percentage of time in which EU EM INT and FPU INT64 pipelines were actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 9 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="SYS And FPU Pipes Active"
>+             symbol_name="SysFpuActive"
>+             underscore_name="sys_fpu_active"
>+             description="The percentage of time in which EU Systolic and FPU INT64 pipelines were actively processing."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 14 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="EU Array/Pipes"
>+             mdapi_usage_flags="Tier3 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="CS Threads Dispatched"
>+             symbol_name="CsThreads"
>+             underscore_name="cs_threads"
>+             description="The total number of compute shader hardware threads dispatched."
>+             data_type="uint64"
>+             units="threads"
>+             semantic_type="event"
>+             equation="A 4 READ"
>+             mdapi_group="EU Array/Compute Shader"
>+             mdapi_usage_flags="Tier3 Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GPU Busy"
>+             symbol_name="GpuBusy"
>+             underscore_name="gpu_busy"
>+             description="The percentage of time in which the GPU has been processing GPU commands."
>+             data_type="float"
>+             max_equation="100"
>+             units="percent"
>+             semantic_type="duration"
>+             equation="A 0 READ 100 UMUL $GpuCoreClocks FDIV"
>+             mdapi_group="GPU"
>+             mdapi_usage_flags="Tier1 Overview System Frame"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="Gti Read Transactions"
>+             symbol_name="GtiReadTransactions"
>+             underscore_name="gti_read_transactions"
>+             description="The total number of read transactions sent to GTI interfaces"
>+             data_type="uint64"
>+             max_equation="$GpuCoreClocks $EuSlicesTotalCount 4 UGT 8 UMUL $EuSlicesTotalCount 4 ULTE $EuSlicesTotalCount 1 UADD 0x6 AND UMUL UADD UMUL"
>+             units="messages"
>+             semantic_type="event"
>+             equation="A 36 READ"
>+             mdapi_group="GTI"
>+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <counter name="GTI Write Transactions"
>+             symbol_name="GtiWriteTransactions"
>+             underscore_name="gti_write_transactions"
>+             description="The total number of write transactions sent to GTI interfaces"
>+             data_type="uint64"
>+             max_equation="$GpuCoreClocks $EuSlicesTotalCount 4 UGT 8 UMUL $EuSlicesTotalCount 4 ULTE $EuSlicesTotalCount 1 UADD 0x6 AND UMUL UADD UMUL"
>+             units="messages"
>+             semantic_type="event"
>+             equation="A 37 READ"
>+             mdapi_group="GTI"
>+             mdapi_usage_flags="Tier1 Overview System Frame Batch Draw"
>+             mdapi_supported_apis=""
>+             mdapi_hw_unit_type="gpu"
>+             />
>+    <register_config type="NOA">
>+        <register type="NOA" address="0x00000D04" value="0x00000200" />
>+        <register type="NOA" address="0x00009884" value="0x00000008" />
>+        <register type="NOA" address="0x00009888" value="0x3B410000" />
>+        <register type="NOA" address="0x00009888" value="0x0140000A" />
>+        <register type="NOA" address="0x00009888" value="0x33406A80" />
>+        <register type="NOA" address="0x00009888" value="0x07410006" />
>+        <register type="NOA" address="0x00009888" value="0x17410033" />
>+        <register type="NOA" address="0x00009888" value="0x03410000" />
>+        <register type="NOA" address="0x00009888" value="0x4F410000" />
>+        <register type="NOA" address="0x00009888" value="0x01030005" />
>+        <register type="NOA" address="0x00009888" value="0x03035540" />
>+        <register type="NOA" address="0x00009888" value="0x0104000A" />
>+        <register type="NOA" address="0x00009888" value="0x0304AA80" />
>+        <register type="NOA" address="0x00009888" value="0x1D500003" />
>+        <register type="NOA" address="0x00009888" value="0x02E71540" />
>+        <register type="NOA" address="0x00009888" value="0x02EA2A80" />
>+        <register type="NOA" address="0x00009888" value="0x02E82A80" />
>+        <register type="NOA" address="0x00009888" value="0x00F07803" />
>+        <register type="NOA" address="0x00009888" value="0x00F10005" />
>+        <register type="NOA" address="0x00009888" value="0x02F12A80" />
>+        <register type="NOA" address="0x00009888" value="0x00F20003" />
>+        <register type="NOA" address="0x00009888" value="0x22F30012" />
>+        <register type="NOA" address="0x00009888" value="0x26F32490" />
>+        <register type="NOA" address="0x00009888" value="0x00F4000A" />
>+        <register type="NOA" address="0x00009888" value="0x22D3003F" />
>+        <register type="NOA" address="0x00009884" value="0x00000004" />
>+        <register type="NOA" address="0x00009888" value="0x044C2000" />
>+        <register type="NOA" address="0x00009888" value="0x064C6000" />
>+        <register type="NOA" address="0x00009888" value="0x004C0010" />
>+        <register type="NOA" address="0x00009888" value="0x0E4C0180" />
>+        <register type="NOA" address="0x00009888" value="0x104C0305" />
>+        <register type="NOA" address="0x00009888" value="0x124C0007" />
>+        <register type="NOA" address="0x00009884" value="0x0000000C" />
>+        <register type="NOA" address="0x00009888" value="0x0050F803" />
>+        <register type="NOA" address="0x00009888" value="0x1C500000" />
>+        <register type="NOA" address="0x00009888" value="0x1E500000" />
>+        <register type="NOA" address="0x00009888" value="0x28500000" />
>+        <register type="NOA" address="0x00009888" value="0x18500000" />
>+        <register type="NOA" address="0x00009888" value="0x20500000" />
>+        <register type="NOA" address="0x00009888" value="0x22500C06" />
>+        <register type="NOA" address="0x00009888" value="0x24500060" />
>+        <register type="NOA" address="0x00009888" value="0x26501606" />
>+        <register type="NOA" address="0x00009884" value="0x00000000" />
>+        <register type="NOA" address="0x00009888" value="0x28036400" />
>+        <register type="NOA" address="0x00009888" value="0x2A030080" />
>+        <register type="NOA" address="0x00009888" value="0x06031300" />
>+        <register type="NOA" address="0x00009888" value="0x08030FB0" />
>+        <register type="NOA" address="0x00009888" value="0x00030000" />
>+        <register type="NOA" address="0x00009888" value="0x00C00005" />
>+        <register type="NOA" address="0x00009888" value="0x00C1000F" />
>+        <register type="NOA" address="0x00009888" value="0x00C2000F" />
>+        <register type="NOA" address="0x00009888" value="0x00C3001B" />
>+        <register type="NOA" address="0x00009884" value="0x00000000" />
>+        <register type="NOA" address="0x00009888" value="0x5C030002" />
>+    </register_config>
>+    <register_config type="OA">
>+        <register type="OA" address="0x0000D920" value="0x00000000" />
>+        <register type="OA" address="0x0000D900" value="0x00000000" />
>+        <register type="OA" address="0x0000D904" value="0xF0800000" />
>+        <register type="OA" address="0x0000D910" value="0x00000000" />
>+        <register type="OA" address="0x0000D914" value="0x70800000" />
>+        <register type="OA" address="0x0000DC40" value="0x007F0000" />
>+        <register type="OA" address="0x0000D940" value="0x00000004" />
>+        <register type="OA" address="0x0000D944" value="0x0000FFFF" />
>+        <register type="OA" address="0x0000DC00" value="0x00000004" />
>+        <register type="OA" address="0x0000DC04" value="0x0000FFFF" />
>+        <register type="OA" address="0x0000D948" value="0x00000003" />
>+        <register type="OA" address="0x0000D94C" value="0x0000FFFF" />
>+        <register type="OA" address="0x0000DC08" value="0x00000003" />
>+        <register type="OA" address="0x0000DC0C" value="0x0000FFFF" />
>+        <register type="OA" address="0x0000D950" value="0x00100002" />
>+        <register type="OA" address="0x0000D954" value="0x0000FFFB" />
>+        <register type="OA" address="0x0000DC10" value="0x00100002" />
>+        <register type="OA" address="0x0000DC14" value="0x0000FFFB" />
>+        <register type="OA" address="0x0000D958" value="0x00100002" />
>+        <register type="OA" address="0x0000D95C" value="0x0000FFE7" />
>+        <register type="OA" address="0x0000DC18" value="0x00100002" />
>+        <register type="OA" address="0x0000DC1C" value="0x0000FFE7" />
>+        <register type="OA" address="0x0000D960" value="0x00100042" />
>+        <register type="OA" address="0x0000D964" value="0x0000FFF7" />
>+        <register type="OA" address="0x0000DC20" value="0x00100042" />
>+        <register type="OA" address="0x0000DC24" value="0x0000FFF7" />
>+        <register type="OA" address="0x0000D968" value="0x00000002" />
>+        <register type="OA" address="0x0000D96C" value="0x0000FFFE" />
>+        <register type="OA" address="0x0000DC28" value="0x00000002" />
>+        <register type="OA" address="0x0000DC2C" value="0x0000FFFE" />
>+        <register type="OA" address="0x0000D970" value="0x00000002" />
>+        <register type="OA" address="0x0000D974" value="0x0000FFFD" />
>+        <register type="OA" address="0x0000DC30" value="0x00000002" />
>+        <register type="OA" address="0x0000DC34" value="0x0000FFFD" />
>+        <register type="OA" address="0x00002B2C" value="0x00000000" />
>+    </register_config>
>+    <register_config type="FLEX">
>+        <register type="FLEX" address="0x0000E458" value="0x00005004" />
>+        <register type="FLEX" address="0x0000E558" value="0x00008003" />
>+        <register type="FLEX" address="0x0000E658" value="0x00001000" />
>+        <register type="FLEX" address="0x0000E758" value="0x0000A009" />
>+    </register_config>
>+  </set>
>+
>+</metrics>
>diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c
>index 576358fe22..d2d0687d9a 100644
>--- a/lib/xe/xe_oa.c
>+++ b/lib/xe/xe_oa.c
>@@ -36,6 +36,7 @@
> #include "xe_oa_metrics_acmgt3.h"
> #include "xe_oa_metrics_mtlgt2.h"
> #include "xe_oa_metrics_mtlgt3.h"
>+#include "xe_oa_metrics_pvc.h"
> #include "xe_oa_metrics_lnl.h"
>
> static struct intel_xe_perf_logical_counter_group *
>@@ -296,6 +297,9 @@ intel_xe_perf_for_devinfo(uint32_t device_id,
> 			intel_xe_perf_load_metrics_acmgt3(perf);
> 		else
> 			return unsupported_xe_oa_platform(perf);
>+	} else if (devinfo->is_pontevecchio) {
>+		perf->devinfo.eu_threads_count = 8;
>+		intel_xe_perf_load_metrics_pvc(perf);
> 	} else if (intel_graphics_ver(device_id) >= IP_VER(20, 0)) {
> 		intel_xe_perf_load_metrics_lnl(perf);
> 	} else {
>-- 
>2.41.0
>

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
  2024-07-01  2:52 ` [PATCH i-g-t 01/14] lib/xe/oa: Add PVC support Ashutosh Dixit
@ 2024-07-01  2:52 ` Ashutosh Dixit
  2024-07-01 16:53   ` Dixit, Ashutosh
  2024-07-01 19:47   ` Umesh Nerlige Ramappa
  2024-07-01  2:52 ` [PATCH i-g-t 03/14] tests/intel/xe_oa: Add some negative tests Ashutosh Dixit
                   ` (15 subsequent siblings)
  17 siblings, 2 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:52 UTC (permalink / raw)
  To: igt-dev

Add "xe-ref-count" and "sysctl-defaults" subtests.

v2: Set INTEL_XE_DEVICE_MAX_SUBSLICES to 64 (value on PVC)

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 lib/xe/xe_oa.h      |   2 +-
 tests/intel/xe_oa.c | 805 ++++++++++++++++++++++++++++++++++++++++++++
 tests/meson.build   |   2 +
 3 files changed, 808 insertions(+), 1 deletion(-)
 create mode 100644 tests/intel/xe_oa.c

diff --git a/lib/xe/xe_oa.h b/lib/xe/xe_oa.h
index f6f2768b00..27ebb4b217 100644
--- a/lib/xe/xe_oa.h
+++ b/lib/xe/xe_oa.h
@@ -19,7 +19,7 @@ extern "C" {
 #define _DIV_ROUND_UP(a, b)  (((a) + (b) - 1) / (b))
 
 #define INTEL_XE_DEVICE_MAX_SLICES           (8)
-#define INTEL_XE_DEVICE_MAX_SUBSLICES        (32)
+#define INTEL_XE_DEVICE_MAX_SUBSLICES        (64) /* Maximum on XE_PVC */
 #define INTEL_XE_DEVICE_MAX_EUS_PER_SUBSLICE (16) /* Maximum on gfx12 */
 
 enum intel_xe_oa_format_name {
diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
new file mode 100644
index 0000000000..2b5044b116
--- /dev/null
+++ b/tests/intel/xe_oa.c
@@ -0,0 +1,805 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <signal.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <sys/times.h>
+#include <sys/types.h>
+#include <dirent.h>
+#include <time.h>
+#include <poll.h>
+#include <math.h>
+
+#include "drm.h"
+#include "igt.h"
+#include "igt_device.h"
+#include "igt_sysfs.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include "xe/xe_oa.h"
+
+/**
+ * TEST: perf
+ * Description: Test the Xe OA metrics streaming interface
+ * Category: Core
+ * Mega feature: Performance interface
+ * Sub-category: Performance tests
+ * Functionality: oa
+ * Feature: xe streaming interface, oa
+ * Test category: Perf
+ */
+
+#define OA_MI_REPORT_PERF_COUNT		((0x28 << 23) | (4 - 2))
+
+#define OAREPORT_REASON_MASK           0x3f
+#define OAREPORT_REASON_SHIFT          19
+#define OAREPORT_REASON_TIMER          (1<<0)
+#define OAREPORT_REASON_INTERNAL       (3<<1)
+#define OAREPORT_REASON_CTX_SWITCH     (1<<3)
+#define OAREPORT_REASON_GO             (1<<4)
+#define OAREPORT_REASON_CLK_RATIO      (1<<5)
+
+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET	(1 << 19)
+#define PIPE_CONTROL_SYNC_GFDT	  (1 << 17)
+#define PIPE_CONTROL_NO_WRITE	   (0 << 14)
+#define PIPE_CONTROL_WRITE_IMMEDIATE    (1 << 14)
+#define PIPE_CONTROL_WRITE_DEPTH_COUNT  (2 << 14)
+#define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
+#define PIPE_CONTROL_INSTRUCTION_INVALIDATE (1 << 11)
+#define PIPE_CONTROL_ISP_DIS	    (1 << 9)
+#define PIPE_CONTROL_INTERRUPT_ENABLE   (1 << 8)
+/* GT */
+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE      (1 << 5)
+#define PIPE_CONTROL_PPGTT_WRITE	(0 << 2)
+#define PIPE_CONTROL_GLOBAL_GTT_WRITE   (1 << 2)
+
+#define MAX_OA_BUF_SIZE (16 * 1024 * 1024)
+#define OA_BUFFER_SIZE MAX_OA_BUF_SIZE
+
+#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK 0x03fffffc
+/*
+ * Engine specific registers defined as offsets from engine->mmio_base. For
+ * these registers, OR bit[0] with 1 so we can add the mmio_base when running
+ * engine specific test.
+ */
+#define MMIO_BASE_OFFSET 0x1
+
+#define OAG_OASTATUS (0xdafc)
+#define OAG_PERF_COUNTER_B(idx) (0xDA94 + 4 * (idx))
+#define OAG_OATAILPTR (0xdb04)
+#define OAG_OATAILPTR_MASK 0xffffffc0
+#define OAG_OABUFFER (0xdb08)
+
+#define XE_OA_MAX_SET_PROPERTIES 16
+
+#define ADD_PROPS(_head, _tail, _key, _value)	\
+	do { \
+		igt_assert((_tail - _head) < (XE_OA_MAX_SET_PROPERTIES * 2)); \
+		*_tail++ = DRM_XE_OA_PROPERTY_##_key; \
+		*_tail++ = _value; \
+	} while (0)
+
+struct accumulator {
+#define MAX_RAW_OA_COUNTERS 62
+	enum intel_xe_oa_format_name format;
+
+	uint64_t deltas[MAX_RAW_OA_COUNTERS];
+};
+
+/* OA unit types */
+enum {
+	OAG,
+	OAR,
+	OAM,
+
+	MAX_OA_TYPE,
+};
+
+struct oa_format {
+	const char *name;
+	size_t size;
+	int a40_high_off; /* bytes */
+	int a40_low_off;
+	int n_a40;
+	int a64_off;
+	int n_a64;
+	int a_off;
+	int n_a;
+	int first_a;
+	int first_a40;
+	int b_off;
+	int n_b;
+	int c_off;
+	int n_c;
+	int oa_type; /* of enum intel_xe_oa_format_name */
+	bool report_hdr_64bit;
+	int counter_select;
+	int counter_size;
+	int bc_report;
+};
+
+static struct oa_format gen12_oa_formats[XE_OA_FORMAT_MAX] = {
+	[XE_OA_FORMAT_A32u40_A4u32_B8_C8] = {
+		"A32u40_A4u32_B8_C8", .size = 256,
+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
+		.a_off = 144, .n_a = 4, .first_a = 32,
+		.b_off = 192, .n_b = 8,
+		.c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAG,
+		.counter_select = 5,
+	},
+};
+
+static struct oa_format dg2_oa_formats[XE_OA_FORMAT_MAX] = {
+	[XE_OAR_FORMAT_A32u40_A4u32_B8_C8] = {
+		"A32u40_A4u32_B8_C8", .size = 256,
+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
+		.a_off = 144, .n_a = 4, .first_a = 32,
+		.b_off = 192, .n_b = 8,
+		.c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAR,
+		.counter_select = 5,
+	},
+	/* This format has A36 and A37 interleaved with high bytes of some A
+	 * counters, so we will accumulate only subset of counters.
+	 */
+	[XE_OA_FORMAT_A24u40_A14u32_B8_C8] = {
+		"A24u40_A14u32_B8_C8", .size = 256,
+		/* u40: A4 - A23 */
+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 20, .first_a40 = 4,
+		/* u32: A0 - A3 */
+		.a_off = 16, .n_a = 4,
+		.b_off = 192, .n_b = 8,
+		.c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAG,
+		.counter_select = 5,
+	},
+	/* This format has 24 u64 counters ranging from A0 - A35. Until we come
+	 * up with a better mechanism to define missing counters, we will use a
+	 * subset of counters that are indexed by one-increments - A28 - A35.
+	 */
+	[XE_OAC_FORMAT_A24u64_B8_C8] = {
+		"OAC_A24u64_B8_C8", .size = 320,
+		.a64_off = 160, .n_a64 = 8,
+		.b_off = 224, .n_b = 8,
+		.c_off = 256, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAC,
+		.report_hdr_64bit = true,
+		.counter_select = 1, },
+};
+
+static struct oa_format mtl_oa_formats[XE_OA_FORMAT_MAX] = {
+	[XE_OAR_FORMAT_A32u40_A4u32_B8_C8] = {
+		"A32u40_A4u32_B8_C8", .size = 256,
+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
+		.a_off = 144, .n_a = 4, .first_a = 32,
+		.b_off = 192, .n_b = 8,
+		.c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAR,
+		.counter_select = 5,
+	},
+	/* This format has A36 and A37 interleaved with high bytes of some A
+	 * counters, so we will accumulate only subset of counters.
+	 */
+	[XE_OA_FORMAT_A24u40_A14u32_B8_C8] = {
+		"A24u40_A14u32_B8_C8", .size = 256,
+		/* u40: A4 - A23 */
+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 20, .first_a40 = 4,
+		/* u32: A0 - A3 */
+		.a_off = 16, .n_a = 4,
+		.b_off = 192, .n_b = 8,
+		.c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAG,
+		.counter_select = 5,
+	},
+
+	/* Treat MPEC countes as A counters for now */
+	[XE_OAM_FORMAT_MPEC8u64_B8_C8] = {
+		"MPEC8u64_B8_C8", .size = 192,
+		.a64_off = 32, .n_a64 = 8,
+		.b_off = 96, .n_b = 8,
+		.c_off = 128, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAM_MPEC,
+		.report_hdr_64bit = true,
+		.counter_select = 1,
+	},
+	[XE_OAM_FORMAT_MPEC8u32_B8_C8] = {
+		"MPEC8u32_B8_C8", .size = 128,
+		.a_off = 32, .n_a = 8,
+		.b_off = 64, .n_b = 8,
+		.c_off = 96, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAM_MPEC,
+		.report_hdr_64bit = true,
+		.counter_select = 2,
+	},
+	/* This format has 24 u64 counters ranging from A0 - A35. Until we come
+	 * up with a better mechanism to define missing counters, we will use a
+	 * subset of counters that are indexed by one-increments - A28 - A35.
+	 */
+	[XE_OAC_FORMAT_A24u64_B8_C8] = {
+		"OAC_A24u64_B8_C8", .size = 320,
+		.a64_off = 160, .n_a64 = 8,
+		.b_off = 224, .n_b = 8,
+		.c_off = 256, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAC,
+		.report_hdr_64bit = true,
+		.counter_select = 1, },
+};
+
+static struct oa_format lnl_oa_formats[XE_OA_FORMAT_MAX] = {
+	[XE_OA_FORMAT_PEC64u64] = {
+		"PEC64u64", .size = 576,
+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
+		.report_hdr_64bit = true,
+		.counter_select = 1,
+		.counter_size = 1,
+		.bc_report = 0 },
+	[XE_OA_FORMAT_PEC64u64_B8_C8] = {
+		"PEC64u64_B8_C8", .size = 640,
+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
+		.report_hdr_64bit = true,
+		.counter_select = 1,
+		.counter_size = 1,
+		.bc_report = 1 },
+	[XE_OA_FORMAT_PEC64u32] = {
+		"PEC64u32", .size = 320,
+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
+		.report_hdr_64bit = true,
+		.counter_select = 1,
+		.counter_size = 0,
+		.bc_report = 0 },
+	[XE_OA_FORMAT_PEC32u64_G1] = {
+		"PEC32u64_G1", .size = 320,
+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
+		.report_hdr_64bit = true,
+		.counter_select = 5,
+		.counter_size = 1,
+		.bc_report = 0 },
+	[XE_OA_FORMAT_PEC32u32_G1] = {
+		"PEC32u32_G1", .size = 192,
+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
+		.report_hdr_64bit = true,
+		.counter_select = 5,
+		.counter_size = 0,
+		.bc_report = 0 },
+	[XE_OA_FORMAT_PEC32u64_G2] = {
+		"PEC32u64_G2", .size = 320,
+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
+		.report_hdr_64bit = true,
+		.counter_select = 6,
+		.counter_size = 1,
+		.bc_report = 0 },
+	[XE_OA_FORMAT_PEC32u32_G2] = {
+		"PEC32u64_G2", .size = 192,
+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
+		.report_hdr_64bit = true,
+		.counter_select = 6,
+		.counter_size = 0,
+		.bc_report = 0 },
+	[XE_OA_FORMAT_PEC36u64_G1_32_G2_4] = {
+		"PEC36u64_G1_32_G2_4", .size = 320,
+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
+		.report_hdr_64bit = true,
+		.counter_select = 3,
+		.counter_size = 1,
+		.bc_report = 0 },
+	[XE_OA_FORMAT_PEC36u64_G1_4_G2_32] = {
+		"PEC36u64_G1_4_G2_32_G2", .size = 320,
+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
+		.report_hdr_64bit = true,
+		.counter_select = 4,
+		.counter_size = 1,
+		.bc_report = 0 },
+};
+
+static int drm_fd = -1;
+static int sysfs = -1;
+static int pm_fd = -1;
+static int stream_fd = -1;
+static uint32_t devid;
+
+struct drm_xe_engine_class_instance default_hwe;
+
+static struct intel_xe_perf *intel_xe_perf;
+static uint64_t oa_exp_1_millisec;
+struct intel_mmio_data mmio_data;
+
+static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
+{
+	const char *test_set_name = NULL;
+	struct intel_xe_perf_metric_set *metric_set_iter;
+	struct intel_xe_perf_metric_set *test_set = NULL;
+
+	if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
+	    hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE)
+		test_set_name = "TestOa";
+	else if ((hwe->engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ||
+		  hwe->engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE) &&
+		 HAS_OAM(devid))
+		test_set_name = "MediaSet1";
+	else
+		igt_assert(!"reached");
+
+	igt_list_for_each_entry(metric_set_iter, &intel_xe_perf->metric_sets, link) {
+		if (strcmp(metric_set_iter->symbol_name, test_set_name) == 0) {
+			test_set = metric_set_iter;
+			break;
+		}
+	}
+
+	igt_assert(test_set);
+
+	/*
+	 * configuration was loaded in init_sys_info() ->
+	 * intel_xe_perf_load_perf_configs(), and test_set->perf_oa_metrics_set
+	 * should point to metric id returned by the config add ioctl. 0 is
+	 * invalid.
+	 */
+	igt_assert_neq_u64(test_set->perf_oa_metrics_set, 0);
+
+	igt_debug("engine %d:%d - %s metric set UUID = %s\n",
+		  hwe->engine_class,
+		  hwe->engine_instance,
+		  test_set->symbol_name,
+		  test_set->hw_config_guid);
+
+	return test_set;
+}
+#define default_test_set metric_set(&default_hwe)
+
+static void set_fd_flags(int fd, int flags)
+{
+	int old = fcntl(fd, F_GETFL, 0);
+
+	igt_assert_lte(0, old);
+	igt_assert_eq(0, fcntl(fd, F_SETFL, old | flags));
+}
+
+static u32 get_stream_status(int fd)
+{
+	struct drm_xe_oa_stream_status status;
+
+	do_ioctl(fd, DRM_XE_PERF_IOCTL_STATUS, &status);
+
+	return status.oa_status;
+}
+
+static void
+dump_report(const uint32_t *report, uint32_t size, const char *message) {
+	uint32_t i;
+	igt_debug("%s\n", message);
+	for (i = 0; i < size; i += 4) {
+		igt_debug("%08x %08x %08x %08x\n",
+				report[i],
+				report[i + 1],
+				report[i + 2],
+				report[i + 3]);
+	}
+}
+
+static struct oa_format
+get_oa_format(enum intel_xe_oa_format_name format)
+{
+	if (IS_DG2(devid))
+		return dg2_oa_formats[format];
+	else if (IS_METEORLAKE(devid))
+		return mtl_oa_formats[format];
+	else if (intel_graphics_ver(devid) >= IP_VER(20, 0))
+		return lnl_oa_formats[format];
+	else
+		return gen12_oa_formats[format];
+}
+
+static u64 oa_format_fields(u64 name)
+{
+#define FIELD_PREP_ULL(_mask, _val) \
+	(((_val) << (__builtin_ffsll(_mask) - 1)) & (_mask))
+
+	struct oa_format f = get_oa_format(name);
+
+	/* 0 format name is invalid */
+	if (!name)
+		memset(&f, 0xff, sizeof(f));
+
+	return FIELD_PREP_ULL(DRM_XE_OA_FORMAT_MASK_FMT_TYPE, (u64)f.oa_type) |
+		FIELD_PREP_ULL(DRM_XE_OA_FORMAT_MASK_COUNTER_SEL, (u64)f.counter_select) |
+		FIELD_PREP_ULL(DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE, (u64)f.counter_size) |
+		FIELD_PREP_ULL(DRM_XE_OA_FORMAT_MASK_BC_REPORT, (u64)f.bc_report);
+}
+#define __ff oa_format_fields
+
+static void
+__perf_close(int fd)
+{
+	close(fd);
+	stream_fd = -1;
+
+	if (pm_fd >= 0) {
+		close(pm_fd);
+		pm_fd = -1;
+	}
+}
+
+static int
+__perf_open(int fd, struct intel_xe_oa_open_prop *param, bool prevent_pm)
+{
+	int ret;
+	int32_t pm_value = 0;
+
+	if (stream_fd >= 0)
+		__perf_close(stream_fd);
+	if (pm_fd >= 0) {
+		close(pm_fd);
+		pm_fd = -1;
+	}
+
+	ret = intel_xe_perf_ioctl(fd, DRM_XE_PERF_OP_STREAM_OPEN, param);
+
+	igt_assert(ret >= 0);
+	errno = 0;
+
+	if (prevent_pm) {
+		pm_fd = open("/dev/cpu_dma_latency", O_RDWR);
+		igt_assert(pm_fd >= 0);
+
+		igt_assert_eq(write(pm_fd, &pm_value, sizeof(pm_value)), sizeof(pm_value));
+	}
+
+	return ret;
+}
+
+static uint64_t
+read_u64_file(const char *path)
+{
+	FILE *f;
+	uint64_t val;
+
+	f = fopen(path, "r");
+	igt_assert(f);
+
+	igt_assert_eq(fscanf(f, "%"PRIu64, &val), 1);
+
+	fclose(f);
+
+	return val;
+}
+
+static void
+write_u64_file(const char *path, uint64_t val)
+{
+	FILE *f;
+
+	f = fopen(path, "w");
+	igt_assert(f);
+
+	igt_assert(fprintf(f, "%"PRIu64, val) > 0);
+
+	fclose(f);
+}
+
+static uint32_t
+report_reason(const uint32_t *report)
+{
+	return ((report[0] >> OAREPORT_REASON_SHIFT) &
+		OAREPORT_REASON_MASK);
+}
+
+static uint64_t
+oa_timestamp(const uint32_t *report, enum intel_xe_oa_format_name format)
+{
+	struct oa_format fmt = get_oa_format(format);
+
+	return fmt.report_hdr_64bit ? *(uint64_t *)&report[2] : report[1];
+}
+
+static uint64_t
+timebase_scale(uint64_t delta)
+{
+	return (delta * NSEC_PER_SEC) / intel_xe_perf->devinfo.timestamp_frequency;
+}
+
+/* Returns: the largest OA exponent that will still result in a sampling period
+ * less than or equal to the given @period.
+ */
+static int
+max_oa_exponent_for_period_lte(uint64_t period)
+{
+	/* NB: timebase_scale() takes a uint64_t and an exponent of 30
+	 * would already represent a period of ~3 minutes so there's
+	 * really no need to consider higher exponents.
+	 */
+	for (int i = 0; i < 30; i++) {
+		uint64_t oa_period = timebase_scale(2 << i);
+
+		if (oa_period > period)
+			return max(0, i - 1);
+	}
+
+	igt_assert(!"reached");
+	return -1;
+}
+
+static bool
+oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
+{
+	if (report_reason(report) & OAREPORT_REASON_TIMER)
+		return true;
+
+	return false;
+}
+
+static bool
+init_sys_info(void)
+{
+	igt_assert_neq(devid, 0);
+
+	intel_xe_perf = intel_xe_perf_for_fd(drm_fd, 0);
+	igt_require(intel_xe_perf);
+
+	igt_debug("n_eu_slices: %"PRIu64"\n", intel_xe_perf->devinfo.n_eu_slices);
+	igt_debug("n_eu_sub_slices: %"PRIu64"\n", intel_xe_perf->devinfo.n_eu_sub_slices);
+	igt_debug("n_eus: %"PRIu64"\n", intel_xe_perf->devinfo.n_eus);
+	igt_debug("timestamp_frequency = %"PRIu64"\n",
+		  intel_xe_perf->devinfo.timestamp_frequency);
+	igt_assert_neq(intel_xe_perf->devinfo.timestamp_frequency, 0);
+
+	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
+
+	oa_exp_1_millisec = max_oa_exponent_for_period_lte(1000000);
+
+	return true;
+}
+
+static void
+read_2_oa_reports(int format_id,
+		  int exponent,
+		  uint32_t *oa_report0,
+		  uint32_t *oa_report1,
+		  bool timer_only)
+{
+	size_t format_size = get_oa_format(format_id).size;
+	uint32_t exponent_mask = (1 << (exponent + 1)) - 1;
+
+	/* Note: we allocate a large buffer so that each read() iteration
+	 * should scrape *all* pending records.
+	 *
+	 * The largest buffer the OA unit supports is 16MB.
+	 *
+	 * Being sure we are fetching all buffered reports allows us to
+	 * potentially throw away / skip all reports whenever we see
+	 * a _REPORT_LOST notification as a way of being sure are
+	 * measurements aren't skewed by a lost report.
+	 *
+	 * Note: that is is useful for some tests but also not something
+	 * applications would be expected to resort to. Lost reports are
+	 * somewhat unpredictable but typically don't pose a problem - except
+	 * to indicate that the OA unit may be over taxed if lots of reports
+	 * are being lost.
+	 */
+	int max_reports = MAX_OA_BUF_SIZE / format_size;
+	int buf_size = format_size * max_reports * 1.5;
+	uint8_t *buf = malloc(buf_size);
+	int n = 0;
+
+	for (int i = 0; i < 1000; i++) {
+		u32 oa_status = 0;
+		ssize_t len;
+
+		while ((len = read(stream_fd, buf, buf_size)) < 0 && errno == EINTR)
+			;
+		if (errno == EIO) {
+			oa_status = get_stream_status(stream_fd);
+			igt_debug("oa_status %#x\n", oa_status);
+			continue;
+		}
+
+		igt_assert(len > 0);
+		igt_debug("read %d bytes\n", (int)len);
+
+		/* Need at least 2 reports */
+		if (len < 2 * format_size)
+			continue;
+
+		for (size_t offset = 0; offset < len; offset += format_size) {
+			const uint32_t *report = (void *)(buf + offset);
+
+			/* Currently the only test that should ever expect to
+			 * see a _BUFFER_LOST error is the buffer_fill test,
+			 * otherwise something bad has probably happened...
+			 */
+			igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
+
+			/* At high sampling frequencies the OA HW might not be
+			 * able to cope with all write requests and will notify
+			 * us that a report was lost. We restart our read of
+			 * two sequential reports due to the timeline blip this
+			 * implies
+			 */
+			if (oa_status & DRM_XE_OASTATUS_REPORT_LOST) {
+				igt_debug("read restart: OA trigger collision / report lost\n");
+				n = 0;
+
+				/* XXX: break, because we don't know where
+				 * within the series of already read reports
+				 * there could be a blip from the lost report.
+				 */
+				break;
+			}
+
+			dump_report(report, format_size / 4, "oa-formats");
+
+			igt_debug("read report: reason = %x, timestamp = %"PRIx64", exponent mask=%x\n",
+				  report[0], oa_timestamp(report, format_id), exponent_mask);
+
+			/* Don't expect zero for timestamps */
+			igt_assert_neq_u64(oa_timestamp(report, format_id), 0);
+
+			if (timer_only) {
+				if (!oa_report_is_periodic(exponent, report)) {
+					igt_debug("skipping non timer report\n");
+					continue;
+				}
+			}
+
+			if (n++ == 0)
+				memcpy(oa_report0, report, format_size);
+			else {
+				memcpy(oa_report1, report, format_size);
+				free(buf);
+				return;
+			}
+		}
+	}
+
+	free(buf);
+
+	igt_assert(!"reached");
+}
+
+static unsigned read_xe_module_ref(void)
+{
+	FILE *fp = fopen("/proc/modules", "r");
+	char *line = NULL;
+	size_t line_buf_size = 0;
+	int len = 0;
+	unsigned ref_count;
+	char mod[8];
+	int modn = 3;
+
+	igt_assert(fp);
+
+	strcpy(mod, "xe ");
+	while ((len = getline(&line, &line_buf_size, fp)) > 0) {
+		if (strncmp(line, mod, modn) == 0) {
+			unsigned long mem;
+			int ret = sscanf(line + 5, "%lu %u", &mem, &ref_count);
+			igt_assert(ret == 2);
+			goto done;
+		}
+	}
+
+	igt_assert(!"reached");
+
+done:
+	free(line);
+	fclose(fp);
+	return ref_count;
+}
+
+/**
+ * SUBTEST: xe-ref-count
+ * Description: Check that an open oa stream holds a reference on the xe module
+ */
+static void
+test_xe_ref_count(void)
+{
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0 /* updated below */,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(0), /* update below */
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, 0, /* update below */
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	unsigned baseline, ref_count0, ref_count1;
+	uint32_t oa_report0[64];
+	uint32_t oa_report1[64];
+
+	/* This should be the first test before the first fixture so no drm_fd
+	 * should have been opened so far...
+	 */
+	igt_assert_eq(drm_fd, -1);
+
+	baseline = read_xe_module_ref();
+	igt_debug("baseline ref count (drm fd closed) = %u\n", baseline);
+
+	drm_fd = __drm_open_driver(DRIVER_XE);
+	if (is_xe_device(drm_fd))
+		xe_device_get(drm_fd);
+	devid = intel_get_drm_devid(drm_fd);
+	sysfs = igt_sysfs_open(drm_fd);
+
+	/* Note: these global variables are only initialized after calling
+	 * init_sys_info()...
+	 */
+	igt_require(init_sys_info());
+	properties[5] = default_test_set->perf_oa_metrics_set;
+	properties[7] = __ff(default_test_set->perf_oa_format);
+	properties[9] = oa_exp_1_millisec;
+
+	ref_count0 = read_xe_module_ref();
+	igt_debug("initial ref count with drm_fd open = %u\n", ref_count0);
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+        set_fd_flags(stream_fd, O_CLOEXEC);
+	ref_count1 = read_xe_module_ref();
+	igt_debug("ref count after opening oa stream = %u\n", ref_count1);
+
+	drm_close_driver(drm_fd);
+	close(sysfs);
+	drm_fd = -1;
+	sysfs = -1;
+	ref_count0 = read_xe_module_ref();
+	igt_debug("ref count after closing drm fd = %u\n", ref_count0);
+
+	read_2_oa_reports(default_test_set->perf_oa_format,
+			  oa_exp_1_millisec,
+			  oa_report0,
+			  oa_report1,
+			  false); /* not just timer reports */
+
+	__perf_close(stream_fd);
+	ref_count0 = read_xe_module_ref();
+	igt_debug("ref count after closing oa stream fd = %u\n", ref_count0);
+}
+
+/**
+ * SUBTEST: sysctl-defaults
+ * Description: Test that perf_stream_paranoid sysctl exists
+ */
+static void
+test_sysctl_defaults(void)
+{
+	int paranoid = read_u64_file("/proc/sys/dev/xe/perf_stream_paranoid");
+
+	igt_assert_eq(paranoid, 1);
+}
+
+igt_main
+{
+	igt_fixture {
+		struct stat sb;
+
+		/*
+		 * Prior tests may have unloaded the module or failed while
+		 * loading/unloading the module. Load xe here before we
+		 * stat the files.
+		 */
+		drm_load_module(DRIVER_XE);
+		srandom(time(NULL));
+		igt_require(!stat("/proc/sys/dev/xe/perf_stream_paranoid", &sb));
+	}
+
+	igt_subtest("xe-ref-count")
+		test_xe_ref_count();
+
+	igt_subtest("sysctl-defaults")
+		test_sysctl_defaults();
+
+	igt_fixture {
+		/* leave sysctl options in their default state... */
+		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
+
+		if (intel_xe_perf)
+			intel_xe_perf_free(intel_xe_perf);
+
+		drm_close_driver(drm_fd);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 122fbd07ca..c12cf4e211 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -300,6 +300,7 @@ intel_xe_progs = [
 	'xe_mmap',
 	'xe_module_load',
 	'xe_noexec_ping_pong',
+	'xe_oa',
 	'xe_pat',
 	'xe_peer2peer',
 	'xe_pm',
@@ -366,6 +367,7 @@ extra_dependencies = {
 	'perf': [ lib_igt_i915_perf ],
 	'perf_pmu':  [ lib_igt_perf ],
 	'sw_sync': [ libatomic ],
+	'xe_oa': [ lib_igt_xe_oa ],
 }
 
 test_executables = []
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* Re: [PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests
  2024-07-01  2:52 ` [PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests Ashutosh Dixit
@ 2024-07-01 16:53   ` Dixit, Ashutosh
  2024-07-01 19:47   ` Umesh Nerlige Ramappa
  1 sibling, 0 replies; 26+ messages in thread
From: Dixit, Ashutosh @ 2024-07-01 16:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Umesh Nerlige Ramappa

On Sun, 30 Jun 2024 19:52:57 -0700, Ashutosh Dixit wrote:
>
> Add "xe-ref-count" and "sysctl-defaults" subtests.
>
> v2: Set INTEL_XE_DEVICE_MAX_SUBSLICES to 64 (value on PVC)
>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
>  lib/xe/xe_oa.h      |   2 +-
>  tests/intel/xe_oa.c | 805 ++++++++++++++++++++++++++++++++++++++++++++
>  tests/meson.build   |   2 +
>  3 files changed, 808 insertions(+), 1 deletion(-)
>  create mode 100644 tests/intel/xe_oa.c
>
> diff --git a/lib/xe/xe_oa.h b/lib/xe/xe_oa.h
> index f6f2768b00..27ebb4b217 100644
> --- a/lib/xe/xe_oa.h
> +++ b/lib/xe/xe_oa.h
> @@ -19,7 +19,7 @@ extern "C" {
>  #define _DIV_ROUND_UP(a, b)  (((a) + (b) - 1) / (b))
>
>  #define INTEL_XE_DEVICE_MAX_SLICES           (8)
> -#define INTEL_XE_DEVICE_MAX_SUBSLICES        (32)
> +#define INTEL_XE_DEVICE_MAX_SUBSLICES        (64) /* Maximum on XE_PVC */

I will move this line to the previous patch: "lib/xe/oa: Add PVC support",
it should be there.

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests
  2024-07-01  2:52 ` [PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests Ashutosh Dixit
  2024-07-01 16:53   ` Dixit, Ashutosh
@ 2024-07-01 19:47   ` Umesh Nerlige Ramappa
  2024-07-01 22:31     ` Dixit, Ashutosh
  1 sibling, 1 reply; 26+ messages in thread
From: Umesh Nerlige Ramappa @ 2024-07-01 19:47 UTC (permalink / raw)
  To: Ashutosh Dixit; +Cc: igt-dev

On Sun, Jun 30, 2024 at 07:52:57PM -0700, Ashutosh Dixit wrote:
>Add "xe-ref-count" and "sysctl-defaults" subtests.
>
>v2: Set INTEL_XE_DEVICE_MAX_SUBSLICES to 64 (value on PVC)
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>---
> lib/xe/xe_oa.h      |   2 +-
> tests/intel/xe_oa.c | 805 ++++++++++++++++++++++++++++++++++++++++++++
> tests/meson.build   |   2 +
> 3 files changed, 808 insertions(+), 1 deletion(-)
> create mode 100644 tests/intel/xe_oa.c
>
>diff --git a/lib/xe/xe_oa.h b/lib/xe/xe_oa.h
>index f6f2768b00..27ebb4b217 100644
>--- a/lib/xe/xe_oa.h
>+++ b/lib/xe/xe_oa.h
>@@ -19,7 +19,7 @@ extern "C" {
> #define _DIV_ROUND_UP(a, b)  (((a) + (b) - 1) / (b))
>
> #define INTEL_XE_DEVICE_MAX_SLICES           (8)
>-#define INTEL_XE_DEVICE_MAX_SUBSLICES        (32)
>+#define INTEL_XE_DEVICE_MAX_SUBSLICES        (64) /* Maximum on XE_PVC */
> #define INTEL_XE_DEVICE_MAX_EUS_PER_SUBSLICE (16) /* Maximum on gfx12 */
>
> enum intel_xe_oa_format_name {
>diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>new file mode 100644
>index 0000000000..2b5044b116
>--- /dev/null
>+++ b/tests/intel/xe_oa.c
>@@ -0,0 +1,805 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2024 Intel Corporation
>+ */
>+
>+#include <stdlib.h>
>+#include <stdio.h>
>+#include <string.h>
>+#include <fcntl.h>
>+#include <inttypes.h>
>+#include <errno.h>
>+#include <signal.h>
>+#include <sys/stat.h>
>+#include <sys/time.h>
>+#include <sys/times.h>
>+#include <sys/types.h>
>+#include <dirent.h>
>+#include <time.h>
>+#include <poll.h>
>+#include <math.h>
>+
>+#include "drm.h"
>+#include "igt.h"
>+#include "igt_device.h"
>+#include "igt_sysfs.h"
>+#include "xe/xe_ioctl.h"
>+#include "xe/xe_query.h"
>+#include "xe/xe_oa.h"
>+
>+/**
>+ * TEST: perf
>+ * Description: Test the Xe OA metrics streaming interface
>+ * Category: Core
>+ * Mega feature: Performance interface
>+ * Sub-category: Performance tests
>+ * Functionality: oa
>+ * Feature: xe streaming interface, oa
>+ * Test category: Perf
>+ */
>+
>+#define OA_MI_REPORT_PERF_COUNT		((0x28 << 23) | (4 - 2))
>+
>+#define OAREPORT_REASON_MASK           0x3f
>+#define OAREPORT_REASON_SHIFT          19
>+#define OAREPORT_REASON_TIMER          (1<<0)
>+#define OAREPORT_REASON_INTERNAL       (3<<1)
>+#define OAREPORT_REASON_CTX_SWITCH     (1<<3)
>+#define OAREPORT_REASON_GO             (1<<4)
>+#define OAREPORT_REASON_CLK_RATIO      (1<<5)
>+
>+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET	(1 << 19)
>+#define PIPE_CONTROL_SYNC_GFDT	  (1 << 17)
>+#define PIPE_CONTROL_NO_WRITE	   (0 << 14)
>+#define PIPE_CONTROL_WRITE_IMMEDIATE    (1 << 14)
>+#define PIPE_CONTROL_WRITE_DEPTH_COUNT  (2 << 14)
>+#define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
>+#define PIPE_CONTROL_INSTRUCTION_INVALIDATE (1 << 11)
>+#define PIPE_CONTROL_ISP_DIS	    (1 << 9)
>+#define PIPE_CONTROL_INTERRUPT_ENABLE   (1 << 8)
>+/* GT */
>+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE      (1 << 5)
>+#define PIPE_CONTROL_PPGTT_WRITE	(0 << 2)
>+#define PIPE_CONTROL_GLOBAL_GTT_WRITE   (1 << 2)
>+
>+#define MAX_OA_BUF_SIZE (16 * 1024 * 1024)
>+#define OA_BUFFER_SIZE MAX_OA_BUF_SIZE
>+
>+#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK 0x03fffffc
>+/*
>+ * Engine specific registers defined as offsets from engine->mmio_base. For
>+ * these registers, OR bit[0] with 1 so we can add the mmio_base when running
>+ * engine specific test.
>+ */
>+#define MMIO_BASE_OFFSET 0x1
>+
>+#define OAG_OASTATUS (0xdafc)
>+#define OAG_PERF_COUNTER_B(idx) (0xDA94 + 4 * (idx))
>+#define OAG_OATAILPTR (0xdb04)
>+#define OAG_OATAILPTR_MASK 0xffffffc0
>+#define OAG_OABUFFER (0xdb08)
>+
>+#define XE_OA_MAX_SET_PROPERTIES 16
>+
>+#define ADD_PROPS(_head, _tail, _key, _value)	\
>+	do { \
>+		igt_assert((_tail - _head) < (XE_OA_MAX_SET_PROPERTIES * 2)); \
>+		*_tail++ = DRM_XE_OA_PROPERTY_##_key; \
>+		*_tail++ = _value; \
>+	} while (0)
>+
>+struct accumulator {
>+#define MAX_RAW_OA_COUNTERS 62
>+	enum intel_xe_oa_format_name format;
>+
>+	uint64_t deltas[MAX_RAW_OA_COUNTERS];
>+};
>+
>+/* OA unit types */
>+enum {
>+	OAG,
>+	OAR,
>+	OAM,
>+
>+	MAX_OA_TYPE,
>+};
>+
>+struct oa_format {
>+	const char *name;
>+	size_t size;
>+	int a40_high_off; /* bytes */
>+	int a40_low_off;
>+	int n_a40;
>+	int a64_off;
>+	int n_a64;
>+	int a_off;
>+	int n_a;
>+	int first_a;
>+	int first_a40;
>+	int b_off;
>+	int n_b;
>+	int c_off;
>+	int n_c;
>+	int oa_type; /* of enum intel_xe_oa_format_name */
>+	bool report_hdr_64bit;
>+	int counter_select;
>+	int counter_size;
>+	int bc_report;
>+};
>+
>+static struct oa_format gen12_oa_formats[XE_OA_FORMAT_MAX] = {
>+	[XE_OA_FORMAT_A32u40_A4u32_B8_C8] = {
>+		"A32u40_A4u32_B8_C8", .size = 256,
>+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
>+		.a_off = 144, .n_a = 4, .first_a = 32,
>+		.b_off = 192, .n_b = 8,
>+		.c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAG,
>+		.counter_select = 5,
>+	},
>+};
>+
>+static struct oa_format dg2_oa_formats[XE_OA_FORMAT_MAX] = {
>+	[XE_OAR_FORMAT_A32u40_A4u32_B8_C8] = {
>+		"A32u40_A4u32_B8_C8", .size = 256,
>+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
>+		.a_off = 144, .n_a = 4, .first_a = 32,
>+		.b_off = 192, .n_b = 8,
>+		.c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAR,
>+		.counter_select = 5,
>+	},
>+	/* This format has A36 and A37 interleaved with high bytes of some A
>+	 * counters, so we will accumulate only subset of counters.
>+	 */
>+	[XE_OA_FORMAT_A24u40_A14u32_B8_C8] = {
>+		"A24u40_A14u32_B8_C8", .size = 256,
>+		/* u40: A4 - A23 */
>+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 20, .first_a40 = 4,
>+		/* u32: A0 - A3 */
>+		.a_off = 16, .n_a = 4,
>+		.b_off = 192, .n_b = 8,
>+		.c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAG,
>+		.counter_select = 5,
>+	},
>+	/* This format has 24 u64 counters ranging from A0 - A35. Until we come
>+	 * up with a better mechanism to define missing counters, we will use a
>+	 * subset of counters that are indexed by one-increments - A28 - A35.
>+	 */
>+	[XE_OAC_FORMAT_A24u64_B8_C8] = {
>+		"OAC_A24u64_B8_C8", .size = 320,
>+		.a64_off = 160, .n_a64 = 8,
>+		.b_off = 224, .n_b = 8,
>+		.c_off = 256, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 1, },
>+};
>+
>+static struct oa_format mtl_oa_formats[XE_OA_FORMAT_MAX] = {
>+	[XE_OAR_FORMAT_A32u40_A4u32_B8_C8] = {
>+		"A32u40_A4u32_B8_C8", .size = 256,
>+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
>+		.a_off = 144, .n_a = 4, .first_a = 32,
>+		.b_off = 192, .n_b = 8,
>+		.c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAR,
>+		.counter_select = 5,
>+	},
>+	/* This format has A36 and A37 interleaved with high bytes of some A
>+	 * counters, so we will accumulate only subset of counters.
>+	 */
>+	[XE_OA_FORMAT_A24u40_A14u32_B8_C8] = {
>+		"A24u40_A14u32_B8_C8", .size = 256,
>+		/* u40: A4 - A23 */
>+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 20, .first_a40 = 4,
>+		/* u32: A0 - A3 */
>+		.a_off = 16, .n_a = 4,
>+		.b_off = 192, .n_b = 8,
>+		.c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAG,
>+		.counter_select = 5,
>+	},
>+
>+	/* Treat MPEC countes as A counters for now */
>+	[XE_OAM_FORMAT_MPEC8u64_B8_C8] = {
>+		"MPEC8u64_B8_C8", .size = 192,
>+		.a64_off = 32, .n_a64 = 8,
>+		.b_off = 96, .n_b = 8,
>+		.c_off = 128, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAM_MPEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 1,
>+	},
>+	[XE_OAM_FORMAT_MPEC8u32_B8_C8] = {
>+		"MPEC8u32_B8_C8", .size = 128,
>+		.a_off = 32, .n_a = 8,
>+		.b_off = 64, .n_b = 8,
>+		.c_off = 96, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAM_MPEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 2,
>+	},
>+	/* This format has 24 u64 counters ranging from A0 - A35. Until we come
>+	 * up with a better mechanism to define missing counters, we will use a
>+	 * subset of counters that are indexed by one-increments - A28 - A35.
>+	 */
>+	[XE_OAC_FORMAT_A24u64_B8_C8] = {
>+		"OAC_A24u64_B8_C8", .size = 320,
>+		.a64_off = 160, .n_a64 = 8,
>+		.b_off = 224, .n_b = 8,
>+		.c_off = 256, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 1, },
>+};
>+
>+static struct oa_format lnl_oa_formats[XE_OA_FORMAT_MAX] = {
>+	[XE_OA_FORMAT_PEC64u64] = {
>+		"PEC64u64", .size = 576,
>+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 1,
>+		.counter_size = 1,
>+		.bc_report = 0 },
>+	[XE_OA_FORMAT_PEC64u64_B8_C8] = {
>+		"PEC64u64_B8_C8", .size = 640,
>+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 1,
>+		.counter_size = 1,
>+		.bc_report = 1 },
>+	[XE_OA_FORMAT_PEC64u32] = {
>+		"PEC64u32", .size = 320,
>+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 1,
>+		.counter_size = 0,
>+		.bc_report = 0 },
>+	[XE_OA_FORMAT_PEC32u64_G1] = {
>+		"PEC32u64_G1", .size = 320,
>+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 5,
>+		.counter_size = 1,
>+		.bc_report = 0 },
>+	[XE_OA_FORMAT_PEC32u32_G1] = {
>+		"PEC32u32_G1", .size = 192,
>+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 5,
>+		.counter_size = 0,
>+		.bc_report = 0 },
>+	[XE_OA_FORMAT_PEC32u64_G2] = {
>+		"PEC32u64_G2", .size = 320,
>+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 6,
>+		.counter_size = 1,
>+		.bc_report = 0 },
>+	[XE_OA_FORMAT_PEC32u32_G2] = {
>+		"PEC32u64_G2", .size = 192,
>+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 6,
>+		.counter_size = 0,
>+		.bc_report = 0 },
>+	[XE_OA_FORMAT_PEC36u64_G1_32_G2_4] = {
>+		"PEC36u64_G1_32_G2_4", .size = 320,
>+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 3,
>+		.counter_size = 1,
>+		.bc_report = 0 },
>+	[XE_OA_FORMAT_PEC36u64_G1_4_G2_32] = {
>+		"PEC36u64_G1_4_G2_32_G2", .size = 320,
>+		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+		.report_hdr_64bit = true,
>+		.counter_select = 4,
>+		.counter_size = 1,
>+		.bc_report = 0 },
>+};

I think we should do away with the per platform arrays and instead do 
something similar to what the KMD does - have a platform mask or 
something because really the same format does not have a new definition 
for another platform. It should just indicate what platforms the format 
is supported on. Maybe please create an issue to track this and we can 
look at it later sometime.

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh


^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests
  2024-07-01 19:47   ` Umesh Nerlige Ramappa
@ 2024-07-01 22:31     ` Dixit, Ashutosh
  0 siblings, 0 replies; 26+ messages in thread
From: Dixit, Ashutosh @ 2024-07-01 22:31 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: igt-dev

On Mon, 01 Jul 2024 12:47:45 -0700, Umesh Nerlige Ramappa wrote:
>
> > +	[XE_OA_FORMAT_PEC36u64_G1_4_G2_32] = {
> > +		"PEC36u64_G1_4_G2_32_G2", .size = 320,
> > +		.oa_type = DRM_XE_OA_FMT_TYPE_PEC,
> > +		.report_hdr_64bit = true,
> > +		.counter_select = 4,
> > +		.counter_size = 1,
> > +		.bc_report = 0 },
> > +};
>
> I think we should do away with the per platform arrays and instead do
> something similar to what the KMD does - have a platform mask or something
> because really the same format does not have a new definition for another
> platform. It should just indicate what platforms the format is supported
> on. Maybe please create an issue to track this and we can look at it later
> sometime.

Thanks Umesh, yup it's a good idea. I have created an issue about this.

>
> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Thanks.
--
Ashutosh

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 03/14] tests/intel/xe_oa: Add some negative tests
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
  2024-07-01  2:52 ` [PATCH i-g-t 01/14] lib/xe/oa: Add PVC support Ashutosh Dixit
  2024-07-01  2:52 ` [PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests Ashutosh Dixit
@ 2024-07-01  2:52 ` Ashutosh Dixit
  2024-07-01  2:52 ` [PATCH i-g-t 04/14] tests/intel/xe_oa: Add "oa-formats" subtest Ashutosh Dixit
                   ` (14 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:52 UTC (permalink / raw)
  To: igt-dev

Add:
	"non-system-wide-paranoid"
	"invalid-oa-metric-set-id"
	"invalid-oa-format-id"
	"missing-sample-flags"

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 192 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 192 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 2b5044b116..9a59350b16 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -303,6 +303,7 @@ struct drm_xe_engine_class_instance default_hwe;
 static struct intel_xe_perf *intel_xe_perf;
 static uint64_t oa_exp_1_millisec;
 struct intel_mmio_data mmio_data;
+static igt_render_copyfunc_t render_copy;
 
 static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
 {
@@ -550,6 +551,166 @@ init_sys_info(void)
 	return true;
 }
 
+/**
+ * SUBTEST: non-system-wide-paranoid
+ * Description: CAP_SYS_ADMIN is required to open system wide metrics, unless
+ *		sysctl parameter dev.xe.perf_stream_paranoid == 0
+ */
+static void test_system_wide_paranoid(void)
+{
+	igt_fork(child, 1) {
+		uint64_t properties[] = {
+			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+			/* Include OA reports in samples */
+			DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+			/* OA unit configuration */
+			DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		};
+		struct intel_xe_oa_open_prop param = {
+			.num_properties = ARRAY_SIZE(properties) / 2,
+			.properties_ptr = to_user_pointer(properties),
+		};
+
+		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
+
+		igt_drop_root();
+
+		intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param, EACCES);
+	}
+
+	igt_waitchildren();
+
+	igt_fork(child, 1) {
+		uint64_t properties[] = {
+			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+			/* Include OA reports in samples */
+			DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+			/* OA unit configuration */
+			DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		};
+		struct intel_xe_oa_open_prop param = {
+			.num_properties = ARRAY_SIZE(properties) / 2,
+			.properties_ptr = to_user_pointer(properties),
+		};
+		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 0);
+
+		igt_drop_root();
+
+		stream_fd = __perf_open(drm_fd, &param, false);
+		__perf_close(stream_fd);
+	}
+
+	igt_waitchildren();
+
+	/* leave in paranoid state */
+	write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
+}
+
+/**
+ * SUBTEST: invalid-oa-metric-set-id
+ * Description: Test behavior for invalid metric set id's
+ */
+static void test_invalid_oa_metric_set_id(void)
+{
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, UINT64_MAX,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+
+	intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param, EINVAL);
+
+	properties[ARRAY_SIZE(properties) - 1] = 0; /* ID 0 is also be reserved as invalid */
+	intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param, EINVAL);
+
+	/* Check that we aren't just seeing false positives... */
+	properties[ARRAY_SIZE(properties) - 1] = default_test_set->perf_oa_metrics_set;
+	stream_fd = __perf_open(drm_fd, &param, false);
+	__perf_close(stream_fd);
+
+	/* There's no valid default OA metric set ID... */
+	param.num_properties--;
+	intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param, EINVAL);
+}
+
+/**
+ * SUBTEST: invalid-oa-format-id
+ * Description: Test behavior for invalid OA format fields
+ */
+static void test_invalid_oa_format_id(void)
+{
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, UINT64_MAX, /* No __ff() here */
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+
+	intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param, EINVAL);
+
+	properties[ARRAY_SIZE(properties) - 1] = __ff(0); /* ID 0 is also be reserved as invalid */
+	intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param, EINVAL);
+
+	/* Check that we aren't just seeing false positives... */
+	properties[ARRAY_SIZE(properties) - 1] = __ff(default_test_set->perf_oa_format);
+	stream_fd = __perf_open(drm_fd, &param, false);
+	__perf_close(stream_fd);
+	/* There's no valid default OA format... */
+	param.num_properties--;
+	intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param, EINVAL);
+}
+
+/**
+ * SUBTEST: missing-sample-flags
+ * Description: Test behavior for no SAMPLE_OA and no EXEC_QUEUE_ID
+ */
+static void test_missing_sample_flags(void)
+{
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* No _PROP_SAMPLE_xyz flags */
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+
+	intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param, EINVAL);
+}
+
 static void
 read_2_oa_reports(int format_id,
 		  int exponent,
@@ -793,6 +954,37 @@ igt_main
 	igt_subtest("sysctl-defaults")
 		test_sysctl_defaults();
 
+	igt_fixture {
+		/* We expect that the ref count test before these fixtures
+		 * should have closed drm_fd...
+		 */
+		igt_assert_eq(drm_fd, -1);
+
+		drm_fd = drm_open_driver(DRIVER_XE);
+		xe_device_get(drm_fd);
+
+		devid = intel_get_drm_devid(drm_fd);
+		sysfs = igt_sysfs_open(drm_fd);
+
+		igt_require(init_sys_info());
+
+		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
+
+		render_copy = igt_get_render_copyfunc(devid);
+	}
+
+	igt_subtest("non-system-wide-paranoid")
+		test_system_wide_paranoid();
+
+	igt_subtest("invalid-oa-metric-set-id")
+		test_invalid_oa_metric_set_id();
+
+	igt_subtest("invalid-oa-format-id")
+		test_invalid_oa_format_id();
+
+	igt_subtest("missing-sample-flags")
+		test_missing_sample_flags();
+
 	igt_fixture {
 		/* leave sysctl options in their default state... */
 		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 04/14] tests/intel/xe_oa: Add "oa-formats" subtest
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (2 preceding siblings ...)
  2024-07-01  2:52 ` [PATCH i-g-t 03/14] tests/intel/xe_oa: Add some negative tests Ashutosh Dixit
@ 2024-07-01  2:52 ` Ashutosh Dixit
  2024-07-01  2:53 ` [PATCH i-g-t 05/14] tests/intel/xe_oa: Add oa exponent tests Ashutosh Dixit
                   ` (13 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:52 UTC (permalink / raw)
  To: igt-dev

Add "oa-formats" subtest.

v2: Remove undefined_a_counters (Umesh)

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 465 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 465 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 9a59350b16..1d8c6eb599 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -478,6 +478,57 @@ write_u64_file(const char *path, uint64_t val)
 	fclose(f);
 }
 
+static uint64_t
+read_report_ticks(const uint32_t *report, enum intel_xe_oa_format_name format)
+{
+
+	struct oa_format fmt = get_oa_format(format);
+
+	return fmt.report_hdr_64bit ? *(uint64_t *)&report[6] : report[3];
+}
+
+/*
+ * t0 is a value sampled before t1. width is number of bits used to represent
+ * t0/t1. Normally t1 is greater than t0. In cases where t1 < t0 use this
+ * helper. Since the size of t1/t0 is already 64 bits, no special handling is
+ * needed for width = 64.
+ */
+static uint64_t
+elapsed_delta(uint64_t t1, uint64_t t0, uint32_t width)
+{
+	uint32_t max_bits = sizeof(t1) * 8;
+
+	igt_assert(width <= max_bits);
+
+	if (t1 < t0 && width != max_bits)
+		return ((1ULL << width) - t0) + t1;
+
+	return t1 - t0;
+}
+
+static uint64_t
+oa_tick_delta(const uint32_t *report1,
+	      const uint32_t *report0,
+	      enum intel_xe_oa_format_name format)
+{
+	return elapsed_delta(read_report_ticks(report1, format),
+			     read_report_ticks(report0, format), 32);
+}
+
+static void
+read_report_clock_ratios(const uint32_t *report,
+			      uint32_t *slice_freq_mhz,
+			      uint32_t *unslice_freq_mhz)
+{
+	uint32_t unslice_freq = report[0] & 0x1ff;
+	uint32_t slice_freq_low = (report[0] >> 25) & 0x7f;
+	uint32_t slice_freq_high = (report[0] >> 9) & 0x3;
+	uint32_t slice_freq = slice_freq_low | (slice_freq_high << 7);
+
+	*slice_freq_mhz = (slice_freq * 16666) / 1000;
+	*unslice_freq_mhz = (unslice_freq * 16666) / 1000;
+}
+
 static uint32_t
 report_reason(const uint32_t *report)
 {
@@ -485,6 +536,27 @@ report_reason(const uint32_t *report)
 		OAREPORT_REASON_MASK);
 }
 
+static const char *
+read_report_reason(const uint32_t *report)
+{
+	uint32_t reason = report_reason(report);
+
+	if (reason & (1<<0))
+		return "timer";
+	else if (reason & (1<<1))
+	      return "internal trigger 1";
+	else if (reason & (1<<2))
+	      return "internal trigger 2";
+	else if (reason & (1<<3))
+	      return "context switch";
+	else if (reason & (1<<4))
+	      return "GO 1->0 transition (enter RC6)";
+	else if (reason & (1<<5))
+		return "[un]slice clock ratio change";
+	else
+		return "unknown";
+}
+
 static uint64_t
 oa_timestamp(const uint32_t *report, enum intel_xe_oa_format_name format)
 {
@@ -493,6 +565,17 @@ oa_timestamp(const uint32_t *report, enum intel_xe_oa_format_name format)
 	return fmt.report_hdr_64bit ? *(uint64_t *)&report[2] : report[1];
 }
 
+static uint64_t
+oa_timestamp_delta(const uint32_t *report1,
+		   const uint32_t *report0,
+		   enum intel_xe_oa_format_name format)
+{
+	uint32_t width = intel_graphics_ver(devid) >= IP_VER(12, 55) ? 56 : 32;
+
+	return elapsed_delta(oa_timestamp(report1, format),
+			     oa_timestamp(report0, format), width);
+}
+
 static uint64_t
 timebase_scale(uint64_t delta)
 {
@@ -529,6 +612,182 @@ oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
 	return false;
 }
 
+static uint64_t
+read_40bit_a_counter(const uint32_t *report,
+			  enum intel_xe_oa_format_name fmt, int a_id)
+{
+	struct oa_format format = get_oa_format(fmt);
+	uint8_t *a40_high = (((uint8_t *)report) + format.a40_high_off);
+	uint32_t *a40_low = (uint32_t *)(((uint8_t *)report) +
+					 format.a40_low_off);
+	uint64_t high = (uint64_t)(a40_high[a_id]) << 32;
+
+	return a40_low[a_id] | high;
+}
+
+static uint64_t
+xehpsdv_read_64bit_a_counter(const uint32_t *report, enum intel_xe_oa_format_name fmt, int a_id)
+{
+	struct oa_format format = get_oa_format(fmt);
+	uint64_t *a64 = (uint64_t *)(((uint8_t *)report) + format.a64_off);
+
+	return a64[a_id];
+}
+
+static uint64_t
+get_40bit_a_delta(uint64_t value0, uint64_t value1)
+{
+	if (value0 > value1)
+		return (1ULL << 40) + value1 - value0;
+	else
+		return value1 - value0;
+}
+
+static void
+accumulate_uint64(int a_index,
+		  const uint32_t *report0,
+		  const uint32_t *report1,
+		  enum intel_xe_oa_format_name format,
+		  uint64_t *delta)
+{
+	uint64_t value0 = xehpsdv_read_64bit_a_counter(report0, format, a_index),
+		 value1 = xehpsdv_read_64bit_a_counter(report1, format, a_index);
+
+	*delta += (value1 - value0);
+}
+
+/* The TestOa metric set is designed so */
+static void
+sanity_check_reports(const uint32_t *oa_report0, const uint32_t *oa_report1,
+		     enum intel_xe_oa_format_name fmt)
+{
+	struct oa_format format = get_oa_format(fmt);
+	uint64_t time_delta = timebase_scale(oa_timestamp_delta(oa_report1,
+								oa_report0,
+								fmt));
+	uint64_t clock_delta = oa_tick_delta(oa_report1, oa_report0, fmt);
+	uint64_t max_delta;
+	uint64_t freq;
+	uint32_t *rpt0_b = (uint32_t *)(((uint8_t *)oa_report0) +
+					format.b_off);
+	uint32_t *rpt1_b = (uint32_t *)(((uint8_t *)oa_report1) +
+					format.b_off);
+	uint32_t b;
+	uint32_t ref;
+
+	igt_debug("report type: %s->%s\n",
+		  read_report_reason(oa_report0),
+		  read_report_reason(oa_report1));
+
+	freq = time_delta ? (clock_delta * 1000) / time_delta : 0;
+	igt_debug("freq = %"PRIu64"\n", freq);
+
+	igt_debug("clock delta = %"PRIu64"\n", clock_delta);
+
+	max_delta = clock_delta * intel_xe_perf->devinfo.n_eus;
+
+	/* Gen8+ has some 40bit A counters... */
+	for (int j = format.first_a40; j < format.n_a40 + format.first_a40; j++) {
+		uint64_t value0 = read_40bit_a_counter(oa_report0, fmt, j);
+		uint64_t value1 = read_40bit_a_counter(oa_report1, fmt, j);
+		uint64_t delta = get_40bit_a_delta(value0, value1);
+
+		igt_debug("A40_%d: delta = %"PRIu64"\n", j, delta);
+		igt_assert_f(delta <= max_delta,
+			     "A40_%d: delta = %"PRIu64", max_delta = %"PRIu64"\n",
+			     j, delta, max_delta);
+	}
+
+	for (int j = 0; j < format.n_a64; j++) {
+		uint64_t delta = 0;
+
+		accumulate_uint64(j, oa_report0, oa_report1, fmt, &delta);
+
+		igt_debug("A64_%d: delta = %"PRIu64"\n", format.first_a + j, delta);
+		igt_assert_f(delta <= max_delta,
+			     "A64_%d: delta = %"PRIu64", max_delta = %"PRIu64"\n",
+			     format.first_a + j, delta, max_delta);
+	}
+
+	for (int j = 0; j < format.n_a; j++) {
+		uint32_t *a0 = (uint32_t *)(((uint8_t *)oa_report0) +
+					    format.a_off);
+		uint32_t *a1 = (uint32_t *)(((uint8_t *)oa_report1) +
+					    format.a_off);
+		int a_id = format.first_a + j;
+		uint32_t delta = a1[j] - a0[j];
+
+		igt_debug("A%d: delta = %"PRIu32"\n", a_id, delta);
+		igt_assert_f(delta <= max_delta,
+			     "A%d: delta = %"PRIu32", max_delta = %"PRIu64"\n",
+			     a_id, delta, max_delta);
+	}
+
+	/* The TestOa metric set defines all B counters to be a
+	 * multiple of the gpu clock
+	 */
+	if (format.n_b && (format.oa_type == DRM_XE_OA_FMT_TYPE_OAG || format.oa_type == DRM_XE_OA_FMT_TYPE_OAR)) {
+		if (clock_delta > 0) {
+			b = rpt1_b[0] - rpt0_b[0];
+			igt_debug("B0: delta = %"PRIu32"\n", b);
+			igt_assert_eq(b, 0);
+
+			b = rpt1_b[1] - rpt0_b[1];
+			igt_debug("B1: delta = %"PRIu32"\n", b);
+			igt_assert_eq(b, clock_delta);
+
+			b = rpt1_b[2] - rpt0_b[2];
+			igt_debug("B2: delta = %"PRIu32"\n", b);
+			igt_assert_eq(b, clock_delta);
+
+			b = rpt1_b[3] - rpt0_b[3];
+			ref = clock_delta / 2;
+			igt_debug("B3: delta = %"PRIu32"\n", b);
+			igt_assert(b >= ref - 1 && b <= ref + 1);
+
+			b = rpt1_b[4] - rpt0_b[4];
+			ref = clock_delta / 3;
+			igt_debug("B4: delta = %"PRIu32"\n", b);
+			igt_assert(b >= ref - 1 && b <= ref + 1);
+
+			b = rpt1_b[5] - rpt0_b[5];
+			ref = clock_delta / 3;
+			igt_debug("B5: delta = %"PRIu32"\n", b);
+			igt_assert(b >= ref - 1 && b <= ref + 1);
+
+			b = rpt1_b[6] - rpt0_b[6];
+			ref = clock_delta / 6;
+			igt_debug("B6: delta = %"PRIu32"\n", b);
+			igt_assert(b >= ref - 1 && b <= ref + 1);
+
+			b = rpt1_b[7] - rpt0_b[7];
+			ref = clock_delta * 2 / 3;
+			igt_debug("B7: delta = %"PRIu32"\n", b);
+			igt_assert(b >= ref - 1 && b <= ref + 1);
+		} else {
+			for (int j = 0; j < format.n_b; j++) {
+				b = rpt1_b[j] - rpt0_b[j];
+				igt_debug("B%i: delta = %"PRIu32"\n", j, b);
+				igt_assert_eq(b, 0);
+			}
+		}
+	}
+
+	for (int j = 0; j < format.n_c; j++) {
+		uint32_t *c0 = (uint32_t *)(((uint8_t *)oa_report0) +
+					    format.c_off);
+		uint32_t *c1 = (uint32_t *)(((uint8_t *)oa_report1) +
+					    format.c_off);
+		uint32_t delta = c1[j] - c0[j];
+
+		igt_debug("C%d: delta = %"PRIu32", max_delta=%"PRIu64"\n",
+			  j, delta, max_delta);
+		igt_assert_f(delta <= max_delta,
+			     "C%d: delta = %"PRIu32", max_delta = %"PRIu64"\n",
+			     j, delta, max_delta);
+	}
+}
+
 static bool
 init_sys_info(void)
 {
@@ -817,6 +1076,191 @@ read_2_oa_reports(int format_id,
 	igt_assert(!"reached");
 }
 
+static void
+open_and_read_2_oa_reports(int format_id,
+			   int exponent,
+			   uint32_t *oa_report0,
+			   uint32_t *oa_report1,
+			   bool timer_only,
+			   const struct drm_xe_engine_class_instance *hwe)
+{
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(format_id),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, exponent,
+		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+	set_fd_flags(stream_fd, O_CLOEXEC);
+
+	read_2_oa_reports(format_id, exponent,
+			  oa_report0, oa_report1, timer_only);
+
+	__perf_close(stream_fd);
+}
+
+static void
+print_reports(uint32_t *oa_report0, uint32_t *oa_report1, int fmt)
+{
+	struct oa_format format = get_oa_format(fmt);
+	uint64_t ts0 = oa_timestamp(oa_report0, fmt);
+	uint64_t ts1 = oa_timestamp(oa_report1, fmt);
+
+	igt_debug("TIMESTAMP: 1st = %"PRIu64", 2nd = %"PRIu64", delta = %"PRIu64"\n",
+		  ts0, ts1, ts1 - ts0);
+
+	{
+		uint64_t clock0 = read_report_ticks(oa_report0, fmt);
+		uint64_t clock1 = read_report_ticks(oa_report1, fmt);
+
+		igt_debug("CLOCK: 1st = %"PRIu64", 2nd = %"PRIu64", delta = %"PRIu64"\n",
+			  clock0, clock1, clock1 - clock0);
+	}
+
+	{
+		uint32_t slice_freq0, slice_freq1, unslice_freq0, unslice_freq1;
+		const char *reason0 = read_report_reason(oa_report0);
+		const char *reason1 = read_report_reason(oa_report1);
+
+		igt_debug("CTX ID: 1st = %"PRIu32", 2nd = %"PRIu32"\n",
+			  oa_report0[2], oa_report1[2]);
+
+		read_report_clock_ratios(oa_report0,
+					 &slice_freq0, &unslice_freq0);
+		read_report_clock_ratios(oa_report1,
+					 &slice_freq1, &unslice_freq1);
+
+		igt_debug("SLICE CLK: 1st = %umhz, 2nd = %umhz, delta = %d\n",
+			  slice_freq0, slice_freq1,
+			  ((int)slice_freq1 - (int)slice_freq0));
+		igt_debug("UNSLICE CLK: 1st = %umhz, 2nd = %umhz, delta = %d\n",
+			  unslice_freq0, unslice_freq1,
+			  ((int)unslice_freq1 - (int)unslice_freq0));
+
+		igt_debug("REASONS: 1st = \"%s\", 2nd = \"%s\"\n", reason0, reason1);
+	}
+
+	/* Gen8+ has some 40bit A counters... */
+	for (int j = 0; j < format.n_a40; j++) {
+		uint64_t value0 = read_40bit_a_counter(oa_report0, fmt, j);
+		uint64_t value1 = read_40bit_a_counter(oa_report1, fmt, j);
+		uint64_t delta = get_40bit_a_delta(value0, value1);
+
+		igt_debug("A%d: 1st = %"PRIu64", 2nd = %"PRIu64", delta = %"PRIu64"\n",
+			  j, value0, value1, delta);
+	}
+
+	for (int j = 0; j < format.n_a64; j++) {
+		uint64_t value0 = xehpsdv_read_64bit_a_counter(oa_report0, fmt, j);
+		uint64_t value1 = xehpsdv_read_64bit_a_counter(oa_report1, fmt, j);
+		uint64_t delta = value1 - value0;
+
+		igt_debug("A_64%d: 1st = %"PRIu64", 2nd = %"PRIu64", delta = %"PRIu64"\n",
+			  format.first_a + j, value0, value1, delta);
+	}
+
+	for (int j = 0; j < format.n_a; j++) {
+		uint32_t *a0 = (uint32_t *)(((uint8_t *)oa_report0) +
+					    format.a_off);
+		uint32_t *a1 = (uint32_t *)(((uint8_t *)oa_report1) +
+					    format.a_off);
+		int a_id = format.first_a + j;
+		uint32_t delta = a1[j] - a0[j];
+
+		igt_debug("A%d: 1st = %"PRIu32", 2nd = %"PRIu32", delta = %"PRIu32"\n",
+			  a_id, a0[j], a1[j], delta);
+	}
+
+	for (int j = 0; j < format.n_b; j++) {
+		uint32_t *b0 = (uint32_t *)(((uint8_t *)oa_report0) +
+					    format.b_off);
+		uint32_t *b1 = (uint32_t *)(((uint8_t *)oa_report1) +
+					    format.b_off);
+		uint32_t delta = b1[j] - b0[j];
+
+		igt_debug("B%d: 1st = %"PRIu32", 2nd = %"PRIu32", delta = %"PRIu32"\n",
+			  j, b0[j], b1[j], delta);
+	}
+
+	for (int j = 0; j < format.n_c; j++) {
+		uint32_t *c0 = (uint32_t *)(((uint8_t *)oa_report0) +
+					    format.c_off);
+		uint32_t *c1 = (uint32_t *)(((uint8_t *)oa_report1) +
+					    format.c_off);
+		uint32_t delta = c1[j] - c0[j];
+
+		igt_debug("C%d: 1st = %"PRIu32", 2nd = %"PRIu32", delta = %"PRIu32"\n",
+			  j, c0[j], c1[j], delta);
+	}
+}
+
+static bool
+hwe_supports_oa_type(int oa_type, const struct drm_xe_engine_class_instance *hwe)
+{
+	switch (oa_type) {
+	case DRM_XE_OA_FMT_TYPE_OAM:
+	case DRM_XE_OA_FMT_TYPE_OAM_MPEC:
+		return hwe->engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ||
+		       hwe->engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;
+	case DRM_XE_OA_FMT_TYPE_OAG:
+	case DRM_XE_OA_FMT_TYPE_OAR:
+		return hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER;
+	case DRM_XE_OA_FMT_TYPE_OAC:
+		return hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE;
+	case DRM_XE_OA_FMT_TYPE_PEC:
+		return hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
+		       hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE;
+	default:
+		return false;
+	}
+
+}
+
+/**
+ * SUBTEST: oa-formats
+ * Description: Test that supported OA formats work as expected
+ */
+static void test_oa_formats(const struct drm_xe_engine_class_instance *hwe)
+{
+	for (int i = 0; i < XE_OA_FORMAT_MAX; i++) {
+		struct oa_format format = get_oa_format(i);
+		uint32_t oa_report0[format.size / 4];
+		uint32_t oa_report1[format.size / 4];
+
+		if (!format.name) /* sparse, indexed by ID */
+			continue;
+
+		if (!hwe_supports_oa_type(format.oa_type, hwe))
+			continue;
+
+		igt_debug("Checking OA format %s\n", format.name);
+
+		open_and_read_2_oa_reports(i,
+					   oa_exp_1_millisec,
+					   oa_report0,
+					   oa_report1,
+					   false, /* timer reports only */
+					   hwe);
+
+		print_reports(oa_report0, oa_report1, i);
+		sanity_check_reports(oa_report0, oa_report1, i);
+	}
+}
+
+
 static unsigned read_xe_module_ref(void)
 {
 	FILE *fp = fopen("/proc/modules", "r");
@@ -933,8 +1377,25 @@ test_sysctl_defaults(void)
 	igt_assert_eq(paranoid, 1);
 }
 
+#define __for_one_render_engine_0(hwe) \
+	xe_for_each_engine(drm_fd, hwe) \
+		if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER) \
+			break; \
+	for_each_if(hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER) \
+		igt_dynamic_f("rcs-%d", hwe->engine_instance)
+
+#define __for_one_render_engine(hwe)	      \
+	for (int m = 0, done = 0; !done; m++) \
+		for_each_if(m < xe_number_engines(drm_fd) && \
+			    (hwe = &xe_engine(drm_fd, m)->instance) && \
+			    hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER && \
+			    (done = 1)) \
+			igt_dynamic_f("rcs-%d", hwe->engine_instance)
+
 igt_main
 {
+	struct drm_xe_engine_class_instance *hwe = NULL;
+
 	igt_fixture {
 		struct stat sb;
 
@@ -985,6 +1446,10 @@ igt_main
 	igt_subtest("missing-sample-flags")
 		test_missing_sample_flags();
 
+	igt_subtest_with_dynamic("oa-formats")
+		__for_one_render_engine(hwe)
+			test_oa_formats(hwe);
+
 	igt_fixture {
 		/* leave sysctl options in their default state... */
 		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 05/14] tests/intel/xe_oa: Add oa exponent tests
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (3 preceding siblings ...)
  2024-07-01  2:52 ` [PATCH i-g-t 04/14] tests/intel/xe_oa: Add "oa-formats" subtest Ashutosh Dixit
@ 2024-07-01  2:53 ` Ashutosh Dixit
  2024-07-01  2:53 ` [PATCH i-g-t 06/14] tests/intel/xe_oa: buffer-fill, non-zero-reason, enable-disable Ashutosh Dixit
                   ` (12 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:53 UTC (permalink / raw)
  To: igt-dev

Add "invalid-oa-exponent" and "oa-exponents".

v2: Remove ICL specific functionality (Umesh)

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 407 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 407 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 1d8c6eb599..4b6c448c04 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -409,6 +409,27 @@ static u64 oa_format_fields(u64 name)
 }
 #define __ff oa_format_fields
 
+static struct drm_xe_engine_class_instance *oa_unit_engine(int fd, int n)
+{
+	struct drm_xe_query_oa_units *qoa = xe_oa_units(fd);
+	struct drm_xe_engine_class_instance *hwe = NULL;
+	struct drm_xe_oa_unit *oau;
+	u8 *poau;
+
+	poau = (u8 *)&qoa->oa_units[0];
+	for (int i = 0; i < qoa->num_oa_units; i++) {
+		oau = (struct drm_xe_oa_unit *)poau;
+
+		if (i == n) {
+			hwe = &oau->eci[random() % oau->num_engines];
+			break;
+		}
+		poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
+	}
+
+	return hwe;
+}
+
 static void
 __perf_close(int fd)
 {
@@ -603,6 +624,64 @@ max_oa_exponent_for_period_lte(uint64_t period)
 	return -1;
 }
 
+static uint64_t
+oa_exponent_to_ns(int exponent)
+{
+       return 1000000000ULL * (2ULL << exponent) / intel_xe_perf->devinfo.timestamp_frequency;
+}
+
+static bool
+oa_report_ctx_is_valid(uint32_t *report)
+{
+	return report[0] & (1ul << 16);
+}
+
+static uint32_t
+oa_report_get_ctx_id(uint32_t *report)
+{
+	if (!oa_report_ctx_is_valid(report))
+		return 0xffffffff;
+	return report[2];
+}
+
+static void *buf_map(int fd, struct intel_buf *buf, bool write)
+{
+	void *p;
+
+	if (is_xe_device(fd)) {
+		buf->ptr = xe_bo_map(fd, buf->handle, buf->surface[0].size);
+		p = buf->ptr;
+	} else {
+		if (gem_has_llc(fd))
+			p = intel_buf_cpu_map(buf, write);
+		else
+			p = intel_buf_device_map(buf, write);
+	}
+	return p;
+}
+
+static void
+scratch_buf_memset(struct intel_buf *buf, int width, int height, uint32_t color)
+{
+	buf_map(buf_ops_get_fd(buf->bops), buf, true);
+
+	for (int i = 0; i < width * height; i++)
+		buf->ptr[i] = color;
+
+	intel_buf_unmap(buf);
+}
+
+static void
+scratch_buf_init(struct buf_ops *bops,
+		 struct intel_buf *buf,
+		 int width, int height,
+		 uint32_t color)
+{
+	intel_buf_init(bops, buf, width, height, 32, 0,
+		       I915_TILING_NONE, I915_COMPRESSION_NONE);
+	scratch_buf_memset(buf, width, height, color);
+}
+
 static bool
 oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
 {
@@ -1261,6 +1340,296 @@ static void test_oa_formats(const struct drm_xe_engine_class_instance *hwe)
 }
 
 
+enum load {
+	LOW,
+	HIGH
+};
+
+#define LOAD_HELPER_PAUSE_USEC 500
+
+static struct load_helper {
+	int devid;
+	struct buf_ops *bops;
+	uint32_t context_id;
+	uint32_t vm;
+	struct intel_bb *ibb;
+	enum load load;
+	bool exit;
+	struct igt_helper_process igt_proc;
+	struct intel_buf src, dst;
+} lh = { 0, };
+
+static void load_helper_signal_handler(int sig)
+{
+	if (sig == SIGUSR2)
+		lh.load = lh.load == LOW ? HIGH : LOW;
+	else
+		lh.exit = true;
+}
+
+static void load_helper_set_load(enum load load)
+{
+	igt_assert(lh.igt_proc.running);
+
+	if (lh.load == load)
+		return;
+
+	lh.load = load;
+	kill(lh.igt_proc.pid, SIGUSR2);
+}
+
+static void load_helper_run(enum load load)
+{
+	if (!render_copy)
+		return;
+
+	/*
+	 * FIXME fork helpers won't get cleaned up when started from within a
+	 * subtest, so handle the case where it sticks around a bit too long.
+	 */
+	if (lh.igt_proc.running) {
+		load_helper_set_load(load);
+		return;
+	}
+
+	lh.load = load;
+
+	igt_fork_helper(&lh.igt_proc) {
+		signal(SIGUSR1, load_helper_signal_handler);
+		signal(SIGUSR2, load_helper_signal_handler);
+
+		while (!lh.exit) {
+			render_copy(lh.ibb,
+				    &lh.src, 0, 0, 1920, 1080,
+				    &lh.dst, 0, 0);
+
+			intel_bb_sync(lh.ibb);
+
+			/* Lower the load by pausing after every submitted
+			 * write. */
+			if (lh.load == LOW)
+				usleep(LOAD_HELPER_PAUSE_USEC);
+		}
+	}
+}
+
+static void load_helper_stop(void)
+{
+	if (!render_copy)
+		return;
+
+	kill(lh.igt_proc.pid, SIGUSR1);
+	igt_assert(igt_wait_helper(&lh.igt_proc) == 0);
+}
+
+static void load_helper_init(void)
+{
+	if (!render_copy) {
+		igt_info("Running test without render_copy\n");
+		return;
+	}
+
+	lh.devid = intel_get_drm_devid(drm_fd);
+	lh.bops = buf_ops_create(drm_fd);
+	lh.vm = xe_vm_create(drm_fd, 0, 0);
+	lh.context_id = xe_exec_queue_create(drm_fd, lh.vm, &xe_engine(drm_fd, 0)->instance, 0);
+	igt_assert_neq(lh.context_id, 0xffffffff);
+
+	lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, lh.vm, NULL, BATCH_SZ);
+
+	scratch_buf_init(lh.bops, &lh.dst, 1920, 1080, 0);
+	scratch_buf_init(lh.bops, &lh.src, 1920, 1080, 0);
+}
+
+static void load_helper_fini(void)
+{
+	if (!render_copy)
+		return;
+
+	if (lh.igt_proc.running)
+		load_helper_stop();
+
+	intel_buf_close(lh.bops, &lh.src);
+	intel_buf_close(lh.bops, &lh.dst);
+	intel_bb_destroy(lh.ibb);
+	xe_exec_queue_destroy(drm_fd, lh.context_id);
+	xe_vm_destroy(drm_fd, lh.vm);
+	buf_ops_destroy(lh.bops);
+}
+
+static bool expected_report_timing_delta(uint32_t delta, uint32_t expected_delta)
+{
+	return delta <= expected_delta;
+}
+
+/**
+ * SUBTEST: oa-exponents
+ * Description: Test that oa exponent values behave as expected
+ */
+static void test_oa_exponents(const struct drm_xe_engine_class_instance *hwe)
+{
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t fmt = test_set->perf_oa_format;
+
+	load_helper_init();
+	load_helper_run(HIGH);
+
+	/* It's asking a lot to sample with a 160 nanosecond period and the
+	 * test can fail due to buffer overflows if it wasn't possible to
+	 * keep up, so we don't start from an exponent of zero...
+	 */
+	for (int exponent = 5; exponent < 20; exponent++) {
+		uint64_t properties[] = {
+			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+			/* Include OA reports in samples */
+			DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+			/* OA unit configuration */
+			DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
+			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, exponent,
+			DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+		};
+		struct intel_xe_oa_open_prop param = {
+			.num_properties = ARRAY_SIZE(properties) / 2,
+			.properties_ptr = to_user_pointer(properties),
+		};
+		uint64_t expected_timestamp_delta = 2ULL << exponent;
+		size_t format_size = get_oa_format(fmt).size;
+		int max_reports = MAX_OA_BUF_SIZE / format_size;
+		int buf_size = format_size * max_reports * 1.5;
+		uint8_t *buf = calloc(1, buf_size);
+		int ret, n_timer_reports = 0;
+		uint32_t matches = 0;
+#define NUM_TIMER_REPORTS 30
+		uint32_t *reports = malloc(NUM_TIMER_REPORTS * format_size);
+		uint32_t *timer_reports = reports;
+
+		igt_debug("testing OA exponent %d,"
+			  " expected ts delta = %"PRIu64" (%"PRIu64"ns/%.2fus/%.2fms)\n",
+			  exponent, expected_timestamp_delta,
+			  oa_exponent_to_ns(exponent),
+			  oa_exponent_to_ns(exponent) / 1000.0,
+			  oa_exponent_to_ns(exponent) / (1000.0 * 1000.0));
+
+		stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
+
+		while (n_timer_reports < NUM_TIMER_REPORTS) {
+			u32 oa_status = 0;
+
+			while ((ret = read(stream_fd, buf, buf_size)) < 0 && errno == EINTR)
+				;
+			if (errno == EIO) {
+				oa_status = get_stream_status(stream_fd);
+				igt_debug("oa_status %#x\n", oa_status);
+				continue;
+			}
+
+			/* igt_debug(" > read %i bytes\n", ret); */
+			/* We should never have no data. */
+			igt_assert(ret > 0);
+
+			for (int offset = 0;
+			     offset < ret && n_timer_reports < NUM_TIMER_REPORTS;
+			     offset += format_size) {
+				uint32_t *report = (void *)(buf + offset);
+
+				if (oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW) {
+					igt_assert(!"reached");
+					break;
+				}
+
+				if (oa_status & DRM_XE_OASTATUS_REPORT_LOST)
+					igt_debug("report loss\n");
+
+				if (!oa_report_is_periodic(exponent, report))
+					continue;
+
+				memcpy(timer_reports, report, format_size);
+				n_timer_reports++;
+				timer_reports += (format_size / 4);
+			}
+		}
+
+		__perf_close(stream_fd);
+
+		igt_debug("report%04i ts=%"PRIx64" hw_id=0x%08x\n", 0,
+			  oa_timestamp(&reports[0], fmt),
+			  oa_report_get_ctx_id(&reports[0]));
+		for (int i = 1; i < n_timer_reports; i++) {
+			uint64_t delta = oa_timestamp_delta(&reports[i],
+							    &reports[i - 1],
+							    fmt);
+
+			igt_debug("report%04i ts=%"PRIx64" hw_id=0x%08x delta=%"PRIu64" %s\n", i,
+				  oa_timestamp(&reports[i], fmt),
+				  oa_report_get_ctx_id(&reports[i]),
+				  delta, expected_report_timing_delta(delta,
+								      expected_timestamp_delta) ? "" : "******");
+
+			matches += expected_report_timing_delta(delta,expected_timestamp_delta);
+		}
+
+		igt_debug("matches=%u/%u\n", matches, n_timer_reports - 1);
+
+		/*
+		 * Expect half the reports to match the timing
+		 * expectation. The results are quite erratic because
+		 * the condition under which the HW reaches
+		 * expectations depends on memory controller pressure
+		 * etc...
+		 */
+		igt_assert_lte(n_timer_reports / 2, matches);
+
+		free(reports);
+	}
+
+	load_helper_stop();
+	load_helper_fini();
+}
+
+/**
+ * SUBTEST: invalid-oa-exponent
+ * Description: Test that invalid exponent values are rejected
+ */
+/* The OA exponent selects a timestamp counter bit to trigger reports on.
+ *
+ * With a 64bit timestamp and least significant bit approx == 80ns then the MSB
+ * equates to > 40 thousand years and isn't exposed via the xe oa interface.
+ *
+ * The max exponent exposed is expected to be 31, which is still a fairly
+ * ridiculous period (>5min) but is the maximum exponent where it's still
+ * possible to use periodic sampling as a means for tracking the overflow of
+ * 32bit OA report timestamps.
+ */
+static void test_invalid_oa_exponent(void)
+{
+	uint64_t properties[] = {
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, 31, /* maximum exponent expected
+						       to be accepted */
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+
+	__perf_close(stream_fd);
+
+	for (int i = 32; i < 65; i++) {
+		properties[7] = i;
+		intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param, EINVAL);
+	}
+}
+
 static unsigned read_xe_module_ref(void)
 {
 	FILE *fp = fopen("/proc/modules", "r");
@@ -1377,6 +1746,37 @@ test_sysctl_defaults(void)
 	igt_assert_eq(paranoid, 1);
 }
 
+static const char *xe_engine_class_name(uint32_t engine_class)
+{
+	switch (engine_class) {
+		case DRM_XE_ENGINE_CLASS_RENDER:
+			return "rcs";
+		case DRM_XE_ENGINE_CLASS_COPY:
+			return "bcs";
+		case DRM_XE_ENGINE_CLASS_VIDEO_DECODE:
+			return "vcs";
+		case DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE:
+			return "vecs";
+		case DRM_XE_ENGINE_CLASS_COMPUTE:
+			return "ccs";
+		default:
+			igt_warn("Engine class 0x%x unknown\n", engine_class);
+			return "unknown";
+	}
+}
+
+#define __for_one_hwe_in_each_oa_unit(hwe) \
+	for (int m = 0; !m || hwe; m++) \
+		for_each_if(hwe = oa_unit_engine(drm_fd, m)) \
+			igt_dynamic_f("%s-%d", xe_engine_class_name(hwe->engine_class), \
+				      hwe->engine_instance)
+
+/* Only OAG (not OAM) is currently supported */
+#define __for_one_hwe_in_oag(hwe) \
+	if ((hwe = oa_unit_engine(drm_fd, 0))) \
+		igt_dynamic_f("%s-%d", xe_engine_class_name(hwe->engine_class), \
+			      hwe->engine_instance)
+
 #define __for_one_render_engine_0(hwe) \
 	xe_for_each_engine(drm_fd, hwe) \
 		if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER) \
@@ -1450,6 +1850,13 @@ igt_main
 		__for_one_render_engine(hwe)
 			test_oa_formats(hwe);
 
+	igt_subtest("invalid-oa-exponent")
+		test_invalid_oa_exponent();
+
+	igt_subtest_with_dynamic("oa-exponents")
+		__for_one_hwe_in_oag(hwe)
+			test_oa_exponents(hwe);
+
 	igt_fixture {
 		/* leave sysctl options in their default state... */
 		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 06/14] tests/intel/xe_oa: buffer-fill, non-zero-reason, enable-disable
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (4 preceding siblings ...)
  2024-07-01  2:53 ` [PATCH i-g-t 05/14] tests/intel/xe_oa: Add oa exponent tests Ashutosh Dixit
@ 2024-07-01  2:53 ` Ashutosh Dixit
  2024-07-01  2:53 ` [PATCH i-g-t 07/14] tests/intel/xe_oa: blocking and polling tests Ashutosh Dixit
                   ` (11 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:53 UTC (permalink / raw)
  To: igt-dev

Add the following tests:
	"buffer-fill"
	"non-zero-reason"
	"disabled-read-error"
	"enable-disable"
	"short-reads"

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 606 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 606 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 4b6c448c04..c40a632b76 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -1630,6 +1630,591 @@ static void test_invalid_oa_exponent(void)
 	}
 }
 
+/**
+ * SUBTEST: buffer-fill
+ * Description: Test filling, wraparound and overflow of OA buffer
+ */
+static void
+test_buffer_fill(const struct drm_xe_engine_class_instance *hwe)
+{
+	/* ~5 micro second period */
+	int oa_exponent = max_oa_exponent_for_period_lte(5000);
+	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t fmt = test_set->perf_oa_format;
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	size_t report_size = get_oa_format(fmt).size;
+	int buf_size = 65536 * report_size;
+	uint8_t *buf = malloc(buf_size);
+	int len;
+	size_t oa_buf_size = MAX_OA_BUF_SIZE;
+	int n_full_oa_reports = oa_buf_size / report_size;
+	uint64_t fill_duration = n_full_oa_reports * oa_period;
+	uint32_t *last_periodic_report = malloc(report_size);
+	u32 oa_status;
+
+	igt_assert(fill_duration < 1000000000);
+
+	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
+        set_fd_flags(stream_fd, O_CLOEXEC);
+
+	for (int i = 0; i < 5; i++) {
+		bool overflow_seen;
+		uint32_t n_periodic_reports;
+		uint32_t first_timestamp = 0, last_timestamp = 0;
+
+		do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_ENABLE, 0);
+
+		nanosleep(&(struct timespec){ .tv_sec = 0,
+					      .tv_nsec = fill_duration * 1.25 },
+			  NULL);
+again:
+		oa_status = 0;
+		while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
+			;
+
+		if (errno == EIO) {
+			oa_status = get_stream_status(stream_fd);
+			igt_debug("oa_status %#x\n", oa_status);
+			overflow_seen = oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW;
+			igt_assert_eq(overflow_seen, true);
+			goto again;
+		}
+		igt_assert_neq(len, -1);
+
+		do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_DISABLE, 0);
+
+		igt_debug("fill_duration = %"PRIu64"ns, oa_exponent = %u\n",
+			  fill_duration, oa_exponent);
+
+		do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_ENABLE, 0);
+
+		nanosleep(&(struct timespec){ .tv_sec = 0,
+					.tv_nsec = fill_duration / 2 },
+			NULL);
+
+		n_periodic_reports = 0;
+
+		/* Because of the race condition between notification of new
+		 * reports and reports landing in memory, we need to rely on
+		 * timestamps to figure whether we've read enough of them.
+		 */
+		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
+
+			igt_debug("dts=%u elapsed=%"PRIu64" duration=%"PRIu64"\n",
+				  last_timestamp - first_timestamp,
+				  (last_timestamp - first_timestamp) * oa_period,
+				  fill_duration / 2);
+again_1:
+			oa_status = 0;
+			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
+				;
+			if (errno == EIO) {
+				oa_status = get_stream_status(stream_fd);
+				igt_debug("oa_status %#x\n", oa_status);
+				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
+				goto again_1;
+			}
+			igt_assert_neq(len, -1);
+
+			for (int offset = 0; offset < len; offset += report_size) {
+				uint32_t *report = (void *) (buf + offset);
+
+				igt_debug(" > report ts=%"PRIu64""
+					  " ts_delta_last_periodic=%"PRIu64" is_timer=%i ctx_id=%8x nb_periodic=%u\n",
+					  oa_timestamp(report, fmt),
+					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
+					  oa_report_is_periodic(oa_exponent, report),
+					  oa_report_get_ctx_id(report),
+					  n_periodic_reports);
+
+				if (first_timestamp == 0)
+					first_timestamp = oa_timestamp(report, fmt);
+				last_timestamp = oa_timestamp(report, fmt);
+
+				if (oa_report_is_periodic(oa_exponent, report)) {
+					memcpy(last_periodic_report, report, report_size);
+					n_periodic_reports++;
+				}
+			}
+		}
+
+		do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_DISABLE, 0);
+
+		igt_debug("first ts = %u, last ts = %u\n", first_timestamp, last_timestamp);
+
+		igt_debug("%f < %zu < %f\n",
+			  report_size * n_full_oa_reports * 0.45,
+			  n_periodic_reports * report_size,
+			  report_size * n_full_oa_reports * 0.55);
+
+		igt_assert(n_periodic_reports * report_size >
+			   report_size * n_full_oa_reports * 0.45);
+		igt_assert(n_periodic_reports * report_size <
+			   report_size * n_full_oa_reports * 0.55);
+	}
+
+	free(last_periodic_report);
+	free(buf);
+
+	__perf_close(stream_fd);
+}
+
+/**
+ * SUBTEST: non-zero-reason
+ * Description: Test reason field is non-zero. Can also check OA buffer wraparound issues
+ */
+static void
+test_non_zero_reason(const struct drm_xe_engine_class_instance *hwe)
+{
+	/* ~20 micro second period */
+	int oa_exponent = max_oa_exponent_for_period_lte(20000);
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t fmt = test_set->perf_oa_format;
+	size_t report_size = get_oa_format(fmt).size;
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	uint32_t buf_size = 3 * 65536 * report_size;
+	uint8_t *buf = malloc(buf_size);
+	uint32_t total_len = 0;
+	const uint32_t *last_report;
+	int len;
+	u32 oa_status;
+
+	igt_assert(buf);
+
+	igt_debug("Ready to read about %u bytes\n", buf_size);
+
+	load_helper_init();
+	load_helper_run(HIGH);
+
+	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
+        set_fd_flags(stream_fd, O_CLOEXEC);
+
+	while (total_len < buf_size &&
+	       ((len = read(stream_fd, &buf[total_len], buf_size - total_len)) > 0 ||
+		(len == -1 && (errno == EINTR || errno == EIO)))) {
+		if (errno == EIO) {
+			oa_status = get_stream_status(stream_fd);
+			igt_debug("oa_status %#x\n", oa_status);
+			igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
+		}
+		if (len > 0)
+			total_len += len;
+	}
+
+	__perf_close(stream_fd);
+
+	load_helper_stop();
+	load_helper_fini();
+
+	igt_debug("Got %u bytes\n", total_len);
+
+	last_report = NULL;
+	for (uint32_t offset = 0; offset < total_len; offset += report_size) {
+		const uint32_t *report = (void *) (buf + offset);
+		uint32_t reason = (report[0] >> OAREPORT_REASON_SHIFT) & OAREPORT_REASON_MASK;
+
+		igt_assert_neq(reason, 0);
+
+		if (last_report)
+			sanity_check_reports(last_report, report, fmt);
+
+		last_report = report;
+	}
+
+	free(buf);
+}
+
+/**
+ * SUBTEST: enable-disable
+ * Description: Test that OA stream enable/disable works as expected
+ */
+static void
+test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
+{
+	/* ~5 micro second period */
+	int oa_exponent = max_oa_exponent_for_period_lte(5000);
+	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t fmt = test_set->perf_oa_format;
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
+		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	size_t report_size = get_oa_format(fmt).size;
+	int buf_size = 65536 * report_size;
+	uint8_t *buf = malloc(buf_size);
+	size_t oa_buf_size = MAX_OA_BUF_SIZE;
+	int n_full_oa_reports = oa_buf_size / report_size;
+	uint64_t fill_duration = n_full_oa_reports * oa_period;
+	uint32_t *last_periodic_report = malloc(report_size);
+
+	load_helper_init();
+	load_helper_run(HIGH);
+
+	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
+        set_fd_flags(stream_fd, O_CLOEXEC);
+
+	for (int i = 0; i < 5; i++) {
+		int len;
+		uint32_t n_periodic_reports;
+		uint64_t first_timestamp = 0, last_timestamp = 0;
+		u32 oa_status;
+
+		/* Giving enough time for an overflow might help catch whether
+		 * the OA unit has been enabled even if the driver might at
+		 * least avoid copying reports while disabled.
+		 */
+		nanosleep(&(struct timespec){ .tv_sec = 0,
+					      .tv_nsec = fill_duration * 1.25 },
+			  NULL);
+
+		while ((len = read(stream_fd, buf, buf_size)) == -1 &&
+		       (errno == EINTR || errno == EIO))
+			;
+
+		igt_assert_eq(len, -1);
+		igt_assert_eq(errno, EINVAL);
+
+		do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_ENABLE, 0);
+
+		nanosleep(&(struct timespec){ .tv_sec = 0,
+					      .tv_nsec = fill_duration / 2 },
+			NULL);
+
+		n_periodic_reports = 0;
+
+		/* Because of the race condition between notification of new
+		 * reports and reports landing in memory, we need to rely on
+		 * timestamps to figure whether we've read enough of them.
+		 */
+		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
+
+			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
+				;
+			if (errno == EIO) {
+				oa_status = get_stream_status(stream_fd);
+				igt_debug("oa_status %#x\n", oa_status);
+				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
+				continue;
+			}
+			igt_assert_neq(len, -1);
+
+			for (int offset = 0; offset < len; offset += report_size) {
+				uint32_t *report = (void *) (buf + offset);
+
+				if (first_timestamp == 0)
+					first_timestamp = oa_timestamp(report, fmt);
+				last_timestamp = oa_timestamp(report, fmt);
+
+				igt_debug(" > report ts=%"PRIx64""
+					  " ts_delta_last_periodic=%s%"PRIu64""
+					  " is_timer=%i ctx_id=0x%8x\n",
+					  oa_timestamp(report, fmt),
+					  oa_report_is_periodic(oa_exponent, report) ? " " : "*",
+					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
+					  oa_report_is_periodic(oa_exponent, report),
+					  oa_report_get_ctx_id(report));
+
+				if (oa_report_is_periodic(oa_exponent, report)) {
+					memcpy(last_periodic_report, report, report_size);
+
+					/* We want to measure only the periodic reports,
+					 * ctx-switch might inflate the content of the
+					 * buffer and skew or measurement.
+					 */
+					n_periodic_reports++;
+				}
+			}
+		}
+
+		do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_DISABLE, 0);
+
+		igt_debug("first ts = %lu, last ts = %lu\n", first_timestamp, last_timestamp);
+
+		igt_debug("%f < %zu < %f\n",
+			  report_size * n_full_oa_reports * 0.45,
+			  n_periodic_reports * report_size,
+			  report_size * n_full_oa_reports * 0.55);
+
+		igt_assert((n_periodic_reports * report_size) >
+			   (report_size * n_full_oa_reports * 0.45));
+		igt_assert((n_periodic_reports * report_size) <
+			   report_size * n_full_oa_reports * 0.55);
+
+
+		/* It's considered an error to read a stream while it's disabled
+		 * since it would block indefinitely...
+		 */
+		len = read(stream_fd, buf, buf_size);
+
+		igt_assert_eq(len, -1);
+		igt_assert_eq(errno, EINVAL);
+	}
+
+	free(last_periodic_report);
+	free(buf);
+
+	__perf_close(stream_fd);
+
+	load_helper_stop();
+	load_helper_fini();
+}
+
+/**
+ * SUBTEST: short-reads
+ * Description: Test behavior for short reads
+ */
+static void
+test_short_reads(void)
+{
+	int oa_exponent = max_oa_exponent_for_period_lte(5000);
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	size_t record_size = get_oa_format(default_test_set->perf_oa_format).size;
+	size_t page_size = sysconf(_SC_PAGE_SIZE);
+	int zero_fd = open("/dev/zero", O_RDWR|O_CLOEXEC);
+	uint8_t *pages = mmap(NULL, page_size * 2,
+			      PROT_READ|PROT_WRITE, MAP_PRIVATE, zero_fd, 0);
+	u8 *header;
+	int ret, errnum;
+	u32 oa_status;
+
+	igt_assert_neq(zero_fd, -1);
+	close(zero_fd);
+	zero_fd = -1;
+
+	igt_assert(pages);
+
+	ret = mprotect(pages + page_size, page_size, PROT_NONE);
+	igt_assert_eq(ret, 0);
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+
+	nanosleep(&(struct timespec){ .tv_sec = 0, .tv_nsec = 5000000 }, NULL);
+
+	/* At this point there should be lots of pending reports to read */
+
+	/* A read that can return at least one record should result in a short
+	 * read not an EFAULT if the buffer is smaller than the requested read
+	 * size...
+	 *
+	 * Expect to see a sample record here, but at least skip over any
+	 * _RECORD_LOST notifications.
+	 */
+	do {
+		header = (void *)(pages + page_size - record_size);
+		oa_status = 0;
+		ret = read(stream_fd, header, page_size);
+		if (ret < 0 && errno == EIO)
+			oa_status = get_stream_status(stream_fd);
+
+	} while (oa_status & DRM_XE_OASTATUS_REPORT_LOST);
+
+	igt_assert_eq(ret, record_size);
+
+	/* A read that can't return a single record because it would result
+	 * in a fault on buffer overrun should result in an EFAULT error...
+	 *
+	 * Make sure to weed out all report lost errors before verifying EFAULT.
+	 */
+	header = (void *)(pages + page_size - 16);
+	do {
+		oa_status = 0;
+		ret = read(stream_fd, header, page_size);
+		errnum = errno;
+		if (ret < 0 && errno == EIO)
+			oa_status = get_stream_status(stream_fd);
+		errno = errnum;
+	} while (oa_status & DRM_XE_OASTATUS_REPORT_LOST);
+
+	igt_assert_eq(ret, -1);
+	igt_assert_eq(errno, EFAULT);
+
+	/* A read that can't return a single record because the buffer is too
+	 * small should result in an ENOSPC error..
+	 *
+	 * Again, skip over _RECORD_LOST records (smaller than record_size/2)
+	 */
+	do {
+		header = (void *)(pages + page_size - record_size / 2);
+		oa_status = 0;
+		ret = read(stream_fd, header, record_size / 2);
+		errnum = errno;
+		if (ret < 0 && errno == EIO)
+			oa_status = get_stream_status(stream_fd);
+		errno = errnum;
+	} while (oa_status & DRM_XE_OASTATUS_REPORT_LOST);
+
+	igt_assert_eq(ret, -1);
+	igt_assert_eq(errno, ENOSPC);
+
+	__perf_close(stream_fd);
+
+	munmap(pages, page_size * 2);
+}
+
+/**
+ * SUBTEST: non-sampling-read-error
+ * Description: Test that a stream without periodic sampling (no exponent) cannot be read
+ */
+static void
+test_non_sampling_read_error(void)
+{
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* XXX: even without periodic sampling we have to
+		 * specify at least one sample layout property...
+		 */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+
+		/* XXX: no sampling exponent */
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	int ret;
+	uint8_t buf[1024];
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+        set_fd_flags(stream_fd, O_CLOEXEC);
+
+	ret = read(stream_fd, buf, sizeof(buf));
+	igt_assert_eq(ret, -1);
+	igt_assert_eq(errno, EINVAL);
+
+	__perf_close(stream_fd);
+}
+
+/**
+ * SUBTEST: disabled-read-error
+ * Description: Test that attempts to read from a stream while it is disable
+ *		will return EINVAL instead of blocking indefinitely
+ */
+static void
+test_disabled_read_error(void)
+{
+	int oa_exponent = 5; /* 5 micro seconds */
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* XXX: even without periodic sampling we have to
+		 * specify at least one sample layout property...
+		 */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	uint32_t oa_report0[64];
+	uint32_t oa_report1[64];
+	uint32_t buf[128] = { 0 };
+	int ret;
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+
+	ret = read(stream_fd, buf, sizeof(buf));
+	igt_assert_eq(ret, -1);
+	igt_assert_eq(errno, EINVAL);
+
+	__perf_close(stream_fd);
+
+	properties[ARRAY_SIZE(properties) - 1] = false; /* Set DISABLED to false */
+	stream_fd = __perf_open(drm_fd, &param, false);
+        set_fd_flags(stream_fd, O_CLOEXEC);
+
+	read_2_oa_reports(default_test_set->perf_oa_format,
+			  oa_exponent,
+			  oa_report0,
+			  oa_report1,
+			  false); /* not just timer reports */
+
+	do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_DISABLE, 0);
+
+	ret = read(stream_fd, buf, sizeof(buf));
+	igt_assert_eq(ret, -1);
+	igt_assert_eq(errno, EINVAL);
+
+	do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_ENABLE, 0);
+
+	read_2_oa_reports(default_test_set->perf_oa_format,
+			  oa_exponent,
+			  oa_report0,
+			  oa_report1,
+			  false); /* not just timer reports */
+
+	__perf_close(stream_fd);
+}
+
 static unsigned read_xe_module_ref(void)
 {
 	FILE *fp = fopen("/proc/modules", "r");
@@ -1857,6 +2442,27 @@ igt_main
 		__for_one_hwe_in_oag(hwe)
 			test_oa_exponents(hwe);
 
+	igt_subtest_with_dynamic("buffer-fill")
+		__for_one_hwe_in_oag(hwe)
+			test_buffer_fill(hwe);
+
+	igt_subtest_with_dynamic("non-zero-reason") {
+		__for_one_hwe_in_oag(hwe)
+			test_non_zero_reason(hwe);
+	}
+
+	igt_subtest("disabled-read-error")
+		test_disabled_read_error();
+	igt_subtest("non-sampling-read-error")
+		test_non_sampling_read_error();
+
+	igt_subtest_with_dynamic("enable-disable")
+		__for_one_hwe_in_oag(hwe)
+			test_enable_disable(hwe);
+
+	igt_subtest("short-reads")
+		test_short_reads();
+
 	igt_fixture {
 		/* leave sysctl options in their default state... */
 		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 07/14] tests/intel/xe_oa: blocking and polling tests
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (5 preceding siblings ...)
  2024-07-01  2:53 ` [PATCH i-g-t 06/14] tests/intel/xe_oa: buffer-fill, non-zero-reason, enable-disable Ashutosh Dixit
@ 2024-07-01  2:53 ` Ashutosh Dixit
  2024-07-01  2:53 ` [PATCH i-g-t 08/14] tests/intel/xe_oa: OAR/OAC tests Ashutosh Dixit
                   ` (10 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:53 UTC (permalink / raw)
  To: igt-dev

"blocking", "polling" and "polling-small-buf".

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 463 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 463 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index c40a632b76..a1eb1dafeb 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -430,6 +430,24 @@ static struct drm_xe_engine_class_instance *oa_unit_engine(int fd, int n)
 	return hwe;
 }
 
+static char *
+pretty_print_oa_period(uint64_t oa_period_ns)
+{
+	static char result[100];
+	static const char *units[4] = { "ns", "us", "ms", "s" };
+	double val = oa_period_ns;
+	int iter = 0;
+
+	while (iter < (ARRAY_SIZE(units) - 1) &&
+	       val >= 1000.0f) {
+		val /= 1000.0f;
+		iter++;
+	}
+
+	snprintf(result, sizeof(result), "%.3f%s", val, units[iter]);
+	return result;
+}
+
 static void
 __perf_close(int fd)
 {
@@ -1630,6 +1648,432 @@ static void test_invalid_oa_exponent(void)
 	}
 }
 
+static int64_t
+get_time(void)
+{
+	struct timespec ts;
+
+	clock_gettime(CLOCK_MONOTONIC, &ts);
+
+	return ts.tv_sec * 1000000000 + ts.tv_nsec;
+}
+
+/**
+ * SUBTEST: blocking
+ * Description: Test blocking reads
+ */
+/* Note: The interface doesn't currently provide strict guarantees or control
+ * over the upper bound for how long it might take for a POLLIN event after
+ * some OA report is written by the OA unit.
+ *
+ * The plan is to add a property later that gives some control over the maximum
+ * latency, but for now we expect it is tuned for a fairly low latency
+ * suitable for applications wanting to provide live feedback for captured
+ * metrics.
+ *
+ * At the time of writing this test the driver was using a fixed 200Hz hrtimer
+ * regardless of the OA sampling exponent.
+ *
+ * There is no lower bound since a stream configured for periodic sampling may
+ * still contain other automatically triggered reports.
+ *
+ * What we try and check for here is that blocking reads don't return EAGAIN
+ * and that we aren't spending any significant time burning the cpu in
+ * kernelspace.
+ */
+static void test_blocking(uint64_t requested_oa_period,
+			  bool set_kernel_hrtimer,
+			  uint64_t kernel_hrtimer,
+			  const struct drm_xe_engine_class_instance *hwe)
+{
+	int oa_exponent = max_oa_exponent_for_period_lte(requested_oa_period);
+	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
+	uint64_t props[XE_OA_MAX_SET_PROPERTIES * 2];
+	uint64_t *idx = props;
+	struct intel_xe_oa_open_prop param;
+	uint8_t buf[1024 * 1024];
+	struct tms start_times;
+	struct tms end_times;
+	int64_t user_ns, kernel_ns;
+	int64_t tick_ns = 1000000000 / sysconf(_SC_CLK_TCK);
+	int64_t test_duration_ns = tick_ns * 100;
+	int max_iterations = (test_duration_ns / oa_period) + 2;
+	int n_extra_iterations = 0;
+	int perf_fd;
+
+	/* It's a bit tricky to put a lower limit here, but we expect a
+	 * relatively low latency for seeing reports, while we don't currently
+	 * give any control over this in the api.
+	 *
+	 * We assume a maximum latency of 6 millisecond to deliver a POLLIN and
+	 * read() after a new sample is written (46ms per iteration) considering
+	 * the knowledge that that the driver uses a 200Hz hrtimer (5ms period)
+	 * to check for data and giving some time to read().
+	 */
+	int min_iterations = (test_duration_ns / (oa_period + kernel_hrtimer + kernel_hrtimer / 5));
+	int64_t start, end;
+	int n = 0;
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	size_t format_size = get_oa_format(test_set->perf_oa_format).size;
+
+	ADD_PROPS(props, idx, SAMPLE_OA, true);
+	ADD_PROPS(props, idx, OA_METRIC_SET, test_set->perf_oa_metrics_set);
+	ADD_PROPS(props, idx, OA_FORMAT, __ff(test_set->perf_oa_format));
+	ADD_PROPS(props, idx, OA_PERIOD_EXPONENT, oa_exponent);
+	ADD_PROPS(props, idx, OA_DISABLED, true);
+	ADD_PROPS(props, idx, OA_UNIT_ID, 0);
+	ADD_PROPS(props, idx, OA_ENGINE_INSTANCE, hwe->engine_instance);
+
+	param.num_properties = (idx - props) / 2;
+	param.properties_ptr = to_user_pointer(props);
+
+	perf_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
+        set_fd_flags(perf_fd, O_CLOEXEC);
+
+	times(&start_times);
+
+	igt_debug("tick length = %dns, test duration = %"PRIu64"ns, min iter. = %d,"
+		  " estimated max iter. = %d, oa_period = %s\n",
+		  (int)tick_ns, test_duration_ns,
+		  min_iterations, max_iterations,
+		  pretty_print_oa_period(oa_period));
+
+	/* In the loop we perform blocking polls while the HW is sampling at
+	 * ~25Hz, with the expectation that we spend most of our time blocked
+	 * in the kernel, and shouldn't be burning cpu cycles in the kernel in
+	 * association with this process (verified by looking at stime before
+	 * and after loop).
+	 *
+	 * We're looking to assert that less than 1% of the test duration is
+	 * spent in the kernel dealing with polling and read()ing.
+	 *
+	 * The test runs for a relatively long time considering the very low
+	 * resolution of stime in ticks of typically 10 milliseconds. Since we
+	 * don't know the fractional part of tick values we read from userspace
+	 * so our minimum threshold needs to be >= one tick since any
+	 * measurement might really be +- tick_ns (assuming we effectively get
+	 * floor(real_stime)).
+	 *
+	 * We Loop for 1000 x tick_ns so one tick corresponds to 0.1%
+	 *
+	 * Also enable the stream just before poll/read to minimize
+	 * the error delta.
+	 */
+	start = get_time();
+	do_ioctl(perf_fd, DRM_XE_PERF_IOCTL_ENABLE, 0);
+	for (/* nop */; ((end = get_time()) - start) < test_duration_ns; /* nop */) {
+		bool timer_report_read = false;
+		bool non_timer_report_read = false;
+		int ret;
+
+		while ((ret = read(perf_fd, buf, sizeof(buf))) < 0 &&
+		       (errno == EINTR || errno == EIO))
+			;
+		igt_assert(ret > 0);
+
+		for (int offset = 0; offset < ret; offset += format_size) {
+			uint32_t *report = (void *)(buf + offset);
+
+			if (oa_report_is_periodic(oa_exponent, report))
+				timer_report_read = true;
+			else
+				non_timer_report_read = true;
+		}
+
+		if (non_timer_report_read && !timer_report_read)
+			n_extra_iterations++;
+
+		n++;
+	}
+
+	times(&end_times);
+
+	/* Using nanosecond units is fairly silly here, given the tick in-
+	 * precision - ah well, it's consistent with the get_time() units.
+	 */
+	user_ns = (end_times.tms_utime - start_times.tms_utime) * tick_ns;
+	kernel_ns = (end_times.tms_stime - start_times.tms_stime) * tick_ns;
+
+	igt_debug("%d blocking reads during test with %"PRIu64" Hz OA sampling (expect no more than %d)\n",
+		  n, NSEC_PER_SEC / oa_period, max_iterations);
+	igt_debug("%d extra iterations seen, not related to periodic sampling (e.g. context switches)\n",
+		  n_extra_iterations);
+	igt_debug("time in userspace = %"PRIu64"ns (+-%dns) (start utime = %d, end = %d)\n",
+		  user_ns, (int)tick_ns,
+		  (int)start_times.tms_utime, (int)end_times.tms_utime);
+	igt_debug("time in kernelspace = %"PRIu64"ns (+-%dns) (start stime = %d, end = %d)\n",
+		  kernel_ns, (int)tick_ns,
+		  (int)start_times.tms_stime, (int)end_times.tms_stime);
+
+	/* With completely broken blocking (but also not returning an error) we
+	 * could end up with an open loop,
+	 */
+	igt_assert(n <= (max_iterations + n_extra_iterations));
+
+	/* Make sure the driver is reporting new samples with a reasonably
+	 * low latency...
+	 */
+	igt_assert(n > (min_iterations + n_extra_iterations));
+
+	if (!set_kernel_hrtimer)
+		igt_assert(kernel_ns <= (test_duration_ns / 100ull));
+
+	__perf_close(perf_fd);
+}
+
+/**
+ * SUBTEST: polling
+ * Description: Test polled reads
+ */
+static void test_polling(uint64_t requested_oa_period,
+			 bool set_kernel_hrtimer,
+			 uint64_t kernel_hrtimer,
+			 const struct drm_xe_engine_class_instance *hwe)
+{
+	int oa_exponent = max_oa_exponent_for_period_lte(requested_oa_period);
+	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
+	uint64_t props[XE_OA_MAX_SET_PROPERTIES * 2];
+	uint64_t *idx = props;
+	struct intel_xe_oa_open_prop param;
+	uint8_t buf[1024 * 1024];
+	struct tms start_times;
+	struct tms end_times;
+	int64_t user_ns, kernel_ns;
+	int64_t tick_ns = 1000000000 / sysconf(_SC_CLK_TCK);
+	int64_t test_duration_ns = tick_ns * 100;
+
+	int max_iterations = (test_duration_ns / oa_period) + 2;
+	int n_extra_iterations = 0;
+
+	/* It's a bit tricky to put a lower limit here, but we expect a
+	 * relatively low latency for seeing reports.
+	 *
+	 * We assume a maximum latency of kernel_hrtimer + some margin
+	 * to deliver a POLLIN and read() after a new sample is
+	 * written (40ms + hrtimer + margin per iteration) considering
+	 * the knowledge that that the driver uses a 200Hz hrtimer
+	 * (5ms period) to check for data and giving some time to
+	 * read().
+	 */
+	int min_iterations = (test_duration_ns / (oa_period + (kernel_hrtimer + kernel_hrtimer / 5)));
+	int64_t start, end;
+	int n = 0;
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	size_t format_size = get_oa_format(test_set->perf_oa_format).size;
+
+	ADD_PROPS(props, idx, SAMPLE_OA, true);
+	ADD_PROPS(props, idx, OA_METRIC_SET, test_set->perf_oa_metrics_set);
+	ADD_PROPS(props, idx, OA_FORMAT, __ff(test_set->perf_oa_format));
+	ADD_PROPS(props, idx, OA_PERIOD_EXPONENT, oa_exponent);
+	ADD_PROPS(props, idx, OA_DISABLED, true);
+	ADD_PROPS(props, idx, OA_UNIT_ID, 0);
+	ADD_PROPS(props, idx, OA_ENGINE_INSTANCE, hwe->engine_instance);
+
+	param.num_properties = (idx - props) / 2;
+	param.properties_ptr = to_user_pointer(props);
+
+	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
+	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
+
+	times(&start_times);
+
+	igt_debug("tick length = %dns, oa period = %s, "
+		  "test duration = %"PRIu64"ns, min iter. = %d, max iter. = %d\n",
+		  (int)tick_ns, pretty_print_oa_period(oa_period), test_duration_ns,
+		  min_iterations, max_iterations);
+
+	/* In the loop we perform blocking polls while the HW is sampling at
+	 * ~25Hz, with the expectation that we spend most of our time blocked
+	 * in the kernel, and shouldn't be burning cpu cycles in the kernel in
+	 * association with this process (verified by looking at stime before
+	 * and after loop).
+	 *
+	 * We're looking to assert that less than 1% of the test duration is
+	 * spent in the kernel dealing with polling and read()ing.
+	 *
+	 * The test runs for a relatively long time considering the very low
+	 * resolution of stime in ticks of typically 10 milliseconds. Since we
+	 * don't know the fractional part of tick values we read from userspace
+	 * so our minimum threshold needs to be >= one tick since any
+	 * measurement might really be +- tick_ns (assuming we effectively get
+	 * floor(real_stime)).
+	 *
+	 * We Loop for 1000 x tick_ns so one tick corresponds to 0.1%
+	 *
+	 * Also enable the stream just before poll/read to minimize
+	 * the error delta.
+	 */
+	start = get_time();
+	do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_ENABLE, 0);
+	for (/* nop */; ((end = get_time()) - start) < test_duration_ns; /* nop */) {
+		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
+		bool timer_report_read = false;
+		bool non_timer_report_read = false;
+		int ret;
+
+		while ((ret = poll(&pollfd, 1, -1)) < 0 && errno == EINTR)
+			;
+		igt_assert_eq(ret, 1);
+		igt_assert(pollfd.revents & POLLIN);
+
+		while ((ret = read(stream_fd, buf, sizeof(buf))) < 0 &&
+		       (errno == EINTR || errno == EIO))
+			;
+
+		/* Don't expect to see EAGAIN if we've had a POLLIN event
+		 *
+		 * XXX: actually this is technically overly strict since we do
+		 * knowingly allow false positive POLLIN events. At least in
+		 * the future when supporting context filtering of metrics for
+		 * Gen8+ handled in the kernel then POLLIN events may be
+		 * delivered when we know there are pending reports to process
+		 * but before we've done any filtering to know for certain that
+		 * any reports are destined to be copied to userspace.
+		 *
+		 * Still, for now it's a reasonable sanity check.
+		 */
+		if (ret < 0)
+			igt_debug("Unexpected error when reading after poll = %d\n", errno);
+		igt_assert_neq(ret, -1);
+
+		/* For Haswell reports don't contain a well defined reason
+		 * field we so assume all reports to be 'periodic'. For gen8+
+		 * we want to to consider that the HW automatically writes some
+		 * non periodic reports (e.g. on context switch) which might
+		 * lead to more successful read()s than expected due to
+		 * periodic sampling and we don't want these extra reads to
+		 * cause the test to fail...
+		 */
+		for (int offset = 0; offset < ret; offset += format_size) {
+			uint32_t *report = (void *)(buf + offset);
+
+			if (oa_report_is_periodic(oa_exponent, report))
+				timer_report_read = true;
+			else
+				non_timer_report_read = true;
+		}
+
+		if (non_timer_report_read && !timer_report_read)
+			n_extra_iterations++;
+
+		/* At this point, after consuming pending reports (and hoping
+		 * the scheduler hasn't stopped us for too long) we now expect
+		 * EAGAIN on read. While this works most of the times, there are
+		 * some rare failures when the OA period passed to this test is
+		 * very small (say 500 us) and that results in some valid
+		 * reports here. To weed out those rare occurences we assert
+		 * only if the OA period is >= 40 ms because 40 ms has withstood
+		 * the test of time on most platforms (ref: subtest: polling).
+		 */
+		while ((ret = read(stream_fd, buf, sizeof(buf))) < 0 &&
+		       (errno == EINTR || errno == EIO))
+			;
+
+		if (requested_oa_period >= 40000000) {
+			igt_assert_eq(ret, -1);
+			igt_assert_eq(errno, EAGAIN);
+		}
+
+		n++;
+	}
+
+	times(&end_times);
+
+	/* Using nanosecond units is fairly silly here, given the tick in-
+	 * precision - ah well, it's consistent with the get_time() units.
+	 */
+	user_ns = (end_times.tms_utime - start_times.tms_utime) * tick_ns;
+	kernel_ns = (end_times.tms_stime - start_times.tms_stime) * tick_ns;
+
+	igt_debug("%d non-blocking reads during test with %"PRIu64" Hz OA sampling (expect no more than %d)\n",
+		  n, NSEC_PER_SEC / oa_period, max_iterations);
+	igt_debug("%d extra iterations seen, not related to periodic sampling (e.g. context switches)\n",
+		  n_extra_iterations);
+	igt_debug("time in userspace = %"PRIu64"ns (+-%dns) (start utime = %d, end = %d)\n",
+		  user_ns, (int)tick_ns,
+		  (int)start_times.tms_utime, (int)end_times.tms_utime);
+	igt_debug("time in kernelspace = %"PRIu64"ns (+-%dns) (start stime = %d, end = %d)\n",
+		  kernel_ns, (int)tick_ns,
+		  (int)start_times.tms_stime, (int)end_times.tms_stime);
+
+	/* With completely broken blocking while polling (but still somehow
+	 * reporting a POLLIN event) we could end up with an open loop.
+	 */
+	igt_assert(n <= (max_iterations + n_extra_iterations));
+
+	/* Make sure the driver is reporting new samples with a reasonably
+	 * low latency...
+	 */
+	igt_assert(n > (min_iterations + n_extra_iterations));
+
+	if (!set_kernel_hrtimer)
+		igt_assert(kernel_ns <= (test_duration_ns / 100ull));
+
+	__perf_close(stream_fd);
+}
+
+/**
+ * SUBTEST: polling-small-buf
+ * Description: Test polled read with buffer size smaller than available data
+ */
+static void test_polling_small_buf(void)
+{
+	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	uint32_t test_duration = 80 * 1000 * 1000;
+	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
+	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
+	int n_expect_read_bytes = n_expected_reports * sample_size;
+	struct timespec ts = {};
+	int n_bytes_read = 0;
+	uint32_t n_polls = 0;
+
+	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
+	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
+	do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_ENABLE, 0);
+
+	while (igt_nsec_elapsed(&ts) < test_duration) {
+		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
+
+		ppoll(&pollfd, 1, NULL, NULL);
+		if (pollfd.revents & POLLIN) {
+			uint8_t buf[1024];
+			int ret;
+
+			ret = read(stream_fd, buf, sizeof(buf));
+			if (ret >= 0)
+				n_bytes_read += ret;
+		}
+
+		n_polls++;
+	}
+
+	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
+		 n_bytes_read, n_expect_read_bytes,
+		 n_bytes_read * 100.0f / n_expect_read_bytes,
+		 n_polls);
+
+	__perf_close(stream_fd);
+
+	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
+		   0.20 * n_expect_read_bytes);
+}
+
 /**
  * SUBTEST: buffer-fill
  * Description: Test filling, wraparound and overflow of OA buffer
@@ -2460,6 +2904,25 @@ igt_main
 		__for_one_hwe_in_oag(hwe)
 			test_enable_disable(hwe);
 
+	igt_subtest_with_dynamic("blocking") {
+		__for_one_hwe_in_oag(hwe)
+			test_blocking(40 * 1000 * 1000 /* 40ms oa period */,
+				      false /* set_kernel_hrtimer */,
+				      5 * 1000 * 1000 /* default 5ms/200Hz hrtimer */,
+				      hwe);
+	}
+
+	igt_subtest_with_dynamic("polling") {
+		__for_one_hwe_in_oag(hwe)
+			test_polling(40 * 1000 * 1000 /* 40ms oa period */,
+				     false /* set_kernel_hrtimer */,
+				     5 * 1000 * 1000 /* default 5ms/200Hz hrtimer */,
+				     hwe);
+	}
+
+	igt_subtest("polling-small-buf")
+		test_polling_small_buf();
+
 	igt_subtest("short-reads")
 		test_short_reads();
 
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 08/14] tests/intel/xe_oa: OAR/OAC tests
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (6 preceding siblings ...)
  2024-07-01  2:53 ` [PATCH i-g-t 07/14] tests/intel/xe_oa: blocking and polling tests Ashutosh Dixit
@ 2024-07-01  2:53 ` Ashutosh Dixit
  2024-07-01  2:53 ` [PATCH i-g-t 09/14] tests/intel/xe_oa: Exclusive/concurrent access, rc6 and stress open close Ashutosh Dixit
                   ` (9 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:53 UTC (permalink / raw)
  To: igt-dev

"mi-rpc", "oa-tlb-invalidate" and "unprivileged-single-ctx-counters" tests.

v2: Run "oa-tlb-invalidate" only for specific product versions (Umesh)

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 701 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 701 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index a1eb1dafeb..8a28e054da 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -596,6 +596,18 @@ read_report_reason(const uint32_t *report)
 		return "unknown";
 }
 
+static uint32_t
+cs_timestamp_frequency(int fd)
+{
+	return xe_gt_list(drm_fd)->gt_list[0].reference_clock;
+}
+
+static uint64_t
+cs_timebase_scale(uint32_t u32_delta)
+{
+	return ((uint64_t)u32_delta * NSEC_PER_SEC) / cs_timestamp_frequency(drm_fd);
+}
+
 static uint64_t
 oa_timestamp(const uint32_t *report, enum intel_xe_oa_format_name format)
 {
@@ -662,6 +674,15 @@ oa_report_get_ctx_id(uint32_t *report)
 	return report[2];
 }
 
+static int
+oar_unit_default_format(void)
+{
+	if (IS_DG2(devid) || IS_METEORLAKE(devid))
+		return XE_OAR_FORMAT_A32u40_A4u32_B8_C8;
+
+	return default_test_set->perf_oa_format;
+}
+
 static void *buf_map(int fd, struct intel_buf *buf, bool write)
 {
 	void *p;
@@ -700,6 +721,21 @@ scratch_buf_init(struct buf_ops *bops,
 	scratch_buf_memset(buf, width, height, color);
 }
 
+static void
+emit_report_perf_count(struct intel_bb *ibb,
+		       struct intel_buf *dst,
+		       int dst_offset,
+		       uint32_t report_id)
+{
+	intel_bb_add_intel_buf(ibb, dst, true);
+
+	intel_bb_out(ibb, OA_MI_REPORT_PERF_COUNT);
+	intel_bb_emit_reloc(ibb, dst->handle,
+			    I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+			    dst_offset, dst->addr.offset);
+	intel_bb_out(ibb, report_id);
+}
+
 static bool
 oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
 {
@@ -740,6 +776,31 @@ get_40bit_a_delta(uint64_t value0, uint64_t value1)
 		return value1 - value0;
 }
 
+static void
+accumulate_uint32(size_t offset,
+		  uint32_t *report0,
+                  uint32_t *report1,
+                  uint64_t *delta)
+{
+	uint32_t value0 = *(uint32_t *)(((uint8_t *)report0) + offset);
+	uint32_t value1 = *(uint32_t *)(((uint8_t *)report1) + offset);
+
+	*delta += (uint32_t)(value1 - value0);
+}
+
+static void
+accumulate_uint40(int a_index,
+                  uint32_t *report0,
+                  uint32_t *report1,
+		  enum intel_xe_oa_format_name format,
+                  uint64_t *delta)
+{
+	uint64_t value0 = read_40bit_a_counter(report0, format, a_index),
+		 value1 = read_40bit_a_counter(report1, format, a_index);
+
+	*delta += get_40bit_a_delta(value0, value1);
+}
+
 static void
 accumulate_uint64(int a_index,
 		  const uint32_t *report0,
@@ -753,6 +814,78 @@ accumulate_uint64(int a_index,
 	*delta += (value1 - value0);
 }
 
+static void
+accumulate_reports(struct accumulator *accumulator,
+		   uint32_t *start,
+		   uint32_t *end)
+{
+	struct oa_format format = get_oa_format(accumulator->format);
+	uint64_t *deltas = accumulator->deltas;
+	int idx = 0;
+
+	/* timestamp */
+	deltas[idx] += oa_timestamp_delta(end, start, accumulator->format);
+	idx++;
+
+	/* clock cycles */
+	deltas[idx] += oa_tick_delta(end, start, accumulator->format);
+	idx++;
+
+	for (int i = 0; i < format.n_a40; i++) {
+		accumulate_uint40(i, start, end, accumulator->format,
+				  deltas + idx++);
+	}
+
+	for (int i = 0; i < format.n_a64; i++) {
+		accumulate_uint64(i, start, end, accumulator->format,
+				  deltas + idx++);
+	}
+
+	for (int i = 0; i < format.n_a; i++) {
+		accumulate_uint32(format.a_off + 4 * i,
+				  start, end, deltas + idx++);
+	}
+
+	for (int i = 0; i < format.n_b; i++) {
+		accumulate_uint32(format.b_off + 4 * i,
+				  start, end, deltas + idx++);
+	}
+
+	for (int i = 0; i < format.n_c; i++) {
+		accumulate_uint32(format.c_off + 4 * i,
+				  start, end, deltas + idx++);
+	}
+}
+
+static void
+accumulator_print(struct accumulator *accumulator, const char *title)
+{
+	struct oa_format format = get_oa_format(accumulator->format);
+	uint64_t *deltas = accumulator->deltas;
+	int idx = 0;
+
+	igt_debug("%s:\n", title);
+	igt_debug("\ttime delta = %"PRIu64"\n", deltas[idx++]);
+	igt_debug("\tclock cycle delta = %"PRIu64"\n", deltas[idx++]);
+
+	for (int i = 0; i < format.n_a40; i++)
+		igt_debug("\tA%u = %"PRIu64"\n", i, deltas[idx++]);
+
+	for (int i = 0; i < format.n_a64; i++)
+		igt_debug("\tA64_%u = %"PRIu64"\n", i, deltas[idx++]);
+
+	for (int i = 0; i < format.n_a; i++) {
+		int a_id = format.first_a + i;
+		igt_debug("\tA%u = %"PRIu64"\n", a_id, deltas[idx++]);
+	}
+
+	for (int i = 0; i < format.n_a; i++)
+		igt_debug("\tB%u = %"PRIu64"\n", i, deltas[idx++]);
+
+	for (int i = 0; i < format.n_c; i++)
+		igt_debug("\tC%u = %"PRIu64"\n", i, deltas[idx++]);
+}
+
 /* The TestOa metric set is designed so */
 static void
 sanity_check_reports(const uint32_t *oa_report0, const uint32_t *oa_report1,
@@ -2074,6 +2207,92 @@ static void test_polling_small_buf(void)
 		   0.20 * n_expect_read_bytes);
 }
 
+static int
+num_valid_reports_captured(struct intel_xe_oa_open_prop *param,
+			   int64_t *duration_ns, int fmt)
+{
+	uint8_t buf[1024 * 1024];
+	int64_t start, end;
+	int num_reports = 0;
+	size_t format_size = get_oa_format(fmt).size;
+
+	igt_debug("Expected duration = %"PRId64"\n", *duration_ns);
+
+	stream_fd = __perf_open(drm_fd, param, true);
+
+	start = get_time();
+	do_ioctl(stream_fd, DRM_XE_PERF_IOCTL_ENABLE, 0);
+	for (/* nop */; ((end = get_time()) - start) < *duration_ns; /* nop */) {
+		int ret;
+
+		while ((ret = read(stream_fd, buf, sizeof(buf))) < 0 &&
+		       (errno == EINTR || errno == EIO))
+			;
+
+		igt_assert(ret > 0);
+
+		for (int offset = 0; offset < ret; offset += format_size) {
+			uint32_t *report = (void *)(buf + offset);
+
+			if (report_reason(report) & OAREPORT_REASON_TIMER)
+				num_reports++;
+		}
+	}
+	__perf_close(stream_fd);
+
+	*duration_ns = end - start;
+
+	igt_debug("Actual duration = %"PRIu64"\n", *duration_ns);
+
+	return num_reports;
+}
+
+/**
+ * SUBTEST: oa-tlb-invalidate
+ * Description: Open OA stream twice to verify OA TLB invalidation
+ */
+static void
+test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
+{
+	int oa_exponent = max_oa_exponent_for_period_lte(30000000);
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
+		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	int num_reports1, num_reports2, num_expected_reports;
+	int64_t duration;
+
+	/* Capture reports for 5 seconds twice and then make sure you get around
+	 * the same number of reports. In the case of failure, the number of
+	 * reports will vary largely since the beginning of the OA buffer
+	 * will have invalid entries.
+	 */
+	duration = 5LL * NSEC_PER_SEC;
+	num_reports1 = num_valid_reports_captured(&param, &duration, test_set->perf_oa_format);
+	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent);
+	igt_debug("expected num reports = %d\n", num_expected_reports);
+	igt_debug("actual num reports = %d\n", num_reports1);
+	igt_assert(num_reports1 > 0.95 * num_expected_reports);
+
+	duration = 5LL * NSEC_PER_SEC;
+	num_reports2 = num_valid_reports_captured(&param, &duration, test_set->perf_oa_format);
+	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent);
+	igt_debug("expected num reports = %d\n", num_expected_reports);
+	igt_debug("actual num reports = %d\n", num_reports2);
+	igt_assert(num_reports2 > 0.95 * num_expected_reports);
+}
+
 /**
  * SUBTEST: buffer-fill
  * Description: Test filling, wraparound and overflow of OA buffer
@@ -2659,6 +2878,468 @@ test_disabled_read_error(void)
 	__perf_close(stream_fd);
 }
 
+/**
+ * SUBTEST: mi-rpc
+ * Description: Test OAR/OAC using MI_REPORT_PERF_COUNT
+ */
+static void
+test_mi_rpc(struct drm_xe_engine_class_instance *hwe)
+
+{
+	uint64_t fmt = ((IS_DG2(devid) || IS_METEORLAKE(devid)) &&
+			hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) ?
+		XE_OAC_FORMAT_A24u64_B8_C8 : oar_unit_default_format();
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* On Gen12, MI RPC uses OAR. OAR is configured only for the
+		 * render context that wants to measure the performance. Hence a
+		 * context must be specified in the gen12 MI RPC when compared
+		 * to previous gens.
+		 *
+		 * Have a random value here for the context id, but initialize
+		 * it once you figure out the context ID for the work to be
+		 * measured
+		 */
+		DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID, UINT64_MAX,
+
+		/* OA unit configuration:
+		 * DRM_XE_OA_PROPERTY_SAMPLE_OA is no longer required for Gen12
+		 * because the OAR unit increments counters only for the
+		 * relevant context. No other parameters are needed since we do
+		 * not rely on the OA buffer anymore to normalize the counter
+		 * values.
+		 */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
+		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	struct intel_buf *buf;
+#define INVALID_CTX_ID 0xffffffff
+	uint32_t ctx_id = INVALID_CTX_ID;
+	uint32_t vm = 0;
+	uint32_t *report32;
+	size_t format_size_32;
+	struct oa_format format = get_oa_format(fmt);
+
+	/* Ensure perf_stream_paranoid is set to 1 by default */
+	write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
+
+	bops = buf_ops_create(drm_fd);
+	vm = xe_vm_create(drm_fd, 0, 0);
+	ctx_id = xe_exec_queue_create(drm_fd, vm, hwe, 0);
+	igt_assert_neq(ctx_id, INVALID_CTX_ID);
+	properties[3] = ctx_id;
+
+	ibb = intel_bb_create_with_context(drm_fd, ctx_id, vm, NULL, BATCH_SZ);
+	buf = intel_buf_create(bops, 4096, 1, 8, 64,
+			       I915_TILING_NONE, I915_COMPRESSION_NONE);
+
+	buf_map(drm_fd, buf, true);
+	memset(buf->ptr, 0x80, 4096);
+	intel_buf_unmap(buf);
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+        set_fd_flags(stream_fd, O_CLOEXEC);
+
+#define REPORT_ID 0xdeadbeef
+#define REPORT_OFFSET 0
+	emit_report_perf_count(ibb,
+			       buf,
+			       REPORT_OFFSET,
+			       REPORT_ID);
+	intel_bb_flush_render(ibb);
+	intel_bb_sync(ibb);
+
+	buf_map(drm_fd, buf, false);
+	report32 = buf->ptr;
+	format_size_32 = format.size >> 2;
+	dump_report(report32, format_size_32, "mi-rpc");
+
+	/* Sanity check reports
+	 * reportX_32[0]: report id passed with mi-rpc
+	 * reportX_32[1]: timestamp. NOTE: wraps around in ~6 minutes.
+	 *
+	 * reportX_32[format.b_off]: check if the entire report was filled.
+	 * B0 counter falls in the last 64 bytes of this report format.
+	 * Since reports are filled in 64 byte blocks, we should be able to
+	 * assure that the report was filled by checking the B0 counter. B0
+	 * counter is defined to be zero, so we can easily validate it.
+	 *
+	 * reportX_32[format_size_32]: outside report, make sure only the report
+	 * size amount of data was written.
+	 */
+	igt_assert_eq(report32[0], REPORT_ID);
+	igt_assert(oa_timestamp(report32, test_set->perf_oa_format));
+	igt_assert_neq(report32[format.b_off >> 2], 0x80808080);
+	igt_assert_eq(report32[format_size_32], 0x80808080);
+
+	intel_buf_unmap(buf);
+	intel_buf_destroy(buf);
+	intel_bb_destroy(ibb);
+	xe_exec_queue_destroy(drm_fd, ctx_id);
+	xe_vm_destroy(drm_fd, vm);
+	buf_ops_destroy(bops);
+	__perf_close(stream_fd);
+}
+
+static void
+emit_stall_timestamp_and_rpc(struct intel_bb *ibb,
+			     struct intel_buf *dst,
+			     int timestamp_offset,
+			     int report_dst_offset,
+			     uint32_t report_id)
+{
+	uint32_t pipe_ctl_flags = (PIPE_CONTROL_CS_STALL |
+				   PIPE_CONTROL_RENDER_TARGET_FLUSH |
+				   PIPE_CONTROL_WRITE_TIMESTAMP);
+
+	intel_bb_add_intel_buf(ibb, dst, true);
+	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL(6));
+	intel_bb_out(ibb, pipe_ctl_flags);
+	intel_bb_emit_reloc(ibb, dst->handle,
+			    I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+			    timestamp_offset, dst->addr.offset);
+	intel_bb_out(ibb, 0); /* imm lower */
+	intel_bb_out(ibb, 0); /* imm upper */
+
+	emit_report_perf_count(ibb, dst, report_dst_offset, report_id);
+}
+
+static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
+{
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t fmt = oar_unit_default_format();
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Have a random value here for the context id, but initialize
+		 * it once you figure out the context ID for the work to be
+		 * measured
+		 */
+		DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID, UINT64_MAX,
+
+		/* OA unit configuration:
+		 * DRM_XE_OA_PROPERTY_SAMPLE_OA is no longer required for Gen12
+		 * because the OAR unit increments counters only for the
+		 * relevant context. No other parameters are needed since we do
+		 * not rely on the OA buffer anymore to normalize the counter
+		 * values.
+		 */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
+		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	struct buf_ops *bops;
+	struct intel_bb *ibb0, *ibb1;
+	struct intel_buf src[3], dst[3], *dst_buf;
+	uint32_t context0_id, context1_id, vm = 0;
+	uint32_t *report0_32, *report1_32, *report2_32, *report3_32;
+	uint64_t timestamp0_64, timestamp1_64;
+	uint64_t delta_ts64, delta_oa32;
+	uint64_t delta_ts64_ns, delta_oa32_ns;
+	uint64_t delta_delta;
+	int width = 800;
+	int height = 600;
+#define INVALID_CTX_ID 0xffffffff
+	uint32_t ctx0_id = INVALID_CTX_ID;
+	uint32_t ctx1_id = INVALID_CTX_ID;
+	int ret;
+	struct accumulator accumulator = {
+		.format = fmt
+	};
+
+	bops = buf_ops_create(drm_fd);
+
+	for (int i = 0; i < ARRAY_SIZE(src); i++) {
+		scratch_buf_init(bops, &src[i], width, height, 0xff0000ff);
+		scratch_buf_init(bops, &dst[i], width, height, 0x00ff00ff);
+	}
+
+	vm = xe_vm_create(drm_fd, 0, 0);
+	context0_id = xe_exec_queue_create(drm_fd, vm, hwe, 0);
+	context1_id = xe_exec_queue_create(drm_fd, vm, hwe, 0);
+	ibb0 = intel_bb_create_with_context(drm_fd, context0_id, vm, NULL, BATCH_SZ);
+	ibb1 = intel_bb_create_with_context(drm_fd, context1_id, vm, NULL, BATCH_SZ);
+
+	igt_debug("submitting warm up render_copy\n");
+
+	/* Submit some early, unmeasured, work to the context we want */
+	render_copy(ibb0,
+		    &src[0], 0, 0, width, height,
+		    &dst[0], 0, 0);
+
+	/* Initialize the context parameter to the perf open ioctl here */
+	properties[3] = context0_id;
+
+	igt_debug("opening xe oa stream\n");
+	stream_fd = __perf_open(drm_fd, &param, false);
+        set_fd_flags(stream_fd, O_CLOEXEC);
+
+	dst_buf = intel_buf_create(bops, 4096, 1, 8, 64,
+				   I915_TILING_NONE,
+				   I915_COMPRESSION_NONE);
+
+	/* Set write domain to cpu briefly to fill the buffer with 80s */
+	buf_map(drm_fd, dst_buf, true /* write enable */);
+	memset(dst_buf->ptr, 0x80, 2048);
+	memset((uint8_t *) dst_buf->ptr + 2048, 0, 2048);
+	intel_buf_unmap(dst_buf);
+
+	/* Submit an mi-rpc to context0 before measurable work */
+#define BO_TIMESTAMP_OFFSET0 1024
+#define BO_REPORT_OFFSET0 0
+#define BO_REPORT_ID0 0xdeadbeef
+	emit_stall_timestamp_and_rpc(ibb0,
+				     dst_buf,
+				     BO_TIMESTAMP_OFFSET0,
+				     BO_REPORT_OFFSET0,
+				     BO_REPORT_ID0);
+	intel_bb_flush_render(ibb0);
+
+	/* Remove intel_buf from ibb0 added implicitly in rendercopy */
+	intel_bb_remove_intel_buf(ibb0, dst_buf);
+
+	/* This is the work/context that is measured for counter increments */
+	render_copy(ibb0,
+		    &src[0], 0, 0, width, height,
+		    &dst[0], 0, 0);
+	intel_bb_flush_render(ibb0);
+
+	/* Submit an mi-rpc to context1 before work
+	 *
+	 * On gen12, this measurement should just yield counters that are
+	 * all zeroes, since the counters will only increment for the
+	 * context passed to perf open ioctl
+	 */
+#define BO_TIMESTAMP_OFFSET2 1040
+#define BO_REPORT_OFFSET2 512
+#define BO_REPORT_ID2 0x00c0ffee
+	emit_stall_timestamp_and_rpc(ibb1,
+				     dst_buf,
+				     BO_TIMESTAMP_OFFSET2,
+				     BO_REPORT_OFFSET2,
+				     BO_REPORT_ID2);
+	intel_bb_flush_render(ibb1);
+
+	/* Submit two copies on the other context to avoid a false
+	 * positive in case the driver somehow ended up filtering for
+	 * context1
+	 */
+	render_copy(ibb1,
+		    &src[1], 0, 0, width, height,
+		    &dst[1], 0, 0);
+
+	render_copy(ibb1,
+		    &src[2], 0, 0, width, height,
+		    &dst[2], 0, 0);
+	intel_bb_flush_render(ibb1);
+
+	/* Submit an mi-rpc to context1 after all work */
+#define BO_TIMESTAMP_OFFSET3 1048
+#define BO_REPORT_OFFSET3 768
+#define BO_REPORT_ID3 0x01c0ffee
+	emit_stall_timestamp_and_rpc(ibb1,
+				     dst_buf,
+				     BO_TIMESTAMP_OFFSET3,
+				     BO_REPORT_OFFSET3,
+				     BO_REPORT_ID3);
+	intel_bb_flush_render(ibb1);
+
+	/* Remove intel_buf from ibb1 added implicitly in rendercopy */
+	intel_bb_remove_intel_buf(ibb1, dst_buf);
+
+	/* Submit an mi-rpc to context0 after all measurable work */
+#define BO_TIMESTAMP_OFFSET1 1032
+#define BO_REPORT_OFFSET1 256
+#define BO_REPORT_ID1 0xbeefbeef
+	emit_stall_timestamp_and_rpc(ibb0,
+				     dst_buf,
+				     BO_TIMESTAMP_OFFSET1,
+				     BO_REPORT_OFFSET1,
+				     BO_REPORT_ID1);
+	intel_bb_flush_render(ibb0);
+	intel_bb_sync(ibb0);
+	intel_bb_sync(ibb1);
+
+	buf_map(drm_fd, dst_buf, false);
+
+	/* Sanity check reports
+	 * reportX_32[0]: report id passed with mi-rpc
+	 * reportX_32[1]: timestamp
+	 * reportX_32[2]: context id
+	 *
+	 * report0_32: start of measurable work
+	 * report1_32: end of measurable work
+	 * report2_32: start of other work
+	 * report3_32: end of other work
+	 */
+	report0_32 = dst_buf->ptr;
+	igt_assert_eq(report0_32[0], 0xdeadbeef);
+	igt_assert(oa_timestamp(report0_32, fmt));
+	ctx0_id = report0_32[2];
+	igt_debug("MI_RPC(start) CTX ID: %u\n", ctx0_id);
+	dump_report(report0_32, 64, "report0_32");
+
+	report1_32 = report0_32 + 64;
+	igt_assert_eq(report1_32[0], 0xbeefbeef);
+	igt_assert(oa_timestamp(report1_32, fmt));
+	ctx1_id = report1_32[2];
+	igt_debug("CTX ID1: %u\n", ctx1_id);
+	dump_report(report1_32, 64, "report1_32");
+
+	/* Verify that counters in context1 are all zeroes */
+	report2_32 = report0_32 + 128;
+	igt_assert_eq(report2_32[0], 0x00c0ffee);
+	igt_assert(oa_timestamp(report2_32, fmt));
+	dump_report(report2_32, 64, "report2_32");
+	igt_assert_eq(0, memcmp(&report2_32[4],
+				(uint8_t *) dst_buf->ptr + 2048,
+				240));
+
+	report3_32 = report0_32 + 192;
+	igt_assert_eq(report3_32[0], 0x01c0ffee);
+	igt_assert(oa_timestamp(report3_32, fmt));
+	dump_report(report3_32, 64, "report3_32");
+	igt_assert_eq(0, memcmp(&report3_32[4],
+				(uint8_t *) dst_buf->ptr + 2048,
+				240));
+
+	/* Accumulate deltas for counters - A0, A21 and A26 */
+	memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
+	accumulate_reports(&accumulator, report0_32, report1_32);
+	igt_debug("total: A0 = %"PRIu64", A21 = %"PRIu64", A26 = %"PRIu64"\n",
+			accumulator.deltas[2 + 0],
+			accumulator.deltas[2 + 21],
+			accumulator.deltas[2 + 26]);
+
+	igt_debug("oa_timestamp32 0 = %"PRIu64"\n", oa_timestamp(report0_32, fmt));
+	igt_debug("oa_timestamp32 1 = %"PRIu64"\n", oa_timestamp(report1_32, fmt));
+	igt_debug("ctx_id 0 = %u\n", report0_32[2]);
+	igt_debug("ctx_id 1 = %u\n", report1_32[2]);
+
+	/* The delta as calculated via the PIPE_CONTROL timestamp or
+	 * the OA report timestamps should be almost identical but
+	 * allow a 500 nanoseconds margin.
+	 */
+	timestamp0_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET0);
+	timestamp1_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET1);
+
+	igt_debug("ts_timestamp64 0 = %"PRIu64"\n", timestamp0_64);
+	igt_debug("ts_timestamp64 1 = %"PRIu64"\n", timestamp1_64);
+
+	delta_ts64 = timestamp1_64 - timestamp0_64;
+	delta_oa32 = oa_timestamp_delta(report1_32, report0_32, fmt);
+
+	/* Sanity check that we can pass the delta to timebase_scale */
+	delta_oa32_ns = timebase_scale(delta_oa32);
+	delta_ts64_ns = cs_timebase_scale(delta_ts64);
+
+	igt_debug("oa32 delta = %"PRIu64", = %"PRIu64"ns\n",
+			delta_oa32, delta_oa32_ns);
+	igt_debug("ts64 delta = %"PRIu64", = %"PRIu64"ns\n",
+			delta_ts64, delta_ts64_ns);
+
+	delta_delta = delta_ts64_ns > delta_oa32_ns ?
+		      (delta_ts64_ns - delta_oa32_ns) :
+		      (delta_oa32_ns - delta_ts64_ns);
+	if (delta_delta > 500) {
+		igt_debug("delta_delta = %"PRIu64". exceeds margin, skipping..\n",
+			  delta_delta);
+		exit(EAGAIN);
+	}
+
+	igt_debug("n samples written = %"PRIu64"/%"PRIu64" (%ix%i)\n",
+		  accumulator.deltas[2 + 21],
+		  accumulator.deltas[2 + 26],
+		  width, height);
+	accumulator_print(&accumulator, "filtered");
+
+	/* Verify that the work actually happened by comparing the src
+	 * and dst buffers
+	 */
+	buf_map(drm_fd, &src[0], false);
+	buf_map(drm_fd, &dst[0], false);
+
+	ret = memcmp(src[0].ptr, dst[0].ptr, 4 * width * height);
+	intel_buf_unmap(&src[0]);
+	intel_buf_unmap(&dst[0]);
+
+	if (ret != 0) {
+		accumulator_print(&accumulator, "total");
+		exit(EAGAIN);
+	}
+
+	/* FIXME: can we deduce the presence of A26 from get_oa_format(fmt)? */
+	if (intel_graphics_ver(devid) >= IP_VER(20, 0))
+		goto skip_check;
+
+	/* Check that this test passed. The test measures the number of 2x2
+	 * samples written to the render target using the counter A26. For
+	 * OAR, this counter will only have increments relevant to this specific
+	 * context. The value equals the width * height of the rendered work.
+	 */
+	igt_assert_eq(accumulator.deltas[2 + 26], width * height);
+
+ skip_check:
+	/* Clean up */
+	for (int i = 0; i < ARRAY_SIZE(src); i++) {
+		intel_buf_close(bops, &src[i]);
+		intel_buf_close(bops, &dst[i]);
+	}
+
+	intel_buf_unmap(dst_buf);
+	intel_buf_destroy(dst_buf);
+	intel_bb_destroy(ibb0);
+	intel_bb_destroy(ibb1);
+	xe_exec_queue_destroy(drm_fd, context0_id);
+	xe_exec_queue_destroy(drm_fd, context1_id);
+	xe_vm_destroy(drm_fd, vm);
+	buf_ops_destroy(bops);
+	__perf_close(stream_fd);
+}
+
+/**
+ * SUBTEST: unprivileged-single-ctx-counters
+ * Description: A harder test for OAR/OAC using MI_REPORT_PERF_COUNT
+ */
+static void
+test_single_ctx_render_target_writes_a_counter(struct drm_xe_engine_class_instance *hwe)
+{
+	int child_ret;
+	struct igt_helper_process child = {};
+
+	/* Ensure perf_stream_paranoid is set to 1 by default */
+	write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
+
+	do {
+		igt_fork_helper(&child) {
+			/* A local device for local resources. */
+			drm_fd = drm_reopen_driver(drm_fd);
+
+			igt_drop_root();
+
+			single_ctx_helper(hwe);
+
+			drm_close_driver(drm_fd);
+		}
+		child_ret = igt_wait_helper(&child);
+		igt_assert(WEXITSTATUS(child_ret) == EAGAIN ||
+			   WEXITSTATUS(child_ret) == 0);
+	} while (WEXITSTATUS(child_ret) == EAGAIN);
+}
+
 static unsigned read_xe_module_ref(void)
 {
 	FILE *fp = fopen("/proc/modules", "r");
@@ -2926,6 +3607,26 @@ igt_main
 	igt_subtest("short-reads")
 		test_short_reads();
 
+	igt_subtest_group {
+		igt_subtest_with_dynamic("mi-rpc")
+			__for_one_hwe_in_oag(hwe)
+				test_mi_rpc(hwe);
+
+		igt_subtest_with_dynamic("oa-tlb-invalidate") {
+			igt_require(intel_graphics_ver(devid) <= IP_VER(12, 70) &&
+				    intel_graphics_ver(devid) != IP_VER(12, 60));
+			__for_one_hwe_in_oag(hwe)
+				test_oa_tlb_invalidate(hwe);
+		}
+
+		igt_subtest_with_dynamic("unprivileged-single-ctx-counters") {
+			igt_require_f(render_copy, "no render-copy function\n");
+			igt_require(intel_graphics_ver(devid) < IP_VER(20, 0));
+			__for_one_render_engine(hwe)
+				test_single_ctx_render_target_writes_a_counter(hwe);
+		}
+	}
+
 	igt_fixture {
 		/* leave sysctl options in their default state... */
 		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 09/14] tests/intel/xe_oa: Exclusive/concurrent access, rc6 and stress open close
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (7 preceding siblings ...)
  2024-07-01  2:53 ` [PATCH i-g-t 08/14] tests/intel/xe_oa: OAR/OAC tests Ashutosh Dixit
@ 2024-07-01  2:53 ` Ashutosh Dixit
  2024-07-01  2:53 ` [PATCH i-g-t 10/14] tests/intel/xe_oa: add remove OA config tests Ashutosh Dixit
                   ` (8 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:53 UTC (permalink / raw)
  To: igt-dev

Add the following tests:
* "oa-unit-exclusive-stream-sample-oa"
* "oa-unit-exclusive-stream-exec-q"
* "oa-unit-concurrent-oa-buffer-read"
* "rc6-disable"
* "stress-open-close"

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 264 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 264 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 8a28e054da..64805d884f 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -430,6 +430,23 @@ static struct drm_xe_engine_class_instance *oa_unit_engine(int fd, int n)
 	return hwe;
 }
 
+static struct drm_xe_oa_unit *nth_oa_unit(int fd, int n)
+{
+	struct drm_xe_query_oa_units *qoa = xe_oa_units(fd);
+	struct drm_xe_oa_unit *oau;
+	u8 *poau;
+
+	poau = (u8 *)&qoa->oa_units[0];
+	for (int i = 0; i < qoa->num_oa_units; i++) {
+		oau = (struct drm_xe_oa_unit *)poau;
+		if (i == n)
+			return oau;
+		poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
+	}
+
+	return NULL;
+}
+
 static char *
 pretty_print_oa_period(uint64_t oa_period_ns)
 {
@@ -517,6 +534,14 @@ write_u64_file(const char *path, uint64_t val)
 	fclose(f);
 }
 
+static unsigned long rc6_residency_ms(void)
+{
+	unsigned long value;
+
+	igt_assert(igt_sysfs_scanf(sysfs, "device/tile0/gt0/gtidle/idle_residency_ms", "%lu", &value) == 1);
+	return value;
+}
+
 static uint64_t
 read_report_ticks(const uint32_t *report, enum intel_xe_oa_format_name format)
 {
@@ -3370,6 +3395,95 @@ done:
 	return ref_count;
 }
 
+/**
+ * SUBTEST: rc6-disable
+ * Description: Check that opening an OA stream disables RC6
+ */
+static void
+test_rc6_disable(void)
+{
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		/* Include OA reports in samples */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	unsigned long rc6_start, rc6_end;
+
+	/* Verify rc6 is functional by measuring residency while idle */
+	rc6_start = rc6_residency_ms();
+	usleep(50000);
+	rc6_end = rc6_residency_ms();
+	igt_require(rc6_end != rc6_start);
+
+	/* While OA is active, we keep rc6 disabled so we don't lose metrics */
+	stream_fd = __perf_open(drm_fd, &param, false);
+
+	rc6_start = rc6_residency_ms();
+	usleep(50000);
+	rc6_end = rc6_residency_ms();
+	igt_assert_eq(rc6_end - rc6_start, 0);
+
+	__perf_close(stream_fd);
+
+	/* But once OA is closed, we expect the device to sleep again */
+	rc6_start = rc6_residency_ms();
+	usleep(50000);
+	rc6_end = rc6_residency_ms();
+	igt_assert_neq(rc6_end - rc6_start, 0);
+}
+
+/**
+ * SUBTEST: stress-open-close
+ * Description: Open/close OA streams in a tight loop
+ */
+static void
+test_stress_open_close(const struct drm_xe_engine_class_instance *hwe)
+{
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+
+	load_helper_init();
+	load_helper_run(HIGH);
+
+	igt_until_timeout(2) {
+		int oa_exponent = 5; /* 5 micro seconds */
+		uint64_t properties[] = {
+			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+			/* XXX: even without periodic sampling we have to
+			 * specify at least one sample layout property...
+			 */
+			DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+
+			/* OA unit configuration */
+			DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
+			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+			DRM_XE_OA_PROPERTY_OA_DISABLED, true,
+			DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+		};
+		struct intel_xe_oa_open_prop param = {
+			.num_properties = ARRAY_SIZE(properties) / 2,
+			.properties_ptr = to_user_pointer(properties),
+		};
+
+		stream_fd = __perf_open(drm_fd, &param, false);
+		__perf_close(stream_fd);
+	}
+
+	load_helper_stop();
+	load_helper_fini();
+}
+
 /**
  * SUBTEST: xe-ref-count
  * Description: Check that an open oa stream holds a reference on the xe module
@@ -3456,6 +3570,137 @@ test_sysctl_defaults(void)
 	igt_assert_eq(paranoid, 1);
 }
 
+/**
+ * SUBTEST: oa-unit-exclusive-stream-sample-oa
+ * Description: Check that only a single stream can be opened on an OA unit (with sampling)
+ *
+ * SUBTEST: oa-unit-exclusive-stream-exec-q
+ * Description: Check that only a single stream can be opened on an OA unit (for OAR/OAC)
+*/
+/*
+ * Test if OA buffer streams can be independently opened on OA unit. Once a user
+ * opens a stream, that oa unit is exclusive to the user, other users get -EBUSY on
+ * trying to open a stream.
+ */
+static void
+test_oa_unit_exclusive_stream(bool exponent)
+{
+	struct drm_xe_query_oa_units *qoa = xe_oa_units(drm_fd);
+	struct drm_xe_oa_unit *oau;
+	u8 *poau = (u8 *)&qoa->oa_units[0];
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(0),
+		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, 0,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	uint32_t *exec_q = calloc(qoa->num_oa_units, sizeof(u32));
+	uint32_t *perf_fd = calloc(qoa->num_oa_units, sizeof(u32));
+	u32 vm = xe_vm_create(drm_fd, 0, 0);
+	struct intel_xe_perf_metric_set *test_set;
+	uint32_t i;
+
+	/* for each oa unit, open one random perf stream with sample OA */
+	for (i = 0; i < qoa->num_oa_units; i++) {
+		struct drm_xe_engine_class_instance *hwe = oa_unit_engine(drm_fd, i);
+
+		oau = (struct drm_xe_oa_unit *)poau;
+		if (oau->oa_unit_type != DRM_XE_OA_UNIT_TYPE_OAG)
+			continue;
+		test_set = metric_set(hwe);
+
+		igt_debug("opening OA buffer with c:i %d:%d\n",
+			  hwe->engine_class, hwe->engine_instance);
+		exec_q[i] = xe_exec_queue_create(drm_fd, vm, hwe, 0);
+		if (!exponent) {
+			properties[10] = DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID;
+			properties[11] = exec_q[i];
+		}
+
+		properties[1] = oau->oa_unit_id;
+		properties[5] = test_set->perf_oa_metrics_set;
+		properties[7] = __ff(test_set->perf_oa_format);
+		properties[9] = hwe->engine_instance;
+		perf_fd[i] = intel_xe_perf_ioctl(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param);
+		igt_assert(perf_fd[i] >= 0);
+		poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
+	}
+
+	/* Xe KMD holds reference to the exec_q's so they shouldn't be really destroyed */
+	for (i = 0; i < qoa->num_oa_units; i++)
+		if (exec_q[i])
+			xe_exec_queue_destroy(drm_fd, exec_q[i]);
+
+	/* for each oa unit make sure no other streams can be opened */
+	poau = (u8 *)&qoa->oa_units[0];
+	for (i = 0; i < qoa->num_oa_units; i++) {
+		struct drm_xe_engine_class_instance *hwe = oa_unit_engine(drm_fd, i);
+		int err;
+
+		oau = (struct drm_xe_oa_unit *)poau;
+		if (oau->oa_unit_type != DRM_XE_OA_UNIT_TYPE_OAG)
+			continue;
+		test_set = metric_set(hwe);
+
+		igt_debug("try with exp with c:i %d:%d\n",
+			  hwe->engine_class, hwe->engine_instance);
+		/* case 1: concurrent access to OAG should fail */
+		properties[1] = oau->oa_unit_id;
+		properties[5] = test_set->perf_oa_metrics_set;
+		properties[7] = __ff(test_set->perf_oa_format);
+		properties[9] = hwe->engine_instance;
+		properties[10] = DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT;
+		properties[11] = oa_exp_1_millisec;
+		intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param, EBUSY);
+
+		/* case 2: concurrent access to non-OAG unit should fail */
+		igt_debug("try with exec_q with c:i %d:%d\n",
+			  hwe->engine_class, hwe->engine_instance);
+		exec_q[i] = xe_exec_queue_create(drm_fd, vm, hwe, 0);
+		properties[10] = DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID;
+		properties[11] = exec_q[i];
+		errno = 0;
+		err = intel_xe_perf_ioctl(drm_fd, DRM_XE_PERF_OP_STREAM_OPEN, &param);
+		igt_assert(err < 0);
+		igt_assert(errno == EBUSY || errno == ENODEV);
+		poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
+	}
+
+	for (i = 0; i < qoa->num_oa_units; i++) {
+		if (perf_fd[i])
+			close(perf_fd[i]);
+		if (exec_q[i])
+			xe_exec_queue_destroy(drm_fd, exec_q[i]);
+	}
+}
+
+/**
+ * SUBTEST: oa-unit-concurrent-oa-buffer-read
+ * Description: Test that we can read streams concurrently on all OA units
+ */
+static void
+test_oa_unit_concurrent_oa_buffer_read(void)
+{
+	struct drm_xe_query_oa_units *qoa = xe_oa_units(drm_fd);
+
+	igt_fork(child, qoa->num_oa_units) {
+		struct drm_xe_engine_class_instance *hwe = oa_unit_engine(drm_fd, child);
+
+		/* No OAM support yet */
+		if (nth_oa_unit(drm_fd, child)->oa_unit_type != DRM_XE_OA_UNIT_TYPE_OAG)
+			exit(0);
+
+		test_blocking(40 * 1000 * 1000, false, 5 * 1000 * 1000, hwe);
+	}
+	igt_waitchildren();
+}
+
 static const char *xe_engine_class_name(uint32_t engine_class)
 {
 	switch (engine_class) {
@@ -3627,6 +3872,25 @@ igt_main
 		}
 	}
 
+	igt_subtest_group {
+		igt_subtest("oa-unit-exclusive-stream-sample-oa")
+			test_oa_unit_exclusive_stream(true);
+
+		igt_subtest("oa-unit-exclusive-stream-exec-q")
+			test_oa_unit_exclusive_stream(false);
+
+		igt_subtest("oa-unit-concurrent-oa-buffer-read")
+			test_oa_unit_concurrent_oa_buffer_read();
+	}
+
+	igt_subtest("rc6-disable")
+		test_rc6_disable();
+
+	igt_subtest_with_dynamic("stress-open-close") {
+		__for_one_hwe_in_oag(hwe)
+			test_stress_open_close(hwe);
+	}
+
 	igt_fixture {
 		/* leave sysctl options in their default state... */
 		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 10/14] tests/intel/xe_oa: add remove OA config tests
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (8 preceding siblings ...)
  2024-07-01  2:53 ` [PATCH i-g-t 09/14] tests/intel/xe_oa: Exclusive/concurrent access, rc6 and stress open close Ashutosh Dixit
@ 2024-07-01  2:53 ` Ashutosh Dixit
  2024-07-01  2:53 ` [PATCH i-g-t 11/14] tests/intel/xe_oa: OA buffer mmap tests Ashutosh Dixit
                   ` (7 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:53 UTC (permalink / raw)
  To: igt-dev

Add the following tests:
	* "invalid-create-userspace-config"
	* "invalid-remove-userspace-config"
	* "create-destroy-userspace-config"
	* "whitelisted-registers-userspace-config"

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 333 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 333 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 64805d884f..cc0a09da1e 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -534,6 +534,12 @@ write_u64_file(const char *path, uint64_t val)
 	fclose(f);
 }
 
+static bool
+try_sysfs_read_u64(const char *path, uint64_t *val)
+{
+	return igt_sysfs_scanf(sysfs, path, "%"PRIu64, val) == 1;
+}
+
 static unsigned long rc6_residency_ms(void)
 {
 	unsigned long value;
@@ -3484,6 +3490,321 @@ test_stress_open_close(const struct drm_xe_engine_class_instance *hwe)
 	load_helper_fini();
 }
 
+static int __xe_oa_add_config(int fd, struct drm_xe_oa_config *config)
+{
+	int ret = intel_xe_perf_ioctl(fd, DRM_XE_PERF_OP_ADD_CONFIG, config);
+	if (ret < 0)
+		ret = -errno;
+	return ret;
+}
+
+static int xe_oa_add_config(int fd, struct drm_xe_oa_config *config)
+{
+	int config_id = __xe_oa_add_config(fd, config);
+
+	igt_debug("config_id=%i\n", config_id);
+	igt_assert(config_id > 0);
+
+	return config_id;
+}
+
+static void xe_oa_remove_config(int fd, uint64_t config_id)
+{
+	igt_assert_eq(intel_xe_perf_ioctl(fd, DRM_XE_PERF_OP_REMOVE_CONFIG, &config_id), 0);
+}
+
+static bool has_xe_oa_userspace_config(int fd)
+{
+	uint64_t config = 0;
+	int ret = intel_xe_perf_ioctl(fd, DRM_XE_PERF_OP_REMOVE_CONFIG, &config);
+	igt_assert_eq(ret, -1);
+
+	igt_debug("errno=%i\n", errno);
+
+	return errno != EINVAL;
+}
+
+#define SAMPLE_MUX_REG (intel_graphics_ver(devid) >= IP_VER(20, 0) ?	\
+			0x13000 /* PES* */ : 0x9888 /* NOA_WRITE */)
+
+/**
+ * SUBTEST: invalid-create-userspace-config
+ * Description: Test invalid configs are rejected
+ */
+static void
+test_invalid_create_userspace_config(void)
+{
+	struct drm_xe_oa_config config;
+	const char *uuid = "01234567-0123-0123-0123-0123456789ab";
+	const char *invalid_uuid = "blablabla-wrong";
+	uint32_t mux_regs[] = { SAMPLE_MUX_REG, 0x0 };
+	uint32_t invalid_mux_regs[] = { 0x12345678 /* invalid register */, 0x0 };
+
+	igt_require(has_xe_oa_userspace_config(drm_fd));
+
+	memset(&config, 0, sizeof(config));
+
+	/* invalid uuid */
+	strncpy(config.uuid, invalid_uuid, sizeof(config.uuid));
+	config.n_regs = 1;
+	config.regs_ptr = to_user_pointer(mux_regs);
+
+	igt_assert_eq(__xe_oa_add_config(drm_fd, &config), -EINVAL);
+
+	/* invalid mux_regs */
+	memcpy(config.uuid, uuid, sizeof(config.uuid));
+	config.n_regs = 1;
+	config.regs_ptr = to_user_pointer(invalid_mux_regs);
+
+	igt_assert_eq(__xe_oa_add_config(drm_fd, &config), -EINVAL);
+
+	/* empty config */
+	memcpy(config.uuid, uuid, sizeof(config.uuid));
+	config.n_regs = 0;
+	config.regs_ptr = to_user_pointer(mux_regs);
+
+	igt_assert_eq(__xe_oa_add_config(drm_fd, &config), -EINVAL);
+
+	/* empty config with null pointer */
+	memcpy(config.uuid, uuid, sizeof(config.uuid));
+	config.n_regs = 1;
+	config.regs_ptr = to_user_pointer(NULL);
+
+	igt_assert_eq(__xe_oa_add_config(drm_fd, &config), -EINVAL);
+
+	/* invalid pointer */
+	memcpy(config.uuid, uuid, sizeof(config.uuid));
+	config.n_regs = 42;
+	config.regs_ptr = to_user_pointer((void *) 0xDEADBEEF);
+
+	igt_assert_eq(__xe_oa_add_config(drm_fd, &config), -EFAULT);
+}
+
+/**
+ * SUBTEST: invalid-remove-userspace-config
+ * Description: Test invalid remove configs are rejected
+ */
+static void
+test_invalid_remove_userspace_config(void)
+{
+	struct drm_xe_oa_config config;
+	const char *uuid = "01234567-0123-0123-0123-0123456789ab";
+	uint32_t mux_regs[] = { SAMPLE_MUX_REG, 0x0 };
+	uint64_t config_id, wrong_config_id = 999999999;
+	char path[512];
+
+	igt_require(has_xe_oa_userspace_config(drm_fd));
+
+	snprintf(path, sizeof(path), "metrics/%s/id", uuid);
+
+	/* Destroy previous configuration if present */
+	if (try_sysfs_read_u64(path, &config_id))
+		xe_oa_remove_config(drm_fd, config_id);
+
+	memset(&config, 0, sizeof(config));
+
+	memcpy(config.uuid, uuid, sizeof(config.uuid));
+
+	config.n_regs = 1;
+	config.regs_ptr = to_user_pointer(mux_regs);
+
+	config_id = xe_oa_add_config(drm_fd, &config);
+
+	/* Removing configs without permissions should fail. */
+	igt_fork(child, 1) {
+		igt_drop_root();
+
+		intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_REMOVE_CONFIG, &config_id, EACCES);
+	}
+	igt_waitchildren();
+
+	/* Removing invalid config ID should fail. */
+	intel_xe_perf_ioctl_err(drm_fd, DRM_XE_PERF_OP_REMOVE_CONFIG, &wrong_config_id, ENOENT);
+
+	xe_oa_remove_config(drm_fd, config_id);
+}
+
+/**
+ * SUBTEST: create-destroy-userspace-config
+ * Description: Test add/remove OA configs
+ */
+static void
+test_create_destroy_userspace_config(void)
+{
+	struct drm_xe_oa_config config;
+	const char *uuid = "01234567-0123-0123-0123-0123456789ab";
+	uint32_t mux_regs[] = { SAMPLE_MUX_REG, 0x0 };
+	uint32_t regs[100];
+	int i;
+	uint64_t config_id;
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0, /* Filled later */
+
+		/* OA unit configuration */
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	char path[512];
+
+	igt_require(has_xe_oa_userspace_config(drm_fd));
+
+	snprintf(path, sizeof(path), "metrics/%s/id", uuid);
+
+	/* Destroy previous configuration if present */
+	if (try_sysfs_read_u64(path, &config_id))
+		xe_oa_remove_config(drm_fd, config_id);
+
+	memset(&config, 0, sizeof(config));
+	memcpy(config.uuid, uuid, sizeof(config.uuid));
+
+	regs[0] = mux_regs[0];
+	regs[1] = mux_regs[1];
+	/* Flex EU counters */
+	for (i = 1; i < ARRAY_SIZE(regs) / 2; i++) {
+		regs[i * 2] = 0xe458; /* EU_PERF_CNTL0 */
+		regs[i * 2 + 1] = 0x0;
+	}
+	config.regs_ptr = to_user_pointer(regs);
+	config.n_regs = ARRAY_SIZE(regs) / 2;
+
+	/* Creating configs without permissions shouldn't work. */
+	igt_fork(child, 1) {
+		igt_drop_root();
+
+		igt_assert_eq(__xe_oa_add_config(drm_fd, &config), -EACCES);
+	}
+	igt_waitchildren();
+
+	/* Create a new config */
+	config_id = xe_oa_add_config(drm_fd, &config);
+
+	/* Verify that adding the another config with the same uuid fails. */
+	igt_assert_eq(__xe_oa_add_config(drm_fd, &config), -EADDRINUSE);
+
+	/* Try to use the new config */
+	properties[3] = config_id;
+	stream_fd = __perf_open(drm_fd, &param, false);
+
+	/* Verify that destroying the config doesn't yield any error. */
+	xe_oa_remove_config(drm_fd, config_id);
+
+	/* Read the config to verify shouldn't raise any issue. */
+	config_id = xe_oa_add_config(drm_fd, &config);
+
+	__perf_close(stream_fd);
+
+	xe_oa_remove_config(drm_fd, config_id);
+}
+
+/**
+ * SUBTEST: whitelisted-registers-userspace-config
+ * Description: Test that an OA config constructed using whitelisted register works
+ */
+/* Registers required by userspace. This list should be maintained by
+ * the OA configs developers and agreed upon with kernel developers as
+ * some of the registers have bits used by the kernel (for workarounds
+ * for instance) and other bits that need to be set by the OA configs.
+ */
+static void
+test_whitelisted_registers_userspace_config(void)
+{
+	struct drm_xe_oa_config config;
+	const char *uuid = "01234567-0123-0123-0123-0123456789ab";
+	uint32_t regs[600];
+	uint32_t i;
+	uint32_t oa_start_trig1, oa_start_trig8;
+	uint32_t oa_report_trig1, oa_report_trig8;
+	uint64_t config_id;
+	char path[512];
+	int ret;
+	const uint32_t flex[] = {
+		0xe458,
+		0xe558,
+		0xe658,
+		0xe758,
+		0xe45c,
+		0xe55c,
+		0xe65c
+	};
+
+	igt_require(has_xe_oa_userspace_config(drm_fd));
+
+	snprintf(path, sizeof(path), "metrics/%s/id", uuid);
+
+	if (try_sysfs_read_u64(path, &config_id))
+		xe_oa_remove_config(drm_fd, config_id);
+
+	memset(&config, 0, sizeof(config));
+	memcpy(config.uuid, uuid, sizeof(config.uuid));
+
+	oa_start_trig1 = 0xd900;
+	oa_start_trig8 = 0xd91c;
+	oa_report_trig1 = 0xd920;
+	oa_report_trig8 = 0xd93c;
+
+	/* b_counters_regs: OASTARTTRIG[1-8] */
+	for (i = oa_start_trig1; i <= oa_start_trig8; i += 4) {
+		regs[config.n_regs * 2] = i;
+		regs[config.n_regs * 2 + 1] = 0;
+		config.n_regs++;
+	}
+	/* b_counters_regs: OAREPORTTRIG[1-8] */
+	for (i = oa_report_trig1; i <= oa_report_trig8; i += 4) {
+		regs[config.n_regs * 2] = i;
+		regs[config.n_regs * 2 + 1] = 0;
+		config.n_regs++;
+	}
+
+	/* Flex EU registers, only from Gen8+. */
+	for (i = 0; i < ARRAY_SIZE(flex); i++) {
+		regs[config.n_regs * 2] = flex[i];
+		regs[config.n_regs * 2 + 1] = 0;
+		config.n_regs++;
+	}
+
+	/* Mux registers (too many of them, just checking bounds) */
+	/* NOA_WRITE */
+	regs[config.n_regs * 2] = SAMPLE_MUX_REG;
+	regs[config.n_regs * 2 + 1] = 0;
+	config.n_regs++;
+
+	/* NOA_CONFIG */
+	/* Prior to Xe2 */
+	if (intel_graphics_ver(devid) < IP_VER(20, 0)) {
+		regs[config.n_regs * 2] = 0xD04;
+		regs[config.n_regs * 2 + 1] = 0;
+		config.n_regs++;
+		regs[config.n_regs * 2] = 0xD2C;
+		regs[config.n_regs * 2 + 1] = 0;
+		config.n_regs++;
+	}
+	/* Prior to MTLx */
+	if (intel_graphics_ver(devid) < IP_VER(12, 70)) {
+		/* WAIT_FOR_RC6_EXIT */
+		regs[config.n_regs * 2] = 0x20CC;
+		regs[config.n_regs * 2 + 1] = 0;
+		config.n_regs++;
+	}
+
+	config.regs_ptr = (uintptr_t) regs;
+
+	/* Create a new config */
+	ret = intel_xe_perf_ioctl(drm_fd, DRM_XE_PERF_OP_ADD_CONFIG, &config);
+	igt_assert(ret > 0); /* Config 0 should be used by the kernel */
+	config_id = ret;
+
+	xe_oa_remove_config(drm_fd, config_id);
+}
+
 /**
  * SUBTEST: xe-ref-count
  * Description: Check that an open oa stream holds a reference on the xe module
@@ -3891,6 +4212,18 @@ igt_main
 			test_stress_open_close(hwe);
 	}
 
+	igt_subtest("invalid-create-userspace-config")
+		test_invalid_create_userspace_config();
+
+	igt_subtest("invalid-remove-userspace-config")
+		test_invalid_remove_userspace_config();
+
+	igt_subtest("create-destroy-userspace-config")
+		test_create_destroy_userspace_config();
+
+	igt_subtest("whitelisted-registers-userspace-config")
+		test_whitelisted_registers_userspace_config();
+
 	igt_fixture {
 		/* leave sysctl options in their default state... */
 		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 11/14] tests/intel/xe_oa: OA buffer mmap tests
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (9 preceding siblings ...)
  2024-07-01  2:53 ` [PATCH i-g-t 10/14] tests/intel/xe_oa: add remove OA config tests Ashutosh Dixit
@ 2024-07-01  2:53 ` Ashutosh Dixit
  2024-07-01  2:53 ` [PATCH i-g-t 12/14] tests/intel/xe_oa: Register whitelisting and MMIO trigger tests Ashutosh Dixit
                   ` (6 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:53 UTC (permalink / raw)
  To: igt-dev

Add the following tests:
* "map-oa-buffer"
* "invalid-map-oa-buffer"
* "non-privileged-map-oa-buffer"
* "non-privileged-access-vaddr"
* "privileged-forked-access-vaddr"
* "closed-fd-and-unmapped-access"

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 251 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 251 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index cc0a09da1e..67d8701953 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -4022,6 +4022,231 @@ test_oa_unit_concurrent_oa_buffer_read(void)
 	igt_waitchildren();
 }
 
+static void *map_oa_buffer(u32 *size)
+{
+	void *vaddr = mmap(0, OA_BUFFER_SIZE, PROT_READ, MAP_PRIVATE, stream_fd, 0);
+
+	igt_assert(vaddr != NULL);
+	*size = OA_BUFFER_SIZE;
+	return vaddr;
+}
+
+static void invalid_param_map_oa_buffer(const struct drm_xe_engine_class_instance *hwe)
+{
+	void *oa_vaddr = NULL;
+
+	/* try a couple invalid mmaps */
+	/* bad prots */
+	oa_vaddr = mmap(0, OA_BUFFER_SIZE, PROT_WRITE, MAP_PRIVATE, stream_fd, 0);
+	igt_assert(oa_vaddr == MAP_FAILED);
+
+	oa_vaddr = mmap(0, OA_BUFFER_SIZE, PROT_EXEC, MAP_PRIVATE, stream_fd, 0);
+	igt_assert(oa_vaddr == MAP_FAILED);
+
+	/* bad MAPs */
+	oa_vaddr = mmap(0, OA_BUFFER_SIZE, PROT_READ, MAP_SHARED, stream_fd, 0);
+	igt_assert(oa_vaddr == MAP_FAILED);
+
+	/* bad size */
+	oa_vaddr = mmap(0, OA_BUFFER_SIZE + 1, PROT_READ, MAP_PRIVATE, stream_fd, 0);
+	igt_assert(oa_vaddr == MAP_FAILED);
+
+	/* do the right thing */
+	oa_vaddr = mmap(0, OA_BUFFER_SIZE, PROT_READ, MAP_PRIVATE, stream_fd, 0);
+	igt_assert(oa_vaddr != MAP_FAILED && oa_vaddr != NULL);
+
+	munmap(oa_vaddr, OA_BUFFER_SIZE);
+}
+
+static void unprivileged_try_to_map_oa_buffer(void)
+{
+	void *oa_vaddr;
+
+	oa_vaddr = mmap(0, OA_BUFFER_SIZE, PROT_READ, MAP_PRIVATE, stream_fd, 0);
+	igt_assert(oa_vaddr == MAP_FAILED);
+	igt_assert_eq(errno, EACCES);
+}
+
+static void unprivileged_map_oa_buffer(const struct drm_xe_engine_class_instance *hwe)
+{
+	igt_fork(child, 1) {
+		igt_drop_root();
+		unprivileged_try_to_map_oa_buffer();
+	}
+	igt_waitchildren();
+}
+
+static jmp_buf jmp;
+static void __attribute__((noreturn)) sigtrap(int sig)
+{
+	siglongjmp(jmp, sig);
+}
+
+static void try_invalid_access(void *vaddr)
+{
+	sighandler_t old_sigsegv;
+	uint32_t dummy;
+
+	old_sigsegv = signal(SIGSEGV, sigtrap);
+	switch (sigsetjmp(jmp, SIGSEGV)) {
+	case SIGSEGV:
+		break;
+	case 0:
+		dummy = READ_ONCE(*((uint32_t *)vaddr + 1));
+		(void) dummy;
+	default:
+		igt_assert(!"reached");
+		break;
+	}
+	signal(SIGSEGV, old_sigsegv);
+}
+
+static void map_oa_buffer_unprivilege_access(const struct drm_xe_engine_class_instance *hwe)
+{
+	void *vaddr;
+	uint32_t size;
+
+	vaddr = map_oa_buffer(&size);
+
+	igt_fork(child, 1) {
+		igt_drop_root();
+		try_invalid_access(vaddr);
+	}
+	igt_waitchildren();
+
+	munmap(vaddr, size);
+}
+
+static void map_oa_buffer_forked_access(const struct drm_xe_engine_class_instance *hwe)
+{
+	void *vaddr;
+	uint32_t size;
+
+	vaddr = map_oa_buffer(&size);
+
+	igt_fork(child, 1) {
+		try_invalid_access(vaddr);
+	}
+	igt_waitchildren();
+
+	munmap(vaddr, size);
+}
+
+static void check_reports(void *oa_vaddr, uint32_t oa_size,
+			  const struct drm_xe_engine_class_instance *hwe)
+{
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t fmt = test_set->perf_oa_format;
+	struct oa_format format = get_oa_format(fmt);
+	size_t report_words = format.size >> 2;
+	uint32_t *reports;
+	uint32_t timer_reports = 0;
+
+	for (reports = (uint32_t *)oa_vaddr;
+	     timer_reports < 20 && reports[0] && oa_timestamp(reports, fmt);
+	     reports += report_words) {
+		if (!oa_report_is_periodic(oa_exp_1_millisec, reports))
+			continue;
+
+		timer_reports++;
+		if (timer_reports >= 3)
+			sanity_check_reports(reports - 2 * report_words,
+					     reports - report_words, fmt);
+	}
+
+	igt_assert(timer_reports >= 3);
+}
+
+static void check_reports_from_mapped_buffer(const struct drm_xe_engine_class_instance *hwe)
+{
+	void *vaddr;
+	uint32_t size;
+	uint32_t period_us = oa_exponent_to_ns(oa_exp_1_millisec) / 1000;
+
+	vaddr = map_oa_buffer(&size);
+
+	/* wait for approx 100 reports */
+	usleep(100 * period_us);
+	check_reports(vaddr, size, hwe);
+
+	munmap(vaddr, size);
+}
+
+/**
+ * SUBTEST: closed-fd-and-unmapped-access
+ * Description: Unmap buffer, close fd and try to access
+ */
+static void closed_fd_and_unmapped_access(const struct drm_xe_engine_class_instance *hwe)
+{
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	void *vaddr;
+	uint32_t size;
+	uint32_t period_us = oa_exponent_to_ns(oa_exp_1_millisec) / 1000;
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+	vaddr = map_oa_buffer(&size);
+
+	usleep(100 * period_us);
+	check_reports(vaddr, size, hwe);
+
+	munmap(vaddr, size);
+	__perf_close(stream_fd);
+
+	try_invalid_access(vaddr);
+}
+
+/**
+ * SUBTEST: map-oa-buffer
+ * Description: Verify mapping of oa buffer
+ *
+ * SUBTEST: invalid-map-oa-buffer
+ * Description: Verify invalid mappings of oa buffer
+ *
+ * SUBTEST: non-privileged-map-oa-buffer
+ * Description: Verify if non-privileged user can map oa buffer
+ *
+ * SUBTEST: non-privileged-access-vaddr
+ * Description: Verify if non-privileged user can map oa buffer
+ *
+ * SUBTEST: privileged-forked-access-vaddr
+ * Description: Verify that forked access to mapped buffer fails
+ */
+typedef void (*map_oa_buffer_test_t)(const struct drm_xe_engine_class_instance *hwe);
+static void test_mapped_oa_buffer(map_oa_buffer_test_t test_with_fd_open,
+				  const struct drm_xe_engine_class_instance *hwe)
+{
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+
+	igt_assert(test_with_fd_open);
+	test_with_fd_open(hwe);
+
+	__perf_close(stream_fd);
+}
+
 static const char *xe_engine_class_name(uint32_t engine_class)
 {
 	switch (engine_class) {
@@ -4224,6 +4449,32 @@ igt_main
 	igt_subtest("whitelisted-registers-userspace-config")
 		test_whitelisted_registers_userspace_config();
 
+	igt_subtest_group {
+		igt_subtest_with_dynamic("map-oa-buffer")
+			__for_one_hwe_in_oag(hwe)
+				test_mapped_oa_buffer(check_reports_from_mapped_buffer, hwe);
+
+		igt_subtest_with_dynamic("invalid-map-oa-buffer")
+			__for_one_hwe_in_oag(hwe)
+				test_mapped_oa_buffer(invalid_param_map_oa_buffer, hwe);
+
+		igt_subtest_with_dynamic("non-privileged-map-oa-buffer")
+			__for_one_hwe_in_oag(hwe)
+				test_mapped_oa_buffer(unprivileged_map_oa_buffer, hwe);
+
+		igt_subtest_with_dynamic("non-privileged-access-vaddr")
+			__for_one_hwe_in_oag(hwe)
+				test_mapped_oa_buffer(map_oa_buffer_unprivilege_access, hwe);
+
+		igt_subtest_with_dynamic("privileged-forked-access-vaddr")
+			__for_one_hwe_in_oag(hwe)
+				test_mapped_oa_buffer(map_oa_buffer_forked_access, hwe);
+
+		igt_subtest_with_dynamic("closed-fd-and-unmapped-access")
+			__for_one_hwe_in_oag(hwe)
+				closed_fd_and_unmapped_access(hwe);
+	}
+
 	igt_fixture {
 		/* leave sysctl options in their default state... */
 		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 12/14] tests/intel/xe_oa: Register whitelisting and MMIO trigger tests
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (10 preceding siblings ...)
  2024-07-01  2:53 ` [PATCH i-g-t 11/14] tests/intel/xe_oa: OA buffer mmap tests Ashutosh Dixit
@ 2024-07-01  2:53 ` Ashutosh Dixit
  2024-07-01  2:53 ` [PATCH i-g-t 13/14] tests/intel/xe_oa: Drop "xe-ref-count" subtest Ashutosh Dixit
                   ` (5 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:53 UTC (permalink / raw)
  To: igt-dev

Add the following tests:
	* "oa-regs-whitelisted"
	* "mmio-triggered-reports"

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 327 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 327 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 67d8701953..965ea05d9a 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -3805,6 +3805,317 @@ test_whitelisted_registers_userspace_config(void)
 	xe_oa_remove_config(drm_fd, config_id);
 }
 
+#define OAG_OASTATUS (0xdafc)
+#define OAG_MMIOTRIGGER (0xdb1c)
+
+static const uint32_t oa_wl[] = {
+	OAG_MMIOTRIGGER,
+	OAG_OASTATUS,
+};
+
+static const uint32_t nonpriv_slot_offsets[] = {
+	0x4d0, 0x4d4, 0x4d8, 0x4dc, 0x4e0, 0x4e4, 0x4e8, 0x4ec,
+	0x4f0, 0x4f4, 0x4f8, 0x4fc, 0x010, 0x014, 0x018, 0x01c,
+	0x1e0, 0x1e4, 0x1e8, 0x1ec,
+};
+
+struct test_perf {
+	const uint32_t *slots;
+	uint32_t num_slots;
+	const uint32_t *wl;
+	uint32_t num_wl;
+} perf;
+
+#define HAS_OA_MMIO_TRIGGER(__d) \
+	(IS_DG2(__d) || IS_PONTEVECCHIO(__d) || IS_METEORLAKE(__d) || \
+	 intel_graphics_ver(devid) >= IP_VER(20, 0))
+
+static void perf_init_whitelist(void)
+{
+	perf.slots = nonpriv_slot_offsets;
+	perf.num_slots = 20;
+	perf.wl = oa_wl;
+	perf.num_wl = ARRAY_SIZE(oa_wl);
+}
+
+static void
+emit_oa_reg_read(struct intel_bb *ibb, struct intel_buf *dst, uint32_t offset,
+		 uint32_t reg)
+{
+	intel_bb_add_intel_buf(ibb, dst, true);
+
+	intel_bb_out(ibb, MI_STORE_REGISTER_MEM | 2);
+	intel_bb_out(ibb, reg);
+	intel_bb_emit_reloc(ibb, dst->handle,
+			    I915_GEM_DOMAIN_INSTRUCTION,
+			    I915_GEM_DOMAIN_INSTRUCTION,
+			    offset, dst->addr.offset);
+	intel_bb_out(ibb, lower_32_bits(offset));
+	intel_bb_out(ibb, upper_32_bits(offset));
+}
+
+static void
+emit_mmio_triggered_report(struct intel_bb *ibb, uint32_t value)
+{
+	intel_bb_out(ibb, MI_LOAD_REGISTER_IMM(1));
+	intel_bb_out(ibb, OAG_MMIOTRIGGER);
+	intel_bb_out(ibb, value);
+}
+
+static void dump_whitelist(uint32_t mmio_base, const char *msg)
+{
+	int i;
+
+	igt_debug("%s\n", msg);
+
+	for (i = 0; i < perf.num_slots; i++)
+		igt_debug("FORCE_TO_NON_PRIV_%02d = %08x\n",
+			  i, intel_register_read(&mmio_data,
+						 mmio_base + perf.slots[i]));
+}
+
+static bool in_whitelist(uint32_t mmio_base, uint32_t reg)
+{
+	int i;
+
+	if (reg & MMIO_BASE_OFFSET)
+		reg = (reg & ~MMIO_BASE_OFFSET) + mmio_base;
+
+	for (i = 0; i < perf.num_slots; i++) {
+		uint32_t fpriv = intel_register_read(&mmio_data,
+						     mmio_base + perf.slots[i]);
+
+		if ((fpriv & RING_FORCE_TO_NONPRIV_ADDRESS_MASK) == reg)
+			return true;
+	}
+
+	return false;
+}
+
+static void oa_regs_in_whitelist(uint32_t mmio_base, bool are_present)
+{
+	int i;
+
+	if (are_present) {
+		for (i = 0; i < perf.num_wl; i++)
+			igt_assert(in_whitelist(mmio_base, perf.wl[i]));
+	} else {
+		for (i = 0; i < perf.num_wl; i++)
+			igt_assert(!in_whitelist(mmio_base, perf.wl[i]));
+	}
+}
+
+static u32 oa_get_mmio_base(const struct drm_xe_engine_class_instance *hwe)
+{
+	u32 mmio_base = 0x2000;
+
+	switch (hwe->engine_class) {
+	case DRM_XE_ENGINE_CLASS_RENDER:
+		mmio_base = 0x2000;
+		break;
+	case DRM_XE_ENGINE_CLASS_COMPUTE:
+		switch (hwe->engine_instance) {
+		case 0:
+			mmio_base = 0x1a000;
+			break;
+		case 1:
+			mmio_base = 0x1c000;
+			break;
+		case 2:
+			mmio_base = 0x1e000;
+			break;
+		case 3:
+			mmio_base = 0x26000;
+			break;
+		}
+	}
+
+	return mmio_base;
+}
+
+/**
+ * SUBTEST: oa-regs-whitelisted
+ * Description: Verify that OA registers are whitelisted
+ */
+static void test_oa_regs_whitelist(const struct drm_xe_engine_class_instance *hwe)
+{
+	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = sizeof(properties) / 16,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	// uint32_t mmio_base = gem_engine_mmio_base(drm_fd, e->name);
+	u32 mmio_base;
+
+	/* FIXME: Add support for OAM whitelist testing */
+	if (hwe->engine_class != DRM_XE_ENGINE_CLASS_RENDER &&
+	    hwe->engine_class != DRM_XE_ENGINE_CLASS_COMPUTE)
+		return;
+
+	mmio_base = oa_get_mmio_base(hwe);
+
+	intel_register_access_init(&mmio_data,
+				   igt_device_get_pci_device(drm_fd),
+				   0, drm_fd);
+	stream_fd = __perf_open(drm_fd, &param, false);
+
+	dump_whitelist(mmio_base, "oa whitelisted");
+
+	oa_regs_in_whitelist(mmio_base, true);
+
+	__perf_close(stream_fd);
+
+	dump_whitelist(mmio_base, "oa remove whitelist");
+
+	/*
+	 * after perf close, check that registers are removed from the nonpriv
+	 * slots
+	 * FIXME if needed: currently regs remain added forever
+	 */
+	// oa_regs_in_whitelist(mmio_base, false);
+
+	intel_register_access_fini(&mmio_data);
+}
+
+static void
+__test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
+{
+	struct intel_xe_perf_metric_set *test_set = default_test_set;
+	int oa_exponent = max_oa_exponent_for_period_lte(2 * NSEC_PER_SEC);
+	uint64_t properties[] = {
+		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
+		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+	};
+	struct intel_xe_oa_open_prop param = {
+		.num_properties = sizeof(properties) / 16,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	size_t format_size = get_oa_format(test_set->perf_oa_format).size;
+	uint32_t oa_buffer, offset_tail1, offset_tail2;
+	struct intel_buf src, dst, *dst_buf;
+	uint32_t mmio_triggered_reports = 0;
+	uint32_t *start, *end;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t context, vm;
+	int height = 600;
+	int width = 800;
+	uint8_t *buf;
+
+	bops = buf_ops_create(drm_fd);
+
+	dst_buf = intel_buf_create(bops, 4096, 1, 8, 64,
+				   I915_TILING_NONE,
+				   I915_COMPRESSION_NONE);
+	buf_map(drm_fd, dst_buf, true);
+	memset(dst_buf->ptr, 0, 4096);
+	intel_buf_unmap(dst_buf);
+
+	scratch_buf_init(bops, &src, width, height, 0xff0000ff);
+	scratch_buf_init(bops, &dst, width, height, 0x00ff00ff);
+
+	vm = xe_vm_create(drm_fd, 0, 0);
+	context = xe_exec_queue_create(drm_fd, vm, hwe, 0);
+	igt_assert(context);
+	ibb = intel_bb_create_with_context(drm_fd, context, vm, NULL, BATCH_SZ);
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+        set_fd_flags(stream_fd, O_CLOEXEC);
+
+	buf = mmap(0, OA_BUFFER_SIZE, PROT_READ, MAP_PRIVATE, stream_fd, 0);
+	igt_assert(buf != NULL);
+
+	emit_oa_reg_read(ibb, dst_buf, 0, OAG_OABUFFER);
+	emit_oa_reg_read(ibb, dst_buf, 4, OAG_OATAILPTR);
+	emit_mmio_triggered_report(ibb, 0xc0ffee11);
+
+	if (render_copy)
+		render_copy(ibb,
+			    &src, 0, 0, width, height,
+			    &dst, 0, 0);
+
+	emit_mmio_triggered_report(ibb, 0xc0ffee22);
+
+	emit_oa_reg_read(ibb, dst_buf, 8, OAG_OATAILPTR);
+
+	intel_bb_flush_render(ibb);
+	intel_bb_sync(ibb);
+
+	buf_map(drm_fd, dst_buf, false);
+
+	oa_buffer = dst_buf->ptr[0] & OAG_OATAILPTR_MASK;
+	offset_tail1 = (dst_buf->ptr[1] & OAG_OATAILPTR_MASK) - oa_buffer;
+	offset_tail2 = (dst_buf->ptr[2] & OAG_OATAILPTR_MASK) - oa_buffer;
+
+	igt_debug("oa_buffer = %08x, tail1 = %08x, tail2 = %08x\n",
+		  oa_buffer, offset_tail1, offset_tail2);
+
+	start = (uint32_t *)(buf + offset_tail1);
+	end = (uint32_t *)(buf + offset_tail2);
+	while (start < end) {
+		if (!report_reason(start))
+			mmio_triggered_reports++;
+
+		if (get_oa_format(test_set->perf_oa_format).report_hdr_64bit) {
+			u64 *start64 = (u64 *)start;
+
+			igt_debug("hdr: %016lx %016lx %016lx %016lx\n",
+				  start64[0], start64[1], start64[2], start64[3]);
+		} else {
+			igt_debug("hdr: %08x %08x %08x %08x\n",
+				  start[0], start[1], start[2], start[3]);
+		}
+
+		start += format_size / 4;
+	}
+
+	igt_assert_eq(mmio_triggered_reports, 2);
+
+	munmap(buf, OA_BUFFER_SIZE);
+	intel_buf_close(bops, &src);
+	intel_buf_close(bops, &dst);
+	intel_buf_unmap(dst_buf);
+	intel_buf_destroy(dst_buf);
+	intel_bb_destroy(ibb);
+	xe_exec_queue_destroy(drm_fd, context);
+	xe_vm_destroy(drm_fd, vm);
+	buf_ops_destroy(bops);
+	__perf_close(stream_fd);
+}
+
+/**
+ * SUBTEST: mmio-triggered-reports
+ * Description: Test MMIO trigger functionality
+ */
+static void
+test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
+{
+	struct igt_helper_process child = {};
+	int ret;
+
+	write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 0);
+	igt_fork_helper(&child) {
+		igt_drop_root();
+
+		__test_mmio_triggered_reports(hwe);
+	}
+	ret = igt_wait_helper(&child);
+	write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
+
+	igt_assert(WEXITSTATUS(ret) == EAGAIN ||
+		   WEXITSTATUS(ret) == 0);
+}
+
 /**
  * SUBTEST: xe-ref-count
  * Description: Check that an open oa stream holds a reference on the xe module
@@ -4475,6 +4786,22 @@ igt_main
 				closed_fd_and_unmapped_access(hwe);
 	}
 
+	igt_subtest_group {
+		igt_fixture {
+			perf_init_whitelist();
+		}
+
+		igt_subtest_with_dynamic("oa-regs-whitelisted")
+			__for_one_hwe_in_oag(hwe)
+				test_oa_regs_whitelist(hwe);
+
+		igt_subtest_with_dynamic("mmio-triggered-reports") {
+			igt_require(HAS_OA_MMIO_TRIGGER(devid));
+			__for_one_hwe_in_oag(hwe)
+				test_mmio_triggered_reports(hwe);
+		}
+	}
+
 	igt_fixture {
 		/* leave sysctl options in their default state... */
 		write_u64_file("/proc/sys/dev/xe/perf_stream_paranoid", 1);
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 13/14] tests/intel/xe_oa: Drop "xe-ref-count" subtest
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (11 preceding siblings ...)
  2024-07-01  2:53 ` [PATCH i-g-t 12/14] tests/intel/xe_oa: Register whitelisting and MMIO trigger tests Ashutosh Dixit
@ 2024-07-01  2:53 ` Ashutosh Dixit
  2024-07-01 19:53   ` Umesh Nerlige Ramappa
  2024-07-01  2:53 ` [PATCH i-g-t 14/14] HAX: Add Xe OA tests to xe-fast-feedback.testlist Ashutosh Dixit
                   ` (4 subsequent siblings)
  17 siblings, 1 reply; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:53 UTC (permalink / raw)
  To: igt-dev

Sometime other modules (such as those for child devices) take or drop
references on the xe module. This results in "xe-ref-count" subtest unable
to accurately predict what the module refcount should be, resulting in
frequent false positives in the test.

Drop the test till we are able to devise a robust method to predict xe
module refcount.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/intel/xe_oa.c | 107 --------------------------------------------
 1 file changed, 107 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 965ea05d9a..9d4402d9bf 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -3371,36 +3371,6 @@ test_single_ctx_render_target_writes_a_counter(struct drm_xe_engine_class_instan
 	} while (WEXITSTATUS(child_ret) == EAGAIN);
 }
 
-static unsigned read_xe_module_ref(void)
-{
-	FILE *fp = fopen("/proc/modules", "r");
-	char *line = NULL;
-	size_t line_buf_size = 0;
-	int len = 0;
-	unsigned ref_count;
-	char mod[8];
-	int modn = 3;
-
-	igt_assert(fp);
-
-	strcpy(mod, "xe ");
-	while ((len = getline(&line, &line_buf_size, fp)) > 0) {
-		if (strncmp(line, mod, modn) == 0) {
-			unsigned long mem;
-			int ret = sscanf(line + 5, "%lu %u", &mem, &ref_count);
-			igt_assert(ret == 2);
-			goto done;
-		}
-	}
-
-	igt_assert(!"reached");
-
-done:
-	free(line);
-	fclose(fp);
-	return ref_count;
-}
-
 /**
  * SUBTEST: rc6-disable
  * Description: Check that opening an OA stream disables RC6
@@ -4116,80 +4086,6 @@ test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
 		   WEXITSTATUS(ret) == 0);
 }
 
-/**
- * SUBTEST: xe-ref-count
- * Description: Check that an open oa stream holds a reference on the xe module
- */
-static void
-test_xe_ref_count(void)
-{
-	uint64_t properties[] = {
-		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
-
-		/* Include OA reports in samples */
-		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
-
-		/* OA unit configuration */
-		DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0 /* updated below */,
-		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(0), /* update below */
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, 0, /* update below */
-	};
-	struct intel_xe_oa_open_prop param = {
-		.num_properties = ARRAY_SIZE(properties) / 2,
-		.properties_ptr = to_user_pointer(properties),
-	};
-	unsigned baseline, ref_count0, ref_count1;
-	uint32_t oa_report0[64];
-	uint32_t oa_report1[64];
-
-	/* This should be the first test before the first fixture so no drm_fd
-	 * should have been opened so far...
-	 */
-	igt_assert_eq(drm_fd, -1);
-
-	baseline = read_xe_module_ref();
-	igt_debug("baseline ref count (drm fd closed) = %u\n", baseline);
-
-	drm_fd = __drm_open_driver(DRIVER_XE);
-	if (is_xe_device(drm_fd))
-		xe_device_get(drm_fd);
-	devid = intel_get_drm_devid(drm_fd);
-	sysfs = igt_sysfs_open(drm_fd);
-
-	/* Note: these global variables are only initialized after calling
-	 * init_sys_info()...
-	 */
-	igt_require(init_sys_info());
-	properties[5] = default_test_set->perf_oa_metrics_set;
-	properties[7] = __ff(default_test_set->perf_oa_format);
-	properties[9] = oa_exp_1_millisec;
-
-	ref_count0 = read_xe_module_ref();
-	igt_debug("initial ref count with drm_fd open = %u\n", ref_count0);
-
-	stream_fd = __perf_open(drm_fd, &param, false);
-        set_fd_flags(stream_fd, O_CLOEXEC);
-	ref_count1 = read_xe_module_ref();
-	igt_debug("ref count after opening oa stream = %u\n", ref_count1);
-
-	drm_close_driver(drm_fd);
-	close(sysfs);
-	drm_fd = -1;
-	sysfs = -1;
-	ref_count0 = read_xe_module_ref();
-	igt_debug("ref count after closing drm fd = %u\n", ref_count0);
-
-	read_2_oa_reports(default_test_set->perf_oa_format,
-			  oa_exp_1_millisec,
-			  oa_report0,
-			  oa_report1,
-			  false); /* not just timer reports */
-
-	__perf_close(stream_fd);
-	ref_count0 = read_xe_module_ref();
-	igt_debug("ref count after closing oa stream fd = %u\n", ref_count0);
-}
-
 /**
  * SUBTEST: sysctl-defaults
  * Description: Test that perf_stream_paranoid sysctl exists
@@ -4621,9 +4517,6 @@ igt_main
 		igt_require(!stat("/proc/sys/dev/xe/perf_stream_paranoid", &sb));
 	}
 
-	igt_subtest("xe-ref-count")
-		test_xe_ref_count();
-
 	igt_subtest("sysctl-defaults")
 		test_sysctl_defaults();
 
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* Re: [PATCH i-g-t 13/14] tests/intel/xe_oa: Drop "xe-ref-count" subtest
  2024-07-01  2:53 ` [PATCH i-g-t 13/14] tests/intel/xe_oa: Drop "xe-ref-count" subtest Ashutosh Dixit
@ 2024-07-01 19:53   ` Umesh Nerlige Ramappa
  0 siblings, 0 replies; 26+ messages in thread
From: Umesh Nerlige Ramappa @ 2024-07-01 19:53 UTC (permalink / raw)
  To: Ashutosh Dixit; +Cc: igt-dev

On Sun, Jun 30, 2024 at 07:53:08PM -0700, Ashutosh Dixit wrote:
>Sometime other modules (such as those for child devices) take or drop
>references on the xe module. This results in "xe-ref-count" subtest unable
>to accurately predict what the module refcount should be, resulting in
>frequent false positives in the test.
>
>Drop the test till we are able to devise a robust method to predict xe
>module refcount.
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

>---
> tests/intel/xe_oa.c | 107 --------------------------------------------
> 1 file changed, 107 deletions(-)
>
>diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>index 965ea05d9a..9d4402d9bf 100644
>--- a/tests/intel/xe_oa.c
>+++ b/tests/intel/xe_oa.c
>@@ -3371,36 +3371,6 @@ test_single_ctx_render_target_writes_a_counter(struct drm_xe_engine_class_instan
> 	} while (WEXITSTATUS(child_ret) == EAGAIN);
> }
>
>-static unsigned read_xe_module_ref(void)
>-{
>-	FILE *fp = fopen("/proc/modules", "r");
>-	char *line = NULL;
>-	size_t line_buf_size = 0;
>-	int len = 0;
>-	unsigned ref_count;
>-	char mod[8];
>-	int modn = 3;
>-
>-	igt_assert(fp);
>-
>-	strcpy(mod, "xe ");
>-	while ((len = getline(&line, &line_buf_size, fp)) > 0) {
>-		if (strncmp(line, mod, modn) == 0) {
>-			unsigned long mem;
>-			int ret = sscanf(line + 5, "%lu %u", &mem, &ref_count);
>-			igt_assert(ret == 2);
>-			goto done;
>-		}
>-	}
>-
>-	igt_assert(!"reached");
>-
>-done:
>-	free(line);
>-	fclose(fp);
>-	return ref_count;
>-}
>-
> /**
>  * SUBTEST: rc6-disable
>  * Description: Check that opening an OA stream disables RC6
>@@ -4116,80 +4086,6 @@ test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
> 		   WEXITSTATUS(ret) == 0);
> }
>
>-/**
>- * SUBTEST: xe-ref-count
>- * Description: Check that an open oa stream holds a reference on the xe module
>- */
>-static void
>-test_xe_ref_count(void)
>-{
>-	uint64_t properties[] = {
>-		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>-
>-		/* Include OA reports in samples */
>-		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
>-
>-		/* OA unit configuration */
>-		DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0 /* updated below */,
>-		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(0), /* update below */
>-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, 0, /* update below */
>-	};
>-	struct intel_xe_oa_open_prop param = {
>-		.num_properties = ARRAY_SIZE(properties) / 2,
>-		.properties_ptr = to_user_pointer(properties),
>-	};
>-	unsigned baseline, ref_count0, ref_count1;
>-	uint32_t oa_report0[64];
>-	uint32_t oa_report1[64];
>-
>-	/* This should be the first test before the first fixture so no drm_fd
>-	 * should have been opened so far...
>-	 */
>-	igt_assert_eq(drm_fd, -1);
>-
>-	baseline = read_xe_module_ref();
>-	igt_debug("baseline ref count (drm fd closed) = %u\n", baseline);
>-
>-	drm_fd = __drm_open_driver(DRIVER_XE);
>-	if (is_xe_device(drm_fd))
>-		xe_device_get(drm_fd);
>-	devid = intel_get_drm_devid(drm_fd);
>-	sysfs = igt_sysfs_open(drm_fd);
>-
>-	/* Note: these global variables are only initialized after calling
>-	 * init_sys_info()...
>-	 */
>-	igt_require(init_sys_info());
>-	properties[5] = default_test_set->perf_oa_metrics_set;
>-	properties[7] = __ff(default_test_set->perf_oa_format);
>-	properties[9] = oa_exp_1_millisec;
>-
>-	ref_count0 = read_xe_module_ref();
>-	igt_debug("initial ref count with drm_fd open = %u\n", ref_count0);
>-
>-	stream_fd = __perf_open(drm_fd, &param, false);
>-        set_fd_flags(stream_fd, O_CLOEXEC);
>-	ref_count1 = read_xe_module_ref();
>-	igt_debug("ref count after opening oa stream = %u\n", ref_count1);
>-
>-	drm_close_driver(drm_fd);
>-	close(sysfs);
>-	drm_fd = -1;
>-	sysfs = -1;
>-	ref_count0 = read_xe_module_ref();
>-	igt_debug("ref count after closing drm fd = %u\n", ref_count0);
>-
>-	read_2_oa_reports(default_test_set->perf_oa_format,
>-			  oa_exp_1_millisec,
>-			  oa_report0,
>-			  oa_report1,
>-			  false); /* not just timer reports */
>-
>-	__perf_close(stream_fd);
>-	ref_count0 = read_xe_module_ref();
>-	igt_debug("ref count after closing oa stream fd = %u\n", ref_count0);
>-}
>-
> /**
>  * SUBTEST: sysctl-defaults
>  * Description: Test that perf_stream_paranoid sysctl exists
>@@ -4621,9 +4517,6 @@ igt_main
> 		igt_require(!stat("/proc/sys/dev/xe/perf_stream_paranoid", &sb));
> 	}
>
>-	igt_subtest("xe-ref-count")
>-		test_xe_ref_count();
>-
> 	igt_subtest("sysctl-defaults")
> 		test_sysctl_defaults();
>
>-- 
>2.41.0
>

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH i-g-t 14/14] HAX: Add Xe OA tests to xe-fast-feedback.testlist
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (12 preceding siblings ...)
  2024-07-01  2:53 ` [PATCH i-g-t 13/14] tests/intel/xe_oa: Drop "xe-ref-count" subtest Ashutosh Dixit
@ 2024-07-01  2:53 ` Ashutosh Dixit
  2024-07-01  3:23 ` ✓ CI.xeBAT: success for Intel Xe OA IGT's (rev7) Patchwork
                   ` (3 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2024-07-01  2:53 UTC (permalink / raw)
  To: igt-dev

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel-ci/xe-fast-feedback.testlist | 40 ++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/tests/intel-ci/xe-fast-feedback.testlist b/tests/intel-ci/xe-fast-feedback.testlist
index aa98b37e64..bcd53fb98f 100644
--- a/tests/intel-ci/xe-fast-feedback.testlist
+++ b/tests/intel-ci/xe-fast-feedback.testlist
@@ -65,6 +65,46 @@ igt@kms_prop_blob@basic
 igt@kms_psr@psr-primary-page-flip
 igt@kms_psr@psr-cursor-plane-move
 igt@kms_psr@psr-sprite-plane-onoff
+
+# oa tests
+igt@xe_oa@sysctl-defaults
+igt@xe_oa@non-system-wide-paranoid
+igt@xe_oa@invalid-oa-metric-set-id
+igt@xe_oa@invalid-oa-format-id
+igt@xe_oa@missing-sample-flags
+igt@xe_oa@oa-formats
+igt@xe_oa@invalid-oa-exponent
+igt@xe_oa@oa-exponents
+igt@xe_oa@buffer-fill
+igt@xe_oa@non-zero-reason
+igt@xe_oa@disabled-read-error
+igt@xe_oa@non-sampling-read-error
+igt@xe_oa@enable-disable
+igt@xe_oa@blocking
+igt@xe_oa@polling
+igt@xe_oa@polling-small-buf
+igt@xe_oa@short-reads
+igt@xe_oa@mi-rpc
+igt@xe_oa@oa-tlb-invalidate
+igt@xe_oa@unprivileged-single-ctx-counters
+igt@xe_oa@oa-unit-exclusive-stream-sample-oa
+igt@xe_oa@oa-unit-exclusive-stream-exec-q
+igt@xe_oa@oa-unit-concurrent-oa-buffer-read
+igt@xe_oa@rc6-disable
+igt@xe_oa@stress-open-close
+igt@xe_oa@invalid-create-userspace-config
+igt@xe_oa@invalid-remove-userspace-config
+igt@xe_oa@create-destroy-userspace-config
+igt@xe_oa@whitelisted-registers-userspace-config
+igt@xe_oa@map-oa-buffer
+igt@xe_oa@invalid-map-oa-buffer
+igt@xe_oa@non-privileged-map-oa-buffer
+igt@xe_oa@non-privileged-access-vaddr
+igt@xe_oa@privileged-forked-access-vaddr
+igt@xe_oa@closed-fd-and-unmapped-access
+igt@xe_oa@oa-regs-whitelisted
+igt@xe_oa@mmio-triggered-reports
+
 igt@xe_compute@compute-square
 igt@xe_create@create-execqueues-noleak
 igt@xe_create@create-execqueues-leak
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* ✓ CI.xeBAT: success for Intel Xe OA IGT's (rev7)
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (13 preceding siblings ...)
  2024-07-01  2:53 ` [PATCH i-g-t 14/14] HAX: Add Xe OA tests to xe-fast-feedback.testlist Ashutosh Dixit
@ 2024-07-01  3:23 ` Patchwork
  2024-07-01  3:31 ` ✓ Fi.CI.BAT: " Patchwork
                   ` (2 subsequent siblings)
  17 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2024-07-01  3:23 UTC (permalink / raw)
  To: Ashutosh Dixit; +Cc: igt-dev

[-- Attachment #1: Type: text/plain, Size: 11818 bytes --]

== Series Details ==

Series: Intel Xe OA IGT's (rev7)
URL   : https://patchwork.freedesktop.org/series/130033/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7908_BAT -> XEIGTPW_11343_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (5 -> 5)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_11343_BAT:

### IGT changes ###

#### Possible regressions ####

  * {igt@xe_oa@mi-rpc} (NEW):
    - bat-atsm-2:         NOTRUN -> [INCOMPLETE][1] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-atsm-2/igt@xe_oa@mi-rpc.html

  * {igt@xe_oa@mi-rpc@ccs-0} (NEW):
    - bat-pvc-2:          NOTRUN -> [INCOMPLETE][2] +1 other test incomplete
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-pvc-2/igt@xe_oa@mi-rpc@ccs-0.html
    - bat-dg2-oem2:       NOTRUN -> [INCOMPLETE][3] +1 other test incomplete
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-dg2-oem2/igt@xe_oa@mi-rpc@ccs-0.html

  * {igt@xe_oa@mmio-triggered-reports} (NEW):
    - bat-adlp-7:         NOTRUN -> [SKIP][4]
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-adlp-7/igt@xe_oa@mmio-triggered-reports.html

  * {igt@xe_oa@non-zero-reason} (NEW):
    - bat-pvc-2:          NOTRUN -> [FAIL][5] +6 other tests fail
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-pvc-2/igt@xe_oa@non-zero-reason.html
    - bat-dg2-oem2:       NOTRUN -> [FAIL][6] +1 other test fail
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-dg2-oem2/igt@xe_oa@non-zero-reason.html

  * {igt@xe_oa@oa-formats} (NEW):
    - bat-pvc-2:          NOTRUN -> [TIMEOUT][7] +1 other test timeout
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-pvc-2/igt@xe_oa@oa-formats.html

  * {igt@xe_oa@oa-tlb-invalidate} (NEW):
    - {bat-lnl-1}:        NOTRUN -> [SKIP][8] +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-lnl-1/igt@xe_oa@oa-tlb-invalidate.html
    - bat-pvc-2:          NOTRUN -> [SKIP][9] +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-pvc-2/igt@xe_oa@oa-tlb-invalidate.html

  * {igt@xe_oa@polling-small-buf} (NEW):
    - bat-atsm-2:         NOTRUN -> [FAIL][10]
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-atsm-2/igt@xe_oa@polling-small-buf.html

  * {igt@xe_oa@rc6-disable} (NEW):
    - bat-atsm-2:         NOTRUN -> [SKIP][11]
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-atsm-2/igt@xe_oa@rc6-disable.html

  
New tests
---------

  New tests have been introduced between XEIGT_7908_BAT and XEIGTPW_11343_BAT:

### New IGT tests (73) ###

  * igt@xe_oa@blocking:
    - Statuses : 5 pass(s)
    - Exec time: [1.01, 1.03] s

  * igt@xe_oa@blocking@ccs-0:
    - Statuses : 3 pass(s)
    - Exec time: [1.01, 1.03] s

  * igt@xe_oa@blocking@rcs-0:
    - Statuses : 2 pass(s)
    - Exec time: [1.01] s

  * igt@xe_oa@buffer-fill:
    - Statuses : 5 pass(s)
    - Exec time: [1.00, 6.70] s

  * igt@xe_oa@buffer-fill@ccs-0:
    - Statuses : 2 pass(s)
    - Exec time: [1.00, 5.10] s

  * igt@xe_oa@buffer-fill@rcs-0:
    - Statuses : 3 pass(s)
    - Exec time: [2.29, 6.70] s

  * igt@xe_oa@closed-fd-and-unmapped-access:
    - Statuses : 1 fail(s) 4 pass(s)
    - Exec time: [0.08, 0.11] s

  * igt@xe_oa@closed-fd-and-unmapped-access@ccs-0:
    - Statuses : 1 fail(s) 1 pass(s)
    - Exec time: [0.08, 0.10] s

  * igt@xe_oa@closed-fd-and-unmapped-access@rcs-0:
    - Statuses : 3 pass(s)
    - Exec time: [0.10] s

  * igt@xe_oa@create-destroy-userspace-config:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.05] s

  * igt@xe_oa@disabled-read-error:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.02] s

  * igt@xe_oa@enable-disable:
    - Statuses : 5 pass(s)
    - Exec time: [0.98, 5.82] s

  * igt@xe_oa@enable-disable@ccs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.98, 5.81] s

  * igt@xe_oa@enable-disable@rcs-0:
    - Statuses : 3 pass(s)
    - Exec time: [2.23, 4.78] s

  * igt@xe_oa@invalid-create-userspace-config:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@xe_oa@invalid-map-oa-buffer:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.02] s

  * igt@xe_oa@invalid-map-oa-buffer@ccs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@invalid-map-oa-buffer@rcs-0:
    - Statuses : 3 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@invalid-oa-exponent:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.03] s

  * igt@xe_oa@invalid-oa-format-id:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.02] s

  * igt@xe_oa@invalid-oa-metric-set-id:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.02] s

  * igt@xe_oa@invalid-remove-userspace-config:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.06] s

  * igt@xe_oa@map-oa-buffer:
    - Statuses : 1 fail(s) 4 pass(s)
    - Exec time: [0.08, 0.10] s

  * igt@xe_oa@map-oa-buffer@ccs-0:
    - Statuses : 1 fail(s) 1 pass(s)
    - Exec time: [0.08, 0.10] s

  * igt@xe_oa@map-oa-buffer@rcs-0:
    - Statuses : 3 pass(s)
    - Exec time: [0.10] s

  * igt@xe_oa@mi-rpc:
    - Statuses : 3 incomplete(s) 2 pass(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_oa@mi-rpc@ccs-0:
    - Statuses : 2 incomplete(s) 1 pass(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_oa@mi-rpc@rcs-0:
    - Statuses : 1 incomplete(s) 1 pass(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_oa@missing-sample-flags:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@xe_oa@mmio-triggered-reports:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.04] s

  * igt@xe_oa@mmio-triggered-reports@ccs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.01, 0.04] s

  * igt@xe_oa@mmio-triggered-reports@rcs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.01, 0.03] s

  * igt@xe_oa@non-privileged-access-vaddr:
    - Statuses : 5 pass(s)
    - Exec time: [0.02, 0.05] s

  * igt@xe_oa@non-privileged-access-vaddr@ccs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.02, 0.05] s

  * igt@xe_oa@non-privileged-access-vaddr@rcs-0:
    - Statuses : 3 pass(s)
    - Exec time: [0.02] s

  * igt@xe_oa@non-privileged-map-oa-buffer:
    - Statuses : 5 pass(s)
    - Exec time: [0.02, 0.06] s

  * igt@xe_oa@non-privileged-map-oa-buffer@ccs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.02, 0.06] s

  * igt@xe_oa@non-privileged-map-oa-buffer@rcs-0:
    - Statuses : 3 pass(s)
    - Exec time: [0.02] s

  * igt@xe_oa@non-sampling-read-error:
    - Statuses : 5 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@non-system-wide-paranoid:
    - Statuses : 5 pass(s)
    - Exec time: [0.03, 0.10] s

  * igt@xe_oa@non-zero-reason:
    - Statuses : 2 fail(s) 3 pass(s)
    - Exec time: [2.00, 8.77] s

  * igt@xe_oa@non-zero-reason@ccs-0:
    - Statuses : 2 fail(s) 2 pass(s)
    - Exec time: [2.00, 8.77] s

  * igt@xe_oa@non-zero-reason@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [7.50] s

  * igt@xe_oa@oa-exponents:
    - Statuses : 5 pass(s)
    - Exec time: [1.93, 5.91] s

  * igt@xe_oa@oa-exponents@ccs-0:
    - Statuses : 3 pass(s)
    - Exec time: [1.93, 5.91] s

  * igt@xe_oa@oa-exponents@rcs-0:
    - Statuses : 2 pass(s)
    - Exec time: [3.38, 3.46] s

  * igt@xe_oa@oa-formats:
    - Statuses : 4 pass(s) 1 timeout(s)
    - Exec time: [0.0, 0.14] s

  * igt@xe_oa@oa-formats@rcs-0:
    - Statuses : 4 pass(s)
    - Exec time: [0.01, 0.14] s

  * igt@xe_oa@oa-regs-whitelisted:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.21] s

  * igt@xe_oa@oa-regs-whitelisted@ccs-0:
    - Statuses : 3 pass(s)
    - Exec time: [0.02, 0.21] s

  * igt@xe_oa@oa-regs-whitelisted@rcs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@oa-tlb-invalidate:
    - Statuses : 3 pass(s) 2 skip(s)
    - Exec time: [0.0, 10.05] s

  * igt@xe_oa@oa-tlb-invalidate@ccs-0:
    - Statuses : 1 pass(s)
    - Exec time: [10.04] s

  * igt@xe_oa@oa-tlb-invalidate@rcs-0:
    - Statuses : 2 pass(s)
    - Exec time: [10.04, 10.05] s

  * igt@xe_oa@oa-unit-concurrent-oa-buffer-read:
    - Statuses : 5 pass(s)
    - Exec time: [1.02, 1.05] s

  * igt@xe_oa@oa-unit-exclusive-stream-exec-q:
    - Statuses : 5 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
    - Statuses : 5 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@polling:
    - Statuses : 5 pass(s)
    - Exec time: [1.02, 1.03] s

  * igt@xe_oa@polling-small-buf:
    - Statuses : 2 fail(s) 3 pass(s)
    - Exec time: [0.09, 0.10] s

  * igt@xe_oa@polling@ccs-0:
    - Statuses : 3 pass(s)
    - Exec time: [1.02, 1.03] s

  * igt@xe_oa@polling@rcs-0:
    - Statuses : 2 pass(s)
    - Exec time: [1.02] s

  * igt@xe_oa@privileged-forked-access-vaddr:
    - Statuses : 5 pass(s)
    - Exec time: [0.02, 0.06] s

  * igt@xe_oa@privileged-forked-access-vaddr@ccs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.02, 0.06] s

  * igt@xe_oa@privileged-forked-access-vaddr@rcs-0:
    - Statuses : 3 pass(s)
    - Exec time: [0.02, 0.03] s

  * igt@xe_oa@rc6-disable:
    - Statuses : 3 pass(s) 2 skip(s)
    - Exec time: [0.05, 0.17] s

  * igt@xe_oa@short-reads:
    - Statuses : 5 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@stress-open-close:
    - Statuses : 5 pass(s)
    - Exec time: [2.17, 5.83] s

  * igt@xe_oa@stress-open-close@ccs-0:
    - Statuses : 3 pass(s)
    - Exec time: [2.17, 5.83] s

  * igt@xe_oa@stress-open-close@rcs-0:
    - Statuses : 2 pass(s)
    - Exec time: [2.17, 2.21] s

  * igt@xe_oa@sysctl-defaults:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@xe_oa@unprivileged-single-ctx-counters:
    - Statuses : 3 pass(s) 1 skip(s) 1 timeout(s)
    - Exec time: [0.0, 0.05] s

  * igt@xe_oa@unprivileged-single-ctx-counters@rcs-0:
    - Statuses : 3 pass(s)
    - Exec time: [0.01, 0.05] s

  * igt@xe_oa@whitelisted-registers-userspace-config:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_11343_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_frontbuffer_tracking@basic:
    - bat-adlp-7:         [PASS][12] -> [DMESG-FAIL][13] ([Intel XE#324])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@xe_exec_compute_mode@twice-userptr-invalidate:
    - {bat-lnl-1}:        [FAIL][14] ([Intel XE#1069]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/bat-lnl-1/igt@xe_exec_compute_mode@twice-userptr-invalidate.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/bat-lnl-1/igt@xe_exec_compute_mode@twice-userptr-invalidate.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1069
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324


Build changes
-------------

  * IGT: IGT_7908 -> IGTPW_11343
  * Linux: xe-1546-886eeb6d89b58f914ee5045fcac54b59a73d8299 -> xe-1548-886eeb6d89b58f914ee5045fcac54b59a73d8299

  IGTPW_11343: 11343
  IGT_7908: 7908
  xe-1546-886eeb6d89b58f914ee5045fcac54b59a73d8299: 886eeb6d89b58f914ee5045fcac54b59a73d8299
  xe-1548-886eeb6d89b58f914ee5045fcac54b59a73d8299: 886eeb6d89b58f914ee5045fcac54b59a73d8299

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/index.html

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^ permalink raw reply	[flat|nested] 26+ messages in thread

* ✓ Fi.CI.BAT: success for Intel Xe OA IGT's (rev7)
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (14 preceding siblings ...)
  2024-07-01  3:23 ` ✓ CI.xeBAT: success for Intel Xe OA IGT's (rev7) Patchwork
@ 2024-07-01  3:31 ` Patchwork
  2024-07-01  5:00 ` ✗ CI.xeFULL: failure " Patchwork
  2024-07-01  5:36 ` ✗ Fi.CI.IGT: " Patchwork
  17 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2024-07-01  3:31 UTC (permalink / raw)
  To: Ashutosh Dixit; +Cc: igt-dev

[-- Attachment #1: Type: text/plain, Size: 3782 bytes --]

== Series Details ==

Series: Intel Xe OA IGT's (rev7)
URL   : https://patchwork.freedesktop.org/series/130033/
State : success

== Summary ==

CI Bug Log - changes from IGT_7908 -> IGTPW_11343
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/index.html

Participating hosts (41 -> 37)
------------------------------

  Missing    (4): bat-kbl-2 bat-arlh-2 fi-cfl-8109u fi-snb-2520m 

Known issues
------------

  Here are the changes found in IGTPW_11343 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@load:
    - bat-dg2-9:          [PASS][1] -> [DMESG-WARN][2] ([i915#11548])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/bat-dg2-9/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/bat-dg2-9/igt@i915_module_load@load.html

  * igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1:
    - bat-dg2-8:          [PASS][3] -> [FAIL][4] ([i915#11379])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/bat-dg2-8/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/bat-dg2-8/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@client:
    - bat-arls-1:         [DMESG-WARN][5] ([i915#10341]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/bat-arls-1/igt@i915_selftest@live@client.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/bat-arls-1/igt@i915_selftest@live@client.html

  * igt@i915_selftest@live@execlists:
    - bat-arls-1:         [DMESG-FAIL][7] ([i915#10262]) -> [PASS][8] +11 other tests pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/bat-arls-1/igt@i915_selftest@live@execlists.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/bat-arls-1/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@hangcheck:
    - bat-arls-2:         [ABORT][9] -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/bat-arls-2/igt@i915_selftest@live@hangcheck.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/bat-arls-2/igt@i915_selftest@live@hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-arls-2:         [DMESG-WARN][11] ([i915#7507]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/bat-arls-2/igt@kms_frontbuffer_tracking@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/bat-arls-2/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-dp-1:
    - bat-dg2-8:          [FAIL][13] ([i915#11379]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/bat-dg2-8/igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-dp-1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/bat-dg2-8/igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-dp-1.html

  
  [i915#10262]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10262
  [i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
  [i915#11379]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11379
  [i915#11548]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11548
  [i915#7507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7507


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7908 -> IGTPW_11343

  CI-20190529: 20190529
  CI_DRM_15013: 0318a12ff6fb8c321458aa2b373e9322896ee951 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_11343: 11343
  IGT_7908: 7908

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/index.html

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^ permalink raw reply	[flat|nested] 26+ messages in thread

* ✗ CI.xeFULL: failure for Intel Xe OA IGT's (rev7)
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (15 preceding siblings ...)
  2024-07-01  3:31 ` ✓ Fi.CI.BAT: " Patchwork
@ 2024-07-01  5:00 ` Patchwork
  2024-07-01 19:56   ` Umesh Nerlige Ramappa
  2024-07-01  5:36 ` ✗ Fi.CI.IGT: " Patchwork
  17 siblings, 1 reply; 26+ messages in thread
From: Patchwork @ 2024-07-01  5:00 UTC (permalink / raw)
  To: Ashutosh Dixit; +Cc: igt-dev

[-- Attachment #1: Type: text/plain, Size: 34663 bytes --]

== Series Details ==

Series: Intel Xe OA IGT's (rev7)
URL   : https://patchwork.freedesktop.org/series/130033/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_7908_full -> XEIGTPW_11343_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_11343_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_11343_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_11343_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_pm_rpm@i2c:
    - shard-dg2-set2:     [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-436/igt@kms_pm_rpm@i2c.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-434/igt@kms_pm_rpm@i2c.html

  * {igt@xe_oa@non-zero-reason@rcs-0} (NEW):
    - shard-dg2-set2:     NOTRUN -> [FAIL][3] +1 other test fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-434/igt@xe_oa@non-zero-reason@rcs-0.html

  * {igt@xe_oa@unprivileged-single-ctx-counters} (NEW):
    - {shard-lnl}:        NOTRUN -> [SKIP][4]
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-2/igt@xe_oa@unprivileged-single-ctx-counters.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p}:
    - {shard-lnl}:        NOTRUN -> [SKIP][5]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-4/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_cursor_crc@cursor-random-64x64:
    - {shard-lnl}:        [PASS][6] -> [INCOMPLETE][7]
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-lnl-5/igt@kms_cursor_crc@cursor-random-64x64.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-8/igt@kms_cursor_crc@cursor-random-64x64.html

  * igt@xe_pm:
    - {shard-lnl}:        NOTRUN -> [INCOMPLETE][8]
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-8/igt@xe_pm.html

  
New tests
---------

  New tests have been introduced between XEIGT_7908_full and XEIGTPW_11343_full:

### New IGT tests (61) ###

  * igt@xe_oa@blocking:
    - Statuses : 1 pass(s)
    - Exec time: [1.01] s

  * igt@xe_oa@blocking@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [1.01] s

  * igt@xe_oa@buffer-fill:
    - Statuses : 2 pass(s)
    - Exec time: [1.00, 2.33] s

  * igt@xe_oa@buffer-fill@rcs-0:
    - Statuses : 2 pass(s)
    - Exec time: [1.00, 2.33] s

  * igt@xe_oa@closed-fd-and-unmapped-access:
    - Statuses : 2 pass(s)
    - Exec time: [0.10] s

  * igt@xe_oa@closed-fd-and-unmapped-access@ccs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.10] s

  * igt@xe_oa@closed-fd-and-unmapped-access@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.10] s

  * igt@xe_oa@create-destroy-userspace-config:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@disabled-read-error:
    - Statuses : 2 pass(s)
    - Exec time: [0.01, 0.02] s

  * igt@xe_oa@enable-disable:
    - Statuses : 1 pass(s)
    - Exec time: [2.41] s

  * igt@xe_oa@enable-disable@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [2.41] s

  * igt@xe_oa@invalid-create-userspace-config:
    - Statuses : 2 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@xe_oa@invalid-map-oa-buffer:
    - Statuses : 2 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@invalid-map-oa-buffer@rcs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@invalid-oa-exponent:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@invalid-oa-format-id:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@invalid-oa-metric-set-id:
    - Statuses : 2 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@invalid-remove-userspace-config:
    - Statuses : 2 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@map-oa-buffer:
    - Statuses : 2 pass(s)
    - Exec time: [0.10] s

  * igt@xe_oa@map-oa-buffer@ccs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.10] s

  * igt@xe_oa@mi-rpc:
    - Statuses : 1 incomplete(s) 1 pass(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_oa@mi-rpc@ccs-0:
    - Statuses : 1 incomplete(s) 1 pass(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_oa@missing-sample-flags:
    - Statuses : 2 pass(s)
    - Exec time: [0.0] s

  * igt@xe_oa@mmio-triggered-reports:
    - Statuses : 2 pass(s)
    - Exec time: [0.01, 0.04] s

  * igt@xe_oa@mmio-triggered-reports@ccs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@mmio-triggered-reports@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.04] s

  * igt@xe_oa@non-privileged-access-vaddr:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@xe_oa@non-privileged-access-vaddr@ccs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@xe_oa@non-privileged-map-oa-buffer:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@xe_oa@non-privileged-map-oa-buffer@ccs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@xe_oa@non-sampling-read-error:
    - Statuses : 2 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@non-system-wide-paranoid:
    - Statuses : 2 pass(s)
    - Exec time: [0.03, 0.04] s

  * igt@xe_oa@non-zero-reason:
    - Statuses : 1 fail(s) 1 pass(s)
    - Exec time: [2.79, 2.85] s

  * igt@xe_oa@non-zero-reason@ccs-0:
    - Statuses : 1 pass(s)
    - Exec time: [2.85] s

  * igt@xe_oa@non-zero-reason@rcs-0:
    - Statuses : 1 fail(s)
    - Exec time: [2.79] s

  * igt@xe_oa@oa-exponents:
    - Statuses : 1 pass(s)
    - Exec time: [3.04] s

  * igt@xe_oa@oa-exponents@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [3.04] s

  * igt@xe_oa@oa-formats:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@xe_oa@oa-formats@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@xe_oa@oa-regs-whitelisted:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@oa-regs-whitelisted@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@oa-tlb-invalidate:
    - Statuses : 1 pass(s)
    - Exec time: [10.03] s

  * igt@xe_oa@oa-tlb-invalidate@ccs-0:
    - Statuses : 1 pass(s)
    - Exec time: [10.03] s

  * igt@xe_oa@oa-unit-concurrent-oa-buffer-read:
    - Statuses : 2 pass(s)
    - Exec time: [1.02, 1.03] s

  * igt@xe_oa@oa-unit-exclusive-stream-exec-q:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@polling:
    - Statuses : 1 pass(s)
    - Exec time: [1.02] s

  * igt@xe_oa@polling-small-buf:
    - Statuses : 2 pass(s)
    - Exec time: [0.09] s

  * igt@xe_oa@polling@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [1.02] s

  * igt@xe_oa@privileged-forked-access-vaddr:
    - Statuses : 2 pass(s)
    - Exec time: [0.02, 0.03] s

  * igt@xe_oa@privileged-forked-access-vaddr@ccs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@xe_oa@privileged-forked-access-vaddr@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.03] s

  * igt@xe_oa@rc6-disable:
    - Statuses : 2 pass(s)
    - Exec time: [0.17] s

  * igt@xe_oa@short-reads:
    - Statuses : 2 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@stress-open-close:
    - Statuses : 2 pass(s)
    - Exec time: [2.17, 2.40] s

  * igt@xe_oa@stress-open-close@ccs-0:
    - Statuses : 1 pass(s)
    - Exec time: [2.17] s

  * igt@xe_oa@stress-open-close@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [2.40] s

  * igt@xe_oa@sysctl-defaults:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@xe_oa@unprivileged-single-ctx-counters:
    - Statuses : 1 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_oa@unprivileged-single-ctx-counters@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_oa@whitelisted-registers-userspace-config:
    - Statuses : 2 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_11343_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#1124] / [Intel XE#1201]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-434/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#1201] / [Intel XE#1252])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-466/igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#1201] / [Intel XE#787]) +20 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +5 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#1201] / [Intel XE#306])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-464/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_frames@vga-frame-dump:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#1201] / [Intel XE#373]) +3 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-463/igt@kms_chamelium_frames@vga-frame-dump.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#1201] / [Intel XE#308])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-434/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@torture-move@pipe-a:
    - shard-dg2-set2:     [PASS][16] -> [DMESG-WARN][17] ([Intel XE#1214] / [Intel XE#877]) +1 other test dmesg-warn
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-436/igt@kms_cursor_legacy@torture-move@pipe-a.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-464/igt@kms_cursor_legacy@torture-move@pipe-a.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#1201] / [Intel XE#701])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-466/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@cd-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][19] -> [INCOMPLETE][20] ([Intel XE#1195])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-434/igt@kms_flip@2x-flip-vs-suspend-interruptible@cd-hdmi-a6-dp4.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-463/igt@kms_flip@2x-flip-vs-suspend-interruptible@cd-hdmi-a6-dp4.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a6:
    - shard-dg2-set2:     [PASS][21] -> [DMESG-WARN][22] ([Intel XE#1214] / [Intel XE#1551])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-466/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a6.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a6.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#1201] / [Intel XE#651]) +9 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#1201] / [Intel XE#653]) +8 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][25] ([Intel XE#1162] / [Intel XE#1214])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-436/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][26] ([Intel XE#1214]) +1 other test dmesg-warn
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-436/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#1201] / [Intel XE#305] / [Intel XE#455])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-464/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#1201] / [Intel XE#305]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-464/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][29] ([Intel XE#1201] / [Intel XE#455])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-464/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-6.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][30] ([Intel XE#1201] / [Intel XE#1489]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-433/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@pr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][31] ([Intel XE#1201] / [Intel XE#929]) +4 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-435/igt@kms_psr@pr-dpms.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#1201] / [Intel XE#327])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-434/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@xe_ccs@suspend-resume@linear-compressed-compfmt0-system-vram01:
    - shard-dg2-set2:     [PASS][33] -> [FAIL][34] ([Intel XE#2028]) +1 other test fail
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-436/igt@xe_ccs@suspend-resume@linear-compressed-compfmt0-system-vram01.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-466/igt@xe_ccs@suspend-resume@linear-compressed-compfmt0-system-vram01.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][35] ([Intel XE#1201] / [Intel XE#944])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-436/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_evict@evict-cm-threads-large:
    - shard-dg2-set2:     [PASS][36] -> [TIMEOUT][37] ([Intel XE#1041] / [Intel XE#1473] / [Intel XE#392])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-433/igt@xe_evict@evict-cm-threads-large.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-433/igt@xe_evict@evict-cm-threads-large.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][38] ([Intel XE#1201] / [Intel XE#288]) +6 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-464/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-imm.html

  * igt@xe_exec_threads@threads-bal-mixed-userptr:
    - shard-dg2-set2:     [PASS][39] -> [DMESG-WARN][40] ([Intel XE#1214]) +3 other tests dmesg-warn
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-433/igt@xe_exec_threads@threads-bal-mixed-userptr.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-464/igt@xe_exec_threads@threads-bal-mixed-userptr.html

  * igt@xe_exec_threads@threads-bal-shared-vm-userptr-invalidate:
    - shard-dg2-set2:     [PASS][41] -> [DMESG-FAIL][42] ([Intel XE#358])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-433/igt@xe_exec_threads@threads-bal-shared-vm-userptr-invalidate.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-463/igt@xe_exec_threads@threads-bal-shared-vm-userptr-invalidate.html

  * igt@xe_live_ktest@xe_bo:
    - shard-dg2-set2:     [PASS][43] -> [SKIP][44] ([Intel XE#1192] / [Intel XE#1201])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-464/igt@xe_live_ktest@xe_bo.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-436/igt@xe_live_ktest@xe_bo.html

  * {igt@xe_oa@mi-rpc} (NEW):
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][45] ([Intel XE#1195]) +1 other test incomplete
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-434/igt@xe_oa@mi-rpc.html

  * igt@xe_pm@s3-multiple-execs:
    - shard-dg2-set2:     [PASS][46] -> [DMESG-WARN][47] ([Intel XE#1214] / [Intel XE#1551] / [Intel XE#569])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-436/igt@xe_pm@s3-multiple-execs.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-463/igt@xe_pm@s3-multiple-execs.html

  * igt@xe_pm@s3-vm-bind-prefetch:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][48] ([Intel XE#1214] / [Intel XE#569])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-435/igt@xe_pm@s3-vm-bind-prefetch.html

  
#### Possible fixes ####

  * {igt@core_getversion@all-cards}:
    - shard-dg2-set2:     [DMESG-WARN][49] ([Intel XE#1214]) -> [PASS][50] +4 other tests pass
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-466/igt@core_getversion@all-cards.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-464/igt@core_getversion@all-cards.html

  * igt@kms_async_flips@crc@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][51] ([Intel XE#1195]) -> [PASS][52] +2 other tests pass
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-464/igt@kms_async_flips@crc@pipe-d-hdmi-a-6.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-463/igt@kms_async_flips@crc@pipe-d-hdmi-a-6.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-0:
    - {shard-lnl}:        [FAIL][53] ([Intel XE#1659] / [Intel XE#1874]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-lnl-2/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-4/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html

  * igt@kms_cursor_legacy@torture-bo@pipe-b:
    - shard-dg2-set2:     [DMESG-WARN][55] ([Intel XE#1214] / [Intel XE#877]) -> [PASS][56] +1 other test pass
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-434/igt@kms_cursor_legacy@torture-bo@pipe-b.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-433/igt@kms_cursor_legacy@torture-bo@pipe-b.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - {shard-lnl}:        [FAIL][57] ([Intel XE#886]) -> [PASS][58] +1 other test pass
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-lnl-5/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-1/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
    - {shard-lnl}:        [DMESG-WARN][59] ([Intel XE#2052]) -> [PASS][60] +1 other test pass
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-lnl-3/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-2/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     [SKIP][61] ([Intel XE#1201] / [Intel XE#455]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-466/igt@kms_hdr@invalid-hdr.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-463/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [FAIL][63] ([Intel XE#361]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-464/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-434/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - {shard-lnl}:        [ABORT][65] ([Intel XE#1553]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-lnl-1/igt@kms_scaling_modes@scaling-mode-full.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-6/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_scaling_modes@scaling-mode-full@pipe-b-edp-1:
    - {shard-lnl}:        [ABORT][67] -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-lnl-1/igt@kms_scaling_modes@scaling-mode-full@pipe-b-edp-1.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-6/igt@kms_scaling_modes@scaling-mode-full@pipe-b-edp-1.html

  * igt@kms_scaling_modes@scaling-mode-full@pipe-c-edp-1:
    - {shard-lnl}:        [DMESG-WARN][69] ([Intel XE#1553]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-lnl-1/igt@kms_scaling_modes@scaling-mode-full@pipe-c-edp-1.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-6/igt@kms_scaling_modes@scaling-mode-full@pipe-c-edp-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [FAIL][71] ([Intel XE#899]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-436/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-466/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-dg2-set2:     [DMESG-WARN][73] ([Intel XE#1214] / [Intel XE#1551]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-466/igt@kms_vblank@ts-continuation-dpms-suspend.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-436/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@xe_evict@evict-beng-large-multi-vm-cm:
    - shard-dg2-set2:     [FAIL][75] ([Intel XE#1600]) -> [PASS][76] +1 other test pass
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-463/igt@xe_evict@evict-beng-large-multi-vm-cm.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-435/igt@xe_evict@evict-beng-large-multi-vm-cm.html

  * igt@xe_evict@evict-beng-threads-large:
    - shard-dg2-set2:     [TIMEOUT][77] ([Intel XE#1473]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-433/igt@xe_evict@evict-beng-threads-large.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-434/igt@xe_evict@evict-beng-threads-large.html

  * igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race:
    - {shard-lnl}:        [ABORT][79] ([Intel XE#2097]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-lnl-5/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-lnl-4/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_live_ktest@xe_dma_buf:
    - shard-dg2-set2:     [SKIP][81] ([Intel XE#1192] / [Intel XE#1201]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-466/igt@xe_live_ktest@xe_dma_buf.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-434/igt@xe_live_ktest@xe_dma_buf.html

  
#### Warnings ####

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-dg2-set2:     [DMESG-WARN][83] ([Intel XE#1214]) -> [INCOMPLETE][84] ([Intel XE#1195])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-434/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-463/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-dg2-set2:     [INCOMPLETE][85] ([Intel XE#1195] / [Intel XE#2049]) -> [DMESG-WARN][86] ([Intel XE#1214] / [Intel XE#1551])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-466/igt@kms_flip@flip-vs-suspend-interruptible.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@xe_evict@evict-beng-cm-threads-large:
    - shard-dg2-set2:     [TIMEOUT][87] ([Intel XE#1041] / [Intel XE#1473] / [Intel XE#392]) -> [TIMEOUT][88] ([Intel XE#1473] / [Intel XE#392])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-433/igt@xe_evict@evict-beng-cm-threads-large.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-464/igt@xe_evict@evict-beng-cm-threads-large.html

  * igt@xe_evict@evict-beng-mixed-many-threads-large:
    - shard-dg2-set2:     [INCOMPLETE][89] ([Intel XE#1195] / [Intel XE#1473] / [Intel XE#392]) -> [TIMEOUT][90] ([Intel XE#1041] / [Intel XE#1473] / [Intel XE#392])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-466/igt@xe_evict@evict-beng-mixed-many-threads-large.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-433/igt@xe_evict@evict-beng-mixed-many-threads-large.html

  * igt@xe_evict@evict-mixed-threads-large:
    - shard-dg2-set2:     [TIMEOUT][91] ([Intel XE#1473] / [Intel XE#392]) -> [DMESG-FAIL][92] ([Intel XE#482])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-463/igt@xe_evict@evict-mixed-threads-large.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-466/igt@xe_evict@evict-mixed-threads-large.html

  * igt@xe_evict@evict-threads-large:
    - shard-dg2-set2:     [FAIL][93] ([Intel XE#1000]) -> [TIMEOUT][94] ([Intel XE#1473] / [Intel XE#392])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-466/igt@xe_evict@evict-threads-large.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-435/igt@xe_evict@evict-threads-large.html

  * igt@xe_live_ktest@xe_mocs:
    - shard-dg2-set2:     [FAIL][95] ([Intel XE#1999]) -> [SKIP][96] ([Intel XE#1192] / [Intel XE#1201])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-466/igt@xe_live_ktest@xe_mocs.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-463/igt@xe_live_ktest@xe_mocs.html

  * igt@xe_wedged@wedged-at-any-timeout:
    - shard-dg2-set2:     [DMESG-FAIL][97] ([Intel XE#1760]) -> [DMESG-WARN][98] ([Intel XE#1214] / [Intel XE#1760])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7908/shard-dg2-463/igt@xe_wedged@wedged-at-any-timeout.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/shard-dg2-435/igt@xe_wedged@wedged-at-any-timeout.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1000]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1000
  [Intel XE#1041]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1041
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1131
  [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
  [Intel XE#1162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1162
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
  [Intel XE#1214]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1214
  [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252
  [Intel XE#1330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1330
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1413
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1430
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1437
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1551]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1551
  [Intel XE#1553]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1553
  [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
  [Intel XE#1620]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1620
  [Intel XE#1622]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1622
  [Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659
  [Intel XE#1705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1705
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1760
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#1999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1999
  [Intel XE#2028]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2028
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2052]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2052
  [Intel XE#2097]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2097
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/294
  [Intel XE#305]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/305
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
  [Intel XE#358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/358
  [Intel XE#361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/361
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/392
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/482
  [Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498
  [Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * IGT: IGT_7908 -> IGTPW_11343
  * Linux: xe-1546-886eeb6d89b58f914ee5045fcac54b59a73d8299 -> xe-1548-886eeb6d89b58f914ee5045fcac54b59a73d8299

  IGTPW_11343: 11343
  IGT_7908: 7908
  xe-1546-886eeb6d89b58f914ee5045fcac54b59a73d8299: 886eeb6d89b58f914ee5045fcac54b59a73d8299
  xe-1548-886eeb6d89b58f914ee5045fcac54b59a73d8299: 886eeb6d89b58f914ee5045fcac54b59a73d8299

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/index.html

[-- Attachment #2: Type: text/html, Size: 40597 bytes --]

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: ✗ CI.xeFULL: failure for Intel Xe OA IGT's (rev7)
  2024-07-01  5:00 ` ✗ CI.xeFULL: failure " Patchwork
@ 2024-07-01 19:56   ` Umesh Nerlige Ramappa
  2024-07-01 23:08     ` Dixit, Ashutosh
  0 siblings, 1 reply; 26+ messages in thread
From: Umesh Nerlige Ramappa @ 2024-07-01 19:56 UTC (permalink / raw)
  To: igt-dev; +Cc: Ashutosh Dixit

On Mon, Jul 01, 2024 at 05:00:05AM +0000, Patchwork wrote:
>   Patch Details
>
>   Series:  Intel Xe OA IGT's (rev7)
>   URL:     [1]https://patchwork.freedesktop.org/series/130033/
>   State:   failure
>   Details: [2]https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11343/index.html
>
>        CI Bug Log - changes from XEIGT_7908_full -> XEIGTPW_11343_full
>
>Summary
>
>   FAILURE
>
>   Serious unknown changes coming with XEIGTPW_11343_full absolutely need to
>   be
>   verified manually.
>
>   If you think the reported changes have nothing to do with the changes
>   introduced in XEIGTPW_11343_full, please notify your bug team
>   (I915-ci-infra@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in
>   CI.
>
>Participating hosts (3 -> 3)
>
>   No changes in participating hosts
>
>Possible new issues
>
>   Here are the unknown changes that may have been introduced in
>   XEIGTPW_11343_full:
>
>  IGT changes
>
>    Possible regressions
>
>     * igt@kms_pm_rpm@i2c:
>
>          * shard-dg2-set2: [3]PASS -> [4]FAIL
>
>     * {igt@xe_oa@non-zero-reason@rcs-0} (NEW):
>
>          * shard-dg2-set2: NOTRUN -> [5]FAIL +1 other test fail

This is something that is an open bug even in i915 and will fail with Xe 
as well. Should we even merge this test as it will create a bunch of 
JIRAs every now and then.

Umesh
>

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: ✗ CI.xeFULL: failure for Intel Xe OA IGT's (rev7)
  2024-07-01 19:56   ` Umesh Nerlige Ramappa
@ 2024-07-01 23:08     ` Dixit, Ashutosh
  0 siblings, 0 replies; 26+ messages in thread
From: Dixit, Ashutosh @ 2024-07-01 23:08 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: igt-dev

On Mon, 01 Jul 2024 12:56:28 -0700, Umesh Nerlige Ramappa wrote:
>
> >  IGT changes
> >
> >    Possible regressions
> >
> >     * igt@kms_pm_rpm@i2c:
> >
> >          * shard-dg2-set2: [3]PASS -> [4]FAIL
> >
> >     * {igt@xe_oa@non-zero-reason@rcs-0} (NEW):
> >
> >          * shard-dg2-set2: NOTRUN -> [5]FAIL +1 other test fail
>
> This is something that is an open bug even in i915 and will fail with Xe as
> well. Should we even merge this test as it will create a bunch of JIRAs
> every now and then.

I am also thinking what to do about these failures. There are more in
"CI.xeBAT" (since the HAX patch added the tests to
xe-fast-feedback.testlist, though this will not happen in real CI):

	Possible regressions

	* {igt@xe_oa@mi-rpc} (NEW):

	 * bat-atsm-2: NOTRUN -> INCOMPLETE +1 other test incomplete

	* {igt@xe_oa@mi-rpc@ccs-0} (NEW):

	 * bat-pvc-2: NOTRUN -> INCOMPLETE +1 other test incomplete
	 * bat-dg2-oem2: NOTRUN -> INCOMPLETE +1 other test incomplete

	* {igt@xe_oa@mmio-triggered-reports} (NEW):

	 * bat-adlp-7: NOTRUN -> SKIP

	* {igt@xe_oa@non-zero-reason} (NEW):

	 * bat-pvc-2: NOTRUN -> FAIL +6 other tests fail
	 * bat-dg2-oem2: NOTRUN -> FAIL +1 other test fail

	* {igt@xe_oa@oa-formats} (NEW):

	 * bat-pvc-2: NOTRUN -> TIMEOUT +1 other test timeout

	* {igt@xe_oa@oa-tlb-invalidate} (NEW):

	 * {bat-lnl-1}: NOTRUN -> SKIP +1 other test skip
	 * bat-pvc-2: NOTRUN -> SKIP +1 other test skip

	* {igt@xe_oa@polling-small-buf} (NEW):

	 * bat-atsm-2: NOTRUN -> FAIL

	* {igt@xe_oa@rc6-disable} (NEW):

	 * bat-atsm-2: NOTRUN -> SKIP

Mostly similar to those we see in i915 for Xe1.

One idea is to run these xe_oa IGT's only for Xe2 where things seem to be
more stable, that is only for xe KMD supported platforms. Things seem to be
more stable for Xe2, maybe because we don't know how to check Xe2 PEC
counters, like we do for Xe1 in sanity_check_reports. Or simplify the
checks for Xe1, e.g. get rid of sanity_check_reports? And simplify some of
the other asserts.

Or merge these first and as part of fixing the bugs see what to do for the
tests, so that we'll have a record in git of what we did and why?

Thanks.
--
Ashutosh

^ permalink raw reply	[flat|nested] 26+ messages in thread

* ✗ Fi.CI.IGT: failure for Intel Xe OA IGT's (rev7)
  2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
                   ` (16 preceding siblings ...)
  2024-07-01  5:00 ` ✗ CI.xeFULL: failure " Patchwork
@ 2024-07-01  5:36 ` Patchwork
  17 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2024-07-01  5:36 UTC (permalink / raw)
  To: Ashutosh Dixit; +Cc: igt-dev

[-- Attachment #1: Type: text/plain, Size: 88475 bytes --]

== Series Details ==

Series: Intel Xe OA IGT's (rev7)
URL   : https://patchwork.freedesktop.org/series/130033/
State : failure

== Summary ==

CI Bug Log - changes from IGT_7908_full -> IGTPW_11343_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_11343_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_11343_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/index.html

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_11343_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_workarounds@suspend-resume:
    - shard-tglu:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-tglu-6/igt@gem_workarounds@suspend-resume.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-7/igt@gem_workarounds@suspend-resume.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][3] +2 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-dg2:          NOTRUN -> [SKIP][4] +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-dg1:          NOTRUN -> [SKIP][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][6] -> [INCOMPLETE][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-glk5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ac-hdmi-a1-hdmi-a2.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-glk5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ac-hdmi-a1-hdmi-a2.html

  
#### Warnings ####

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-dg2:          [SKIP][8] ([i915#4235]) -> [SKIP][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg2-11/igt@kms_rotation_crc@primary-rotation-270.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@kms_rotation_crc@primary-rotation-270.html

  
New tests
---------

  New tests have been introduced between IGT_7908_full and IGTPW_11343_full:

### New IGT tests (12) ###

  * igt@gem_create@create-ext-cpu-access-big:
    - Statuses : 1 abort(s) 1 pass(s) 4 skip(s)
    - Exec time: [0.0, 1.02] s

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - Statuses : 2 pass(s) 5 skip(s)
    - Exec time: [0.0, 0.02] s

  * igt@gem_exec_capture@capture-recoverable:
    - Statuses : 1 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@i915_query@query-regions-unallocated:
    - Statuses : 6 pass(s)
    - Exec time: [0.0, 0.71] s

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-a-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.65] s

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-b-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.53] s

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.52] s

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.52] s

  * igt@kms_pipe_crc_basic@read-crc@pipe-a-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.60] s

  * igt@kms_pipe_crc_basic@read-crc@pipe-b-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.48] s

  * igt@kms_pipe_crc_basic@read-crc@pipe-c-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.45] s

  * igt@kms_pipe_crc_basic@read-crc@pipe-d-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.44] s

  

Known issues
------------

  Here are the changes found in IGTPW_11343_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-dg1:          NOTRUN -> [SKIP][10] ([i915#8411])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@device_reset@cold-reset-bound:
    - shard-dg1:          NOTRUN -> [SKIP][11] ([i915#11078])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@device_reset@cold-reset-bound.html

  * igt@drm_fdinfo@busy-check-all@bcs0:
    - shard-dg1:          NOTRUN -> [SKIP][12] ([i915#8414]) +10 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@drm_fdinfo@busy-check-all@bcs0.html

  * igt@drm_fdinfo@busy-check-all@ccs0:
    - shard-mtlp:         NOTRUN -> [SKIP][13] ([i915#8414]) +11 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-3/igt@drm_fdinfo@busy-check-all@ccs0.html

  * igt@drm_fdinfo@idle@rcs0:
    - shard-rkl:          NOTRUN -> [FAIL][14] ([i915#7742])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-2/igt@drm_fdinfo@idle@rcs0.html

  * igt@drm_fdinfo@most-busy-check-all@bcs0:
    - shard-dg2:          NOTRUN -> [SKIP][15] ([i915#8414]) +28 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@drm_fdinfo@most-busy-check-all@bcs0.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-rkl:          NOTRUN -> [SKIP][16] ([i915#3555] / [i915#9323])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-rkl:          NOTRUN -> [SKIP][17] ([i915#9323])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-dg2:          NOTRUN -> [SKIP][18] ([i915#7697])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-7/igt@gem_close_race@multigpu-basic-threads.html
    - shard-dg1:          NOTRUN -> [SKIP][19] ([i915#7697])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_create@create-ext-cpu-access-big (NEW):
    - shard-rkl:          NOTRUN -> [SKIP][20] ([i915#6335])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-2/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_create@create-ext-set-pat:
    - shard-dg2:          NOTRUN -> [SKIP][21] ([i915#8562])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-6/igt@gem_create@create-ext-set-pat.html
    - shard-rkl:          NOTRUN -> [SKIP][22] ([i915#8562])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglu:         [PASS][23] -> [FAIL][24] ([i915#6268])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_persistence@engines-hostile-preempt:
    - shard-snb:          NOTRUN -> [SKIP][25] ([i915#1099]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-snb5/igt@gem_ctx_persistence@engines-hostile-preempt.html

  * igt@gem_ctx_persistence@hang:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#8555])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-11/igt@gem_ctx_persistence@hang.html
    - shard-dg1:          NOTRUN -> [SKIP][27] ([i915#8555])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@gem_ctx_persistence@hang.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-dg1:          NOTRUN -> [SKIP][28] ([i915#280])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@gem_ctx_sseu@invalid-args.html
    - shard-mtlp:         NOTRUN -> [SKIP][29] ([i915#280])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-5/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#280]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@gem_ctx_sseu@mmap-args.html
    - shard-rkl:          NOTRUN -> [SKIP][31] ([i915#280]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_eio@kms:
    - shard-dg2:          NOTRUN -> [FAIL][32] ([i915#5784])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-6/igt@gem_eio@kms.html

  * igt@gem_eio@reset-stress:
    - shard-dg2:          [PASS][33] -> [FAIL][34] ([i915#5784])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg2-10/igt@gem_eio@reset-stress.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@gem_eio@reset-stress.html

  * igt@gem_exec_balancer@bonded-semaphore:
    - shard-dg1:          NOTRUN -> [SKIP][35] ([i915#4812]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-13/igt@gem_exec_balancer@bonded-semaphore.html
    - shard-dg2:          NOTRUN -> [SKIP][36] ([i915#4812]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@gem_exec_balancer@bonded-semaphore.html

  * igt@gem_exec_balancer@hog:
    - shard-mtlp:         NOTRUN -> [SKIP][37] ([i915#4812])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-2/igt@gem_exec_balancer@hog.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#4036])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-5/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-rkl:          NOTRUN -> [SKIP][39] ([i915#4525]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_capture@capture-invisible@lmem0:
    - shard-dg2:          NOTRUN -> [SKIP][40] ([i915#6334]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-8/igt@gem_exec_capture@capture-invisible@lmem0.html

  * igt@gem_exec_capture@capture@vecs0-lmem0:
    - shard-dg1:          NOTRUN -> [FAIL][41] ([i915#10386]) +1 other test fail
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@gem_exec_capture@capture@vecs0-lmem0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-rkl:          [PASS][42] -> [FAIL][43] ([i915#2846])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-rkl-3/igt@gem_exec_fair@basic-deadline.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-flow:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#3539] / [i915#4852]) +3 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-6/igt@gem_exec_fair@basic-flow.html

  * igt@gem_exec_fair@basic-none:
    - shard-mtlp:         NOTRUN -> [SKIP][45] ([i915#4473] / [i915#4771])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-8/igt@gem_exec_fair@basic-none.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][46] ([i915#2842]) +2 other tests fail
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none@bcs0:
    - shard-rkl:          NOTRUN -> [FAIL][47] ([i915#2842]) +5 other tests fail
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@gem_exec_fair@basic-none@bcs0.html

  * igt@gem_exec_fair@basic-pace-solo:
    - shard-dg2:          NOTRUN -> [SKIP][48] ([i915#3539]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-7/igt@gem_exec_fair@basic-pace-solo.html

  * igt@gem_exec_flush@basic-uc-prw-default:
    - shard-dg1:          NOTRUN -> [SKIP][49] ([i915#3539]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@gem_exec_flush@basic-uc-prw-default.html

  * igt@gem_exec_flush@basic-wb-ro-before-default:
    - shard-dg1:          NOTRUN -> [SKIP][50] ([i915#3539] / [i915#4852])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@gem_exec_flush@basic-wb-ro-before-default.html

  * igt@gem_exec_reloc@basic-active:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#3281]) +10 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@gem_exec_reloc@basic-active.html

  * igt@gem_exec_reloc@basic-wc-read-active:
    - shard-dg1:          NOTRUN -> [SKIP][52] ([i915#3281]) +9 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@gem_exec_reloc@basic-wc-read-active.html

  * igt@gem_exec_reloc@basic-wc-read-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][53] ([i915#3281]) +10 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-1/igt@gem_exec_reloc@basic-wc-read-noreloc.html

  * igt@gem_exec_reloc@basic-write-cpu-noreloc:
    - shard-mtlp:         NOTRUN -> [SKIP][54] ([i915#3281]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-6/igt@gem_exec_reloc@basic-write-cpu-noreloc.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#4537] / [i915#4812])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@gem_exec_schedule@preempt-queue-contexts-chain.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy:
    - shard-dg1:          NOTRUN -> [SKIP][56] ([i915#4860]) +5 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][57] ([i915#4860]) +2 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html

  * igt@gem_huc_copy@huc-copy:
    - shard-rkl:          NOTRUN -> [SKIP][58] ([i915#2190])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-tglu:         NOTRUN -> [SKIP][59] ([i915#4613])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-3/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-multi@lmem0:
    - shard-dg1:          NOTRUN -> [FAIL][60] ([i915#10378]) +1 other test fail
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@gem_lmem_swapping@heavy-multi@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
    - shard-dg2:          NOTRUN -> [FAIL][61] ([i915#10378])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-random@lmem0:
    - shard-dg2:          [PASS][62] -> [FAIL][63] ([i915#10378])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg2-11/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-rkl:          NOTRUN -> [SKIP][64] ([i915#4613]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          [PASS][65] -> [TIMEOUT][66] ([i915#5493])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg2-11/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_lmem_swapping@verify-ccs@lmem0:
    - shard-dg1:          NOTRUN -> [SKIP][67] ([i915#4565]) +1 other test skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@gem_lmem_swapping@verify-ccs@lmem0.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-glk:          NOTRUN -> [SKIP][68] ([i915#4613]) +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-glk7/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_media_fill@media-fill:
    - shard-mtlp:         NOTRUN -> [SKIP][69] ([i915#8289])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-7/igt@gem_media_fill@media-fill.html
    - shard-dg2:          NOTRUN -> [SKIP][70] ([i915#8289])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@gem_media_fill@media-fill.html

  * igt@gem_mmap_gtt@basic-small-copy-xy:
    - shard-mtlp:         NOTRUN -> [SKIP][71] ([i915#4077]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-6/igt@gem_mmap_gtt@basic-small-copy-xy.html

  * igt@gem_mmap_wc@fault-concurrent:
    - shard-dg2:          NOTRUN -> [SKIP][72] ([i915#4083]) +4 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-7/igt@gem_mmap_wc@fault-concurrent.html
    - shard-mtlp:         NOTRUN -> [SKIP][73] ([i915#4083])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-7/igt@gem_mmap_wc@fault-concurrent.html

  * igt@gem_mmap_wc@read-write-distinct:
    - shard-dg1:          NOTRUN -> [SKIP][74] ([i915#4083]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@gem_mmap_wc@read-write-distinct.html

  * igt@gem_partial_pwrite_pread@write-display:
    - shard-mtlp:         NOTRUN -> [SKIP][75] ([i915#3282]) +1 other test skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-1/igt@gem_partial_pwrite_pread@write-display.html

  * igt@gem_pread@self:
    - shard-dg1:          NOTRUN -> [SKIP][76] ([i915#3282]) +2 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@gem_pread@self.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-rkl:          NOTRUN -> [SKIP][77] ([i915#3282]) +3 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@gem_pwrite@basic-exhaustion.html
    - shard-glk:          NOTRUN -> [WARN][78] ([i915#2658])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-glk4/igt@gem_pwrite@basic-exhaustion.html
    - shard-dg2:          NOTRUN -> [SKIP][79] ([i915#3282]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@create-protected-buffer:
    - shard-dg1:          NOTRUN -> [SKIP][80] ([i915#4270]) +4 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@gem_pxp@create-protected-buffer.html
    - shard-tglu:         NOTRUN -> [SKIP][81] ([i915#4270])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-7/igt@gem_pxp@create-protected-buffer.html

  * igt@gem_pxp@create-regular-buffer:
    - shard-mtlp:         NOTRUN -> [SKIP][82] ([i915#4270]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-6/igt@gem_pxp@create-regular-buffer.html

  * igt@gem_pxp@display-protected-crc:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#4270]) +5 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@gem_pxp@display-protected-crc.html
    - shard-rkl:          NOTRUN -> [SKIP][84] ([i915#4270]) +3 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@gem_pxp@display-protected-crc.html

  * igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([i915#5190] / [i915#8428]) +5 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-6/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][86] ([i915#4079])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
    - shard-rkl:          NOTRUN -> [SKIP][87] ([i915#8411]) +2 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg1:          NOTRUN -> [SKIP][88] ([i915#4079])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_tiled_partial_pwrite_pread@writes:
    - shard-dg2:          NOTRUN -> [SKIP][89] ([i915#4077]) +13 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-7/igt@gem_tiled_partial_pwrite_pread@writes.html

  * igt@gem_tiled_partial_pwrite_pread@writes-after-reads:
    - shard-dg1:          NOTRUN -> [SKIP][90] ([i915#4077]) +12 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@gem_tiled_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_userptr_blits@access-control:
    - shard-tglu:         NOTRUN -> [SKIP][91] ([i915#3297])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-6/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@forbidden-operations:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#3282] / [i915#3297])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-7/igt@gem_userptr_blits@forbidden-operations.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-dg1:          NOTRUN -> [SKIP][93] ([i915#3297] / [i915#4880])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap:
    - shard-dg2:          NOTRUN -> [SKIP][94] ([i915#3297] / [i915#4880])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@gem_userptr_blits@map-fixed-invalidate-overlap.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-mtlp:         NOTRUN -> [SKIP][95] ([i915#3297])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-3/igt@gem_userptr_blits@unsync-overlap.html
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#3297]) +2 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-rkl:          NOTRUN -> [SKIP][97] ([i915#3297]) +1 other test skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@gem_userptr_blits@unsync-unmap-cycles.html
    - shard-dg1:          NOTRUN -> [SKIP][98] ([i915#3297]) +2 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen7_exec_parse@chained-batch:
    - shard-rkl:          NOTRUN -> [SKIP][99] +35 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@gen7_exec_parse@chained-batch.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-rkl:          NOTRUN -> [SKIP][100] ([i915#2527]) +3 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@gen9_exec_parse@bb-chained.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-dg1:          NOTRUN -> [SKIP][101] ([i915#2527])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@gen9_exec_parse@bb-start-cmd.html
    - shard-mtlp:         NOTRUN -> [SKIP][102] ([i915#2856])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-4/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#2856]) +3 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-5/igt@gen9_exec_parse@secure-batches.html
    - shard-tglu:         NOTRUN -> [SKIP][104] ([i915#2527] / [i915#2856])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-3/igt@gen9_exec_parse@secure-batches.html

  * igt@i915_fb_tiling:
    - shard-dg2:          NOTRUN -> [SKIP][105] ([i915#4881])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-6/igt@i915_fb_tiling.html
    - shard-dg1:          NOTRUN -> [SKIP][106] ([i915#4881])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@i915_fb_tiling.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-snb:          [PASS][107] -> [ABORT][108] ([i915#9820])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html
    - shard-tglu:         [PASS][109] -> [ABORT][110] ([i915#10887] / [i915#9820])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-tglu-7/igt@i915_module_load@reload-with-fault-injection.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-10/igt@i915_module_load@reload-with-fault-injection.html
    - shard-mtlp:         NOTRUN -> [ABORT][111] ([i915#10131] / [i915#9820])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-rkl:          NOTRUN -> [SKIP][112] ([i915#6590])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-1/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
    - shard-dg1:          NOTRUN -> [FAIL][113] ([i915#3591]) +1 other test fail
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html

  * igt@i915_pm_rps@min-max-config-idle:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#6621])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@i915_pm_rps@min-max-config-idle.html
    - shard-dg1:          NOTRUN -> [SKIP][115] ([i915#6621])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@i915_pm_rps@min-max-config-idle.html

  * igt@i915_pm_rps@thresholds-idle@gt0:
    - shard-dg1:          NOTRUN -> [SKIP][116] ([i915#8925])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@i915_pm_rps@thresholds-idle@gt0.html

  * igt@i915_pm_rps@thresholds@gt0:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#8925])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@i915_pm_rps@thresholds@gt0.html

  * igt@i915_pm_sseu@full-enable:
    - shard-mtlp:         NOTRUN -> [SKIP][118] ([i915#8437])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-5/igt@i915_pm_sseu@full-enable.html

  * igt@i915_query@query-topology-coherent-slice-mask:
    - shard-dg2:          NOTRUN -> [SKIP][119] ([i915#6188])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@i915_query@query-topology-coherent-slice-mask.html

  * igt@i915_selftest@mock@memory_region:
    - shard-dg2:          NOTRUN -> [DMESG-WARN][120] ([i915#9311])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@i915_selftest@mock@memory_region.html
    - shard-rkl:          NOTRUN -> [DMESG-WARN][121] ([i915#9311])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@i915_selftest@mock@memory_region.html

  * igt@intel_hwmon@hwmon-write:
    - shard-rkl:          NOTRUN -> [SKIP][122] ([i915#7707])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-2/igt@intel_hwmon@hwmon-write.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][123] ([i915#4212]) +1 other test skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-7/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#4215] / [i915#5190])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - shard-dg1:          NOTRUN -> [SKIP][125] ([i915#4212]) +1 other test skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][126] ([i915#8709]) +3 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([i915#8709]) +11 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-mtlp:         NOTRUN -> [SKIP][128] ([i915#3555])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-3/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-dg2:          NOTRUN -> [SKIP][129] ([i915#1769] / [i915#3555])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
    - shard-dg1:          NOTRUN -> [SKIP][130] ([i915#1769] / [i915#3555])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
    - shard-tglu:         NOTRUN -> [SKIP][131] ([i915#1769] / [i915#3555])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-8/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-180:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([i915#5286]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-6/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-dg1:          NOTRUN -> [SKIP][133] ([i915#5286])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-rkl:          NOTRUN -> [SKIP][134] ([i915#5286]) +6 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-dg1:          NOTRUN -> [SKIP][135] ([i915#4538] / [i915#5286]) +3 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][136] ([i915#3638]) +6 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][137] ([i915#3638]) +3 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#4538] / [i915#5190]) +16 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-11/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
    - shard-tglu:         NOTRUN -> [SKIP][139] +19 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-8/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][140] +3 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][141] ([i915#4538]) +4 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_joiner@basic:
    - shard-dg2:          NOTRUN -> [SKIP][142] ([i915#10656]) +1 other test skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-5/igt@kms_big_joiner@basic.html

  * igt@kms_big_joiner@basic-force-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][143] ([i915#10656])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-5/igt@kms_big_joiner@basic-force-joiner.html
    - shard-dg1:          NOTRUN -> [SKIP][144] ([i915#10656])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@kms_big_joiner@basic-force-joiner.html

  * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-d-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][145] ([i915#10307] / [i915#6095]) +188 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-d-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][146] ([i915#6095]) +75 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-13/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][147] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-8/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][148] ([i915#6095]) +63 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][149] ([i915#6095]) +11 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-8/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][150] ([i915#7213]) +3 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2.html

  * igt@kms_cdclk@plane-scaling@pipe-d-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][151] ([i915#4087]) +3 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-11/igt@kms_cdclk@plane-scaling@pipe-d-dp-4.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-dg1:          NOTRUN -> [SKIP][152] ([i915#7828]) +7 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][153] ([i915#7828]) +12 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-1/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium_frames@hdmi-crc-multiple:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#7828]) +8 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-4/igt@kms_chamelium_frames@hdmi-crc-multiple.html

  * igt@kms_chamelium_frames@hdmi-crc-single:
    - shard-tglu:         NOTRUN -> [SKIP][155] ([i915#7828])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-8/igt@kms_chamelium_frames@hdmi-crc-single.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][156] ([i915#7828]) +2 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-2/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_content_protection@content-type-change:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([i915#9424])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][158] ([i915#3299])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@kms_content_protection@dp-mst-lic-type-0.html
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#3116])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-1/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-dg1:          NOTRUN -> [SKIP][160] ([i915#3299])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][161] ([i915#6944] / [i915#9424])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-4/igt@kms_content_protection@legacy.html
    - shard-dg1:          NOTRUN -> [SKIP][162] ([i915#7116] / [i915#9424])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@legacy@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][163] ([i915#7173])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-11/igt@kms_content_protection@legacy@pipe-a-dp-4.html

  * igt@kms_content_protection@uevent:
    - shard-rkl:          NOTRUN -> [SKIP][164] ([i915#7118] / [i915#9424]) +1 other test skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][165] ([i915#3555]) +6 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
    - shard-mtlp:         NOTRUN -> [SKIP][166] ([i915#3555] / [i915#8814]) +1 other test skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-8/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-max-size:
    - shard-dg1:          NOTRUN -> [SKIP][167] ([i915#3555]) +2 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-dg2:          NOTRUN -> [SKIP][168] ([i915#3555]) +4 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][169] ([i915#9809]) +1 other test skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-5/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-dg1:          NOTRUN -> [SKIP][170] ([i915#4103] / [i915#4213])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
    - shard-tglu:         NOTRUN -> [SKIP][171] ([i915#4103])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
    - shard-dg2:          NOTRUN -> [SKIP][172] ([i915#4103] / [i915#4213])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@torture-move@pipe-a:
    - shard-snb:          [PASS][173] -> [DMESG-WARN][174] ([i915#10166])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-snb6/igt@kms_cursor_legacy@torture-move@pipe-a.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-snb6/igt@kms_cursor_legacy@torture-move@pipe-a.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-dg1:          NOTRUN -> [SKIP][175] ([i915#9723])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-dg2:          NOTRUN -> [SKIP][176] ([i915#9833])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-8/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-rkl:          NOTRUN -> [SKIP][177] ([i915#8588])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][178] ([i915#3804])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dp_aux_dev:
    - shard-rkl:          NOTRUN -> [SKIP][179] ([i915#1257])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@kms_dp_aux_dev.html

  * igt@kms_draw_crc@draw-method-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][180] ([i915#8812])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@kms_draw_crc@draw-method-mmap-gtt.html
    - shard-mtlp:         NOTRUN -> [SKIP][181] ([i915#3555] / [i915#8812])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-1/igt@kms_draw_crc@draw-method-mmap-gtt.html
    - shard-dg2:          NOTRUN -> [SKIP][182] ([i915#8812])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-4/igt@kms_draw_crc@draw-method-mmap-gtt.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-dg2:          NOTRUN -> [SKIP][183] ([i915#3840])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
    - shard-rkl:          NOTRUN -> [SKIP][184] ([i915#3840])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-dg2:          NOTRUN -> [SKIP][185] ([i915#3555] / [i915#3840]) +1 other test skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-7/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          NOTRUN -> [SKIP][186] ([i915#3555] / [i915#3840])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][187] ([i915#3955])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-3x:
    - shard-mtlp:         NOTRUN -> [SKIP][188] ([i915#1839])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-2/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-dg1:          NOTRUN -> [SKIP][189] ([i915#1839]) +1 other test skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@kms_feature_discovery@display-4x.html
    - shard-dg2:          NOTRUN -> [SKIP][190] ([i915#1839])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][191] ([i915#8381])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-2/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][192] ([i915#9934]) +7 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-13/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
    - shard-tglu:         NOTRUN -> [SKIP][193] ([i915#3637]) +3 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][194] ([i915#8381])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][195] ([i915#2587] / [i915#2672])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][196] ([i915#2672]) +3 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][197] ([i915#2672]) +1 other test skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][198] ([i915#2587] / [i915#2672]) +3 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][199] ([i915#2672] / [i915#3555])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][200] ([i915#2672] / [i915#3555])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-rte:
    - shard-dg2:          NOTRUN -> [SKIP][201] ([i915#5354]) +45 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][202] ([i915#8708]) +11 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][203] ([i915#8708]) +16 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
    - shard-dg1:          NOTRUN -> [SKIP][204] +46 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
    - shard-mtlp:         NOTRUN -> [SKIP][205] ([i915#1825]) +8 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][206] ([i915#1825]) +41 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][207] ([i915#5439])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-rkl:          NOTRUN -> [SKIP][208] ([i915#9766])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
    - shard-dg2:          NOTRUN -> [SKIP][209] ([i915#9766])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][210] ([i915#3023]) +29 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][211] ([i915#3458]) +21 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-snb:          NOTRUN -> [SKIP][212] +34 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-snb2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
    - shard-dg1:          NOTRUN -> [SKIP][213] ([i915#3458]) +13 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][214] ([i915#8708]) +1 other test skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][215] ([i915#6118])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-dg1:          NOTRUN -> [SKIP][216] ([i915#3555] / [i915#8228]) +1 other test skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@kms_hdr@bpc-switch-dpms.html
    - shard-tglu:         NOTRUN -> [SKIP][217] ([i915#3555] / [i915#8228])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-7/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-rkl:          NOTRUN -> [SKIP][218] ([i915#3555] / [i915#8228])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-2/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][219] ([i915#3555] / [i915#8228]) +2 other tests skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-6/igt@kms_hdr@static-toggle.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-rkl:          NOTRUN -> [SKIP][220] ([i915#6301])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@kms_panel_fitting@atomic-fastset.html
    - shard-dg1:          NOTRUN -> [SKIP][221] ([i915#6301]) +1 other test skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
    - shard-dg2:          NOTRUN -> [SKIP][222] +24 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-8/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-dg2:          NOTRUN -> [SKIP][223] ([i915#3555] / [i915#8821])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-4/igt@kms_plane_lowres@tiling-yf.html
    - shard-mtlp:         NOTRUN -> [SKIP][224] ([i915#3555] / [i915#8821])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-8/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-dg2:          NOTRUN -> [SKIP][225] ([i915#5354] / [i915#9423])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-4/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2:          NOTRUN -> [SKIP][226] ([i915#6953] / [i915#9423])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][227] ([i915#9423]) +3 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][228] ([i915#9423]) +11 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][229] ([i915#9423]) +3 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-7/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][230] ([i915#9423]) +1 other test skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][231] ([i915#5176]) +1 other test skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#5176] / [i915#9423]) +1 other test skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][233] ([i915#5235]) +11 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][234] ([i915#5235] / [i915#9423]) +23 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][235] ([i915#5235]) +7 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          NOTRUN -> [SKIP][236] ([i915#5354])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-5/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-dg1:          NOTRUN -> [SKIP][237] ([i915#5354]) +1 other test skip
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg2:          NOTRUN -> [SKIP][238] ([i915#9685])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@kms_pm_dc@dc3co-vpb-simulation.html
    - shard-rkl:          NOTRUN -> [SKIP][239] ([i915#9685]) +1 other test skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][240] ([i915#9519])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-6/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][241] ([i915#9519]) +1 other test skip
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          [PASS][242] -> [SKIP][243] ([i915#9519])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [PASS][244] -> [SKIP][245] ([i915#9519]) +1 other test skip
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-dg1:          NOTRUN -> [SKIP][246] ([i915#6524]) +1 other test skip
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-mtlp:         NOTRUN -> [SKIP][247] ([i915#6524])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-7/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
    - shard-dg2:          NOTRUN -> [SKIP][248] ([i915#11520]) +3 other tests skip
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-7/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-rkl:          NOTRUN -> [SKIP][249] ([i915#11520]) +4 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-1/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf:
    - shard-tglu:         NOTRUN -> [SKIP][250] ([i915#11520])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-6/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf:
    - shard-dg1:          NOTRUN -> [SKIP][251] ([i915#11520]) +4 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2:          NOTRUN -> [SKIP][252] ([i915#9683]) +2 other tests skip
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@kms_psr2_su@page_flip-p010.html
    - shard-rkl:          NOTRUN -> [SKIP][253] ([i915#9683])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr-cursor-plane-move:
    - shard-dg2:          NOTRUN -> [SKIP][254] ([i915#1072] / [i915#9732]) +22 other tests skip
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-5/igt@kms_psr@fbc-psr-cursor-plane-move.html

  * igt@kms_psr@fbc-psr-primary-page-flip@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][255] ([i915#9688]) +2 other tests skip
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-5/igt@kms_psr@fbc-psr-primary-page-flip@edp-1.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-rkl:          NOTRUN -> [SKIP][256] ([i915#1072] / [i915#9732]) +23 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@pr-cursor-plane-onoff:
    - shard-dg1:          NOTRUN -> [SKIP][257] ([i915#1072] / [i915#9732]) +21 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@kms_psr@pr-cursor-plane-onoff.html

  * igt@kms_psr@pr-sprite-plane-move:
    - shard-tglu:         NOTRUN -> [SKIP][258] ([i915#9732]) +5 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-8/igt@kms_psr@pr-sprite-plane-move.html

  * igt@kms_psr@psr2-sprite-plane-onoff:
    - shard-glk:          NOTRUN -> [SKIP][259] +203 other tests skip
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-glk4/igt@kms_psr@psr2-sprite-plane-onoff.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-mtlp:         NOTRUN -> [SKIP][260] ([i915#5289])
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg2:          NOTRUN -> [SKIP][261] ([i915#4235] / [i915#5190])
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-11/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg2:          NOTRUN -> [SKIP][262] ([i915#5190]) +1 other test skip
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
    - shard-rkl:          NOTRUN -> [SKIP][263] ([i915#5289])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-mtlp:         NOTRUN -> [SKIP][264] ([i915#4235])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-6/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-tglu:         NOTRUN -> [SKIP][265] ([i915#3555]) +1 other test skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-5/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_setmode@basic@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [FAIL][266] ([i915#5465]) +1 other test fail
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@kms_setmode@basic@pipe-a-hdmi-a-4.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg1:          NOTRUN -> [SKIP][267] ([i915#8623])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@kms_tiled_display@basic-test-pattern.html
    - shard-rkl:          NOTRUN -> [SKIP][268] ([i915#8623])
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
    - shard-tglu:         [PASS][269] -> [FAIL][270] ([i915#9196])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html

  * igt@kms_vrr@max-min:
    - shard-dg1:          NOTRUN -> [SKIP][271] ([i915#9906]) +2 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@kms_vrr@max-min.html
    - shard-dg2:          NOTRUN -> [SKIP][272] ([i915#9906])
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-8/igt@kms_vrr@max-min.html

  * igt@kms_vrr@negative-basic:
    - shard-dg2:          NOTRUN -> [SKIP][273] ([i915#3555] / [i915#9906])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-rkl:          NOTRUN -> [SKIP][274] ([i915#9906])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-5/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-rkl:          NOTRUN -> [SKIP][275] ([i915#2437])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@kms_writeback@writeback-fb-id.html
    - shard-dg1:          NOTRUN -> [SKIP][276] ([i915#2437])
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-15/igt@kms_writeback@writeback-fb-id.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-dg2:          NOTRUN -> [SKIP][277] ([i915#2437])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@perf@mi-rpc:
    - shard-mtlp:         NOTRUN -> [SKIP][278] ([i915#2434])
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-8/igt@perf@mi-rpc.html

  * igt@perf_pmu@busy-double-start@bcs0:
    - shard-mtlp:         [PASS][279] -> [FAIL][280] ([i915#4349])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-mtlp-1/igt@perf_pmu@busy-double-start@bcs0.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-4/igt@perf_pmu@busy-double-start@bcs0.html

  * igt@perf_pmu@cpu-hotplug:
    - shard-rkl:          NOTRUN -> [SKIP][281] ([i915#8850])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-2/igt@perf_pmu@cpu-hotplug.html
    - shard-dg1:          NOTRUN -> [SKIP][282] ([i915#8850])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-17/igt@perf_pmu@cpu-hotplug.html

  * igt@perf_pmu@event-wait@rcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][283] ([i915#3555] / [i915#8807])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-2/igt@perf_pmu@event-wait@rcs0.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-dg1:          NOTRUN -> [SKIP][284] ([i915#8516])
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@perf_pmu@rc6-all-gts.html
    - shard-rkl:          NOTRUN -> [SKIP][285] ([i915#8516])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-3/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
    - shard-dg2:          NOTRUN -> [CRASH][286] ([i915#9351])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-2/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html

  * igt@prime_vgem@basic-fence-flip:
    - shard-dg1:          NOTRUN -> [SKIP][287] ([i915#3708]) +1 other test skip
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-read:
    - shard-dg2:          NOTRUN -> [SKIP][288] ([i915#3291] / [i915#3708])
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-4/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-read:
    - shard-rkl:          NOTRUN -> [SKIP][289] ([i915#3291] / [i915#3708])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-5/igt@prime_vgem@basic-read.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-dg2:          NOTRUN -> [SKIP][290] ([i915#9917])
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-5/igt@sriov_basic@enable-vfs-autoprobe-off.html
    - shard-tglu:         NOTRUN -> [SKIP][291] ([i915#9917])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-6/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@syncobj_timeline@invalid-wait-zero-handles:
    - shard-rkl:          NOTRUN -> [FAIL][292] ([i915#9781])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-1/igt@syncobj_timeline@invalid-wait-zero-handles.html
    - shard-dg1:          NOTRUN -> [FAIL][293] ([i915#9781])
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-13/igt@syncobj_timeline@invalid-wait-zero-handles.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
    - shard-rkl:          [FAIL][294] ([i915#7742]) -> [PASS][295]
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-rkl:          [FAIL][296] ([i915#2842]) -> [PASS][297]
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_lmem_swapping@heavy-random@lmem0:
    - shard-dg1:          [FAIL][298] ([i915#10378]) -> [PASS][299]
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg1-13/igt@gem_lmem_swapping@heavy-random@lmem0.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@gem_lmem_swapping@heavy-random@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0:
    - shard-dg2:          [FAIL][300] ([i915#10378]) -> [PASS][301]
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg2-10/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-6/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [TIMEOUT][302] ([i915#5493]) -> [PASS][303]
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@i915_selftest@live@sanitycheck:
    - shard-snb:          [ABORT][304] -> [PASS][305]
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-snb4/igt@i915_selftest@live@sanitycheck.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-snb4/igt@i915_selftest@live@sanitycheck.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [FAIL][306] ([i915#10031] / [i915#11279]) -> [PASS][307]
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [FAIL][308] ([i915#2346]) -> [PASS][309]
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         [SKIP][310] ([i915#4281]) -> [PASS][311]
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-tglu-8/igt@kms_pm_dc@dc9-dpms.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-tglu-6/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [SKIP][312] ([i915#9519]) -> [PASS][313] +1 other test pass
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-rkl-1/igt@kms_pm_rpm@dpms-lpsp.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-rkl-2/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg2:          [SKIP][314] ([i915#9519]) -> [PASS][315] +1 other test pass
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg2-10/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-3/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_setmode@basic@pipe-a-hdmi-a-1:
    - shard-snb:          [FAIL][316] ([i915#5465]) -> [PASS][317] +1 other test pass
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-snb2/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-snb7/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-mtlp:         [INCOMPLETE][318] ([i915#9853]) -> [PASS][319]
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-mtlp-3/igt@perf_pmu@rc6@other-idle-gt0.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-mtlp-3/igt@perf_pmu@rc6@other-idle-gt0.html

  
#### Warnings ####

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          [SKIP][320] ([i915#9433]) -> [SKIP][321] ([i915#9424])
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg1-13/igt@kms_content_protection@mei-interface.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg1-18/igt@kms_content_protection@mei-interface.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-dg2:          [SKIP][322] ([i915#10433] / [i915#3458]) -> [SKIP][323] ([i915#3458])
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_psr@pr-cursor-mmap-cpu:
    - shard-dg2:          [SKIP][324] ([i915#1072] / [i915#9732]) -> [SKIP][325] ([i915#1072] / [i915#9673] / [i915#9732]) +2 other tests skip
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg2-3/igt@kms_psr@pr-cursor-mmap-cpu.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-11/igt@kms_psr@pr-cursor-mmap-cpu.html

  * igt@kms_psr@psr-cursor-render:
    - shard-dg2:          [SKIP][326] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][327] ([i915#1072] / [i915#9732]) +12 other tests skip
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7908/shard-dg2-11/igt@kms_psr@psr-cursor-render.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/shard-dg2-1/igt@kms_psr@psr-cursor-render.html

  
  [i915#10031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10031
  [i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
  [i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
  [i915#10386]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10386
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11279]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11279
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
  [i915#4036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4036
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
  [i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4473]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4473
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
  [i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5465
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6118
  [i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
  [i915#6268]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6268
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8289
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8437
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8807]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8807
  [i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
  [i915#8850]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8850
  [i915#8925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8925
  [i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
  [i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
  [i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
  [i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
  [i915#9853]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9853
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7908 -> IGTPW_11343

  CI-20190529: 20190529
  CI_DRM_15013: 0318a12ff6fb8c321458aa2b373e9322896ee951 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_11343: 11343
  IGT_7908: 7908

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11343/index.html

[-- Attachment #2: Type: text/html, Size: 110509 bytes --]

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end of thread, other threads:[~2024-07-01 23:13 UTC | newest]

Thread overview: 26+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
2024-07-01  2:52 ` [PATCH i-g-t 01/14] lib/xe/oa: Add PVC support Ashutosh Dixit
2024-07-01 19:52   ` Umesh Nerlige Ramappa
2024-07-01  2:52 ` [PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests Ashutosh Dixit
2024-07-01 16:53   ` Dixit, Ashutosh
2024-07-01 19:47   ` Umesh Nerlige Ramappa
2024-07-01 22:31     ` Dixit, Ashutosh
2024-07-01  2:52 ` [PATCH i-g-t 03/14] tests/intel/xe_oa: Add some negative tests Ashutosh Dixit
2024-07-01  2:52 ` [PATCH i-g-t 04/14] tests/intel/xe_oa: Add "oa-formats" subtest Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 05/14] tests/intel/xe_oa: Add oa exponent tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 06/14] tests/intel/xe_oa: buffer-fill, non-zero-reason, enable-disable Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 07/14] tests/intel/xe_oa: blocking and polling tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 08/14] tests/intel/xe_oa: OAR/OAC tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 09/14] tests/intel/xe_oa: Exclusive/concurrent access, rc6 and stress open close Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 10/14] tests/intel/xe_oa: add remove OA config tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 11/14] tests/intel/xe_oa: OA buffer mmap tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 12/14] tests/intel/xe_oa: Register whitelisting and MMIO trigger tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 13/14] tests/intel/xe_oa: Drop "xe-ref-count" subtest Ashutosh Dixit
2024-07-01 19:53   ` Umesh Nerlige Ramappa
2024-07-01  2:53 ` [PATCH i-g-t 14/14] HAX: Add Xe OA tests to xe-fast-feedback.testlist Ashutosh Dixit
2024-07-01  3:23 ` ✓ CI.xeBAT: success for Intel Xe OA IGT's (rev7) Patchwork
2024-07-01  3:31 ` ✓ Fi.CI.BAT: " Patchwork
2024-07-01  5:00 ` ✗ CI.xeFULL: failure " Patchwork
2024-07-01 19:56   ` Umesh Nerlige Ramappa
2024-07-01 23:08     ` Dixit, Ashutosh
2024-07-01  5:36 ` ✗ Fi.CI.IGT: " Patchwork

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