[PATCH v3 01/19] drm-uapi/amdgpu: sync with drm-next

[PATCH v3 01/19] drm-uapi/amdgpu: sync with drm-next

[Sunil Khatri]

Sync with drm-next commit ("e0400bf7d91ed477b827a674e5d64406c78ffd48")

This patch introduces new UAPI/IOCTL for usermode graphics
queue. IGT test cases fill this structure and request
the graphics driver to add a graphics work queue for it.
The output of this UAPI is a queue id.

This UAPI maps the queue into GPU, so the graphics app can start
submitting work to the queue as soon as the call returns.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 include/drm-uapi/amdgpu_drm.h | 123 ++++++++++++++++++++++++++++++++++
 1 file changed, 123 insertions(+)

diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index efe5de6ce..d780e1f2a 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -54,6 +54,7 @@ extern "C" {
 #define DRM_AMDGPU_VM			0x13
 #define DRM_AMDGPU_FENCE_TO_HANDLE	0x14
 #define DRM_AMDGPU_SCHED		0x15
+#define DRM_AMDGPU_USERQ		0x16
 
 #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
 #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -71,6 +72,7 @@ extern "C" {
 #define DRM_IOCTL_AMDGPU_VM		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
 #define DRM_IOCTL_AMDGPU_SCHED		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
+#define DRM_IOCTL_AMDGPU_USERQ		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
 
 /**
  * DOC: memory domains
@@ -319,6 +321,127 @@ union drm_amdgpu_ctx {
 	union drm_amdgpu_ctx_out out;
 };
 
+/* user queue IOCTL operations */
+#define AMDGPU_USERQ_OP_CREATE	1
+#define AMDGPU_USERQ_OP_FREE	2
+
+/*
+ * This structure is a container to pass input configuration
+ * info for all supported userqueue related operations.
+ * For operation AMDGPU_USERQ_OP_CREATE: user is expected
+ *  to set all fields, excep the parameter 'queue_id'.
+ * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected
+ *  to be set is 'queue_id', eveything else is ignored.
+ */
+struct drm_amdgpu_userq_in {
+	/** AMDGPU_USERQ_OP_* */
+	__u32	op;
+	/** Queue id passed for operation USERQ_OP_FREE */
+	__u32	queue_id;
+	/** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */
+	__u32   ip_type;
+	/**
+	 * @doorbell_handle: the handle of doorbell GEM object
+	 * associated with this userqueue client.
+	 */
+	__u32   doorbell_handle;
+	/**
+	 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
+	 * Kernel will generate absolute doorbell offset using doorbell_handle
+	 * and doorbell_offset in the doorbell bo.
+	 */
+	__u32   doorbell_offset;
+	__u32 _pad;
+	/**
+	 * @queue_va: Virtual address of the GPU memory which holds the queue
+	 * object. The queue holds the workload packets.
+	 */
+	__u64   queue_va;
+	/**
+	 * @queue_size: Size of the queue in bytes, this needs to be 256-byte
+	 * aligned.
+	 */
+	__u64   queue_size;
+	/**
+	 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR.
+	 * This object must be at least 8 byte in size and aligned to 8-byte offset.
+	 */
+	__u64   rptr_va;
+	/**
+	 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR.
+	 * This object must be at least 8 byte in size and aligned to 8-byte offset.
+	 *
+	 * Queue, RPTR and WPTR can come from the same object, as long as the size
+	 * and alignment related requirements are met.
+	 */
+	__u64   wptr_va;
+	/**
+	 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow
+	 * the GPU to uniquely define and identify a usermode queue.
+	 *
+	 * MQD data can be of different size for different GPU IP/engine and
+	 * their respective versions/revisions, so this points to a __u64 *
+	 * which holds IP specific MQD of this usermode queue.
+	 */
+	__u64 mqd;
+	/**
+	 * @size: size of MQD data in bytes, it must match the MQD structure
+	 * size of the respective engine/revision defined in UAPI for ex, for
+	 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).
+	 */
+	__u64 mqd_size;
+};
+
+/* The structure to carry output of userqueue ops */
+struct drm_amdgpu_userq_out {
+	/**
+	 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique
+	 * queue ID to represent the newly created userqueue in the system, otherwise
+	 * it should be ignored.
+	 */
+	__u32	queue_id;
+	__u32 _pad;
+};
+
+union drm_amdgpu_userq {
+	struct drm_amdgpu_userq_in in;
+	struct drm_amdgpu_userq_out out;
+};
+
+/* GFX V11 IP specific MQD parameters */
+struct drm_amdgpu_userq_mqd_gfx11 {
+	/**
+	 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.
+	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
+	 */
+	__u64   shadow_va;
+	/**
+	 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
+	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
+	 */
+	__u64   csa_va;
+};
+
+/* GFX V11 SDMA IP specific MQD parameters */
+struct drm_amdgpu_userq_mqd_sdma_gfx11 {
+	/**
+	 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
+	 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
+	 * to get the size.
+	 */
+	__u64   csa_va;
+};
+
+/* GFX V11 Compute IP specific MQD parameters */
+struct drm_amdgpu_userq_mqd_compute_gfx11 {
+	/**
+	 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer.
+	 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
+	 * to get the size.
+	 */
+	__u64   eop_va;
+};
+
 /* vm ioctl */
 #define AMDGPU_VM_OP_RESERVE_VMID	1
 #define AMDGPU_VM_OP_UNRESERVE_VMID	2
-- 
2.43.0

[PATCH v3 01/19] drm-uapi/amdgpu: sync with drm-next

[Sunil Khatri]

Sync with drm-next commit ("e0400bf7d91ed477b827a674e5d64406c78ffd48")

This patch introduces new UAPI/IOCTL for usermode graphics
queue. IGT test cases fill this structure and request
the graphics driver to add a graphics work queue for it.
The output of this UAPI is a queue id.

This UAPI maps the queue into GPU, so the graphics app can start
submitting work to the queue as soon as the call returns.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 include/drm-uapi/amdgpu_drm.h | 123 ++++++++++++++++++++++++++++++++++
 1 file changed, 123 insertions(+)

diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index efe5de6ce..d780e1f2a 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -54,6 +54,7 @@ extern "C" {
 #define DRM_AMDGPU_VM			0x13
 #define DRM_AMDGPU_FENCE_TO_HANDLE	0x14
 #define DRM_AMDGPU_SCHED		0x15
+#define DRM_AMDGPU_USERQ		0x16
 
 #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
 #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -71,6 +72,7 @@ extern "C" {
 #define DRM_IOCTL_AMDGPU_VM		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
 #define DRM_IOCTL_AMDGPU_SCHED		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
+#define DRM_IOCTL_AMDGPU_USERQ		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
 
 /**
  * DOC: memory domains
@@ -319,6 +321,127 @@ union drm_amdgpu_ctx {
 	union drm_amdgpu_ctx_out out;
 };
 
+/* user queue IOCTL operations */
+#define AMDGPU_USERQ_OP_CREATE	1
+#define AMDGPU_USERQ_OP_FREE	2
+
+/*
+ * This structure is a container to pass input configuration
+ * info for all supported userqueue related operations.
+ * For operation AMDGPU_USERQ_OP_CREATE: user is expected
+ *  to set all fields, excep the parameter 'queue_id'.
+ * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected
+ *  to be set is 'queue_id', eveything else is ignored.
+ */
+struct drm_amdgpu_userq_in {
+	/** AMDGPU_USERQ_OP_* */
+	__u32	op;
+	/** Queue id passed for operation USERQ_OP_FREE */
+	__u32	queue_id;
+	/** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */
+	__u32   ip_type;
+	/**
+	 * @doorbell_handle: the handle of doorbell GEM object
+	 * associated with this userqueue client.
+	 */
+	__u32   doorbell_handle;
+	/**
+	 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
+	 * Kernel will generate absolute doorbell offset using doorbell_handle
+	 * and doorbell_offset in the doorbell bo.
+	 */
+	__u32   doorbell_offset;
+	__u32 _pad;
+	/**
+	 * @queue_va: Virtual address of the GPU memory which holds the queue
+	 * object. The queue holds the workload packets.
+	 */
+	__u64   queue_va;
+	/**
+	 * @queue_size: Size of the queue in bytes, this needs to be 256-byte
+	 * aligned.
+	 */
+	__u64   queue_size;
+	/**
+	 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR.
+	 * This object must be at least 8 byte in size and aligned to 8-byte offset.
+	 */
+	__u64   rptr_va;
+	/**
+	 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR.
+	 * This object must be at least 8 byte in size and aligned to 8-byte offset.
+	 *
+	 * Queue, RPTR and WPTR can come from the same object, as long as the size
+	 * and alignment related requirements are met.
+	 */
+	__u64   wptr_va;
+	/**
+	 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow
+	 * the GPU to uniquely define and identify a usermode queue.
+	 *
+	 * MQD data can be of different size for different GPU IP/engine and
+	 * their respective versions/revisions, so this points to a __u64 *
+	 * which holds IP specific MQD of this usermode queue.
+	 */
+	__u64 mqd;
+	/**
+	 * @size: size of MQD data in bytes, it must match the MQD structure
+	 * size of the respective engine/revision defined in UAPI for ex, for
+	 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).
+	 */
+	__u64 mqd_size;
+};
+
+/* The structure to carry output of userqueue ops */
+struct drm_amdgpu_userq_out {
+	/**
+	 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique
+	 * queue ID to represent the newly created userqueue in the system, otherwise
+	 * it should be ignored.
+	 */
+	__u32	queue_id;
+	__u32 _pad;
+};
+
+union drm_amdgpu_userq {
+	struct drm_amdgpu_userq_in in;
+	struct drm_amdgpu_userq_out out;
+};
+
+/* GFX V11 IP specific MQD parameters */
+struct drm_amdgpu_userq_mqd_gfx11 {
+	/**
+	 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.
+	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
+	 */
+	__u64   shadow_va;
+	/**
+	 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
+	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
+	 */
+	__u64   csa_va;
+};
+
+/* GFX V11 SDMA IP specific MQD parameters */
+struct drm_amdgpu_userq_mqd_sdma_gfx11 {
+	/**
+	 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
+	 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
+	 * to get the size.
+	 */
+	__u64   csa_va;
+};
+
+/* GFX V11 Compute IP specific MQD parameters */
+struct drm_amdgpu_userq_mqd_compute_gfx11 {
+	/**
+	 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer.
+	 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
+	 * to get the size.
+	 */
+	__u64   eop_va;
+};
+
 /* vm ioctl */
 #define AMDGPU_VM_OP_RESERVE_VMID	1
 #define AMDGPU_VM_OP_UNRESERVE_VMID	2
-- 
2.43.0

[PATCH v3 02/19] drm-uapi/amdgpu: sync with drm-next

[Sunil Khatri]

Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")

Added support of UAPI for user queue secure semaphore.
The semaphore is used to synchronize between the caller and
the gpu hw and user wait for the semaphore.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 include/drm-uapi/amdgpu_drm.h | 117 ++++++++++++++++++++++++++++++++++
 1 file changed, 117 insertions(+)

diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index d780e1f2a..fed39c9b4 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -55,6 +55,8 @@ extern "C" {
 #define DRM_AMDGPU_FENCE_TO_HANDLE	0x14
 #define DRM_AMDGPU_SCHED		0x15
 #define DRM_AMDGPU_USERQ		0x16
+#define DRM_AMDGPU_USERQ_SIGNAL		0x17
+#define DRM_AMDGPU_USERQ_WAIT		0x18
 
 #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
 #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -73,6 +75,8 @@ extern "C" {
 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
 #define DRM_IOCTL_AMDGPU_SCHED		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
 #define DRM_IOCTL_AMDGPU_USERQ		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
+#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
+#define DRM_IOCTL_AMDGPU_USERQ_WAIT	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
 
 /**
  * DOC: memory domains
@@ -442,6 +446,119 @@ struct drm_amdgpu_userq_mqd_compute_gfx11 {
 	__u64   eop_va;
 };
 
+/* userq signal/wait ioctl */
+struct drm_amdgpu_userq_signal {
+	/**
+	 * @queue_id: Queue handle used by the userq fence creation function
+	 * to retrieve the WPTR.
+	 */
+	__u32	queue_id;
+	__u32	pad;
+	/**
+	 * @syncobj_handles: The list of syncobj handles submitted by the user queue
+	 * job to be signaled.
+	 */
+	__u64	syncobj_handles;
+	/**
+	 * @num_syncobj_handles: A count that represents the number of syncobj handles in
+	 * @syncobj_handles.
+	 */
+	__u64	num_syncobj_handles;
+	/**
+	 * @bo_read_handles: The list of BO handles that the submitted user queue job
+	 * is using for read only. This will update BO fences in the kernel.
+	 */
+	__u64	bo_read_handles;
+	/**
+	 * @bo_write_handles: The list of BO handles that the submitted user queue job
+	 * is using for write only. This will update BO fences in the kernel.
+	 */
+	__u64	bo_write_handles;
+	/**
+	 * @num_bo_read_handles: A count that represents the number of read BO handles in
+	 * @bo_read_handles.
+	 */
+	__u32	num_bo_read_handles;
+	/**
+	 * @num_bo_write_handles: A count that represents the number of write BO handles in
+	 * @bo_write_handles.
+	 */
+	__u32	num_bo_write_handles;
+};
+
+struct drm_amdgpu_userq_fence_info {
+	/**
+	 * @va: A gpu address allocated for each queue which stores the
+	 * read pointer (RPTR) value.
+	 */
+	__u64	va;
+	/**
+	 * @value: A 64 bit value represents the write pointer (WPTR) of the
+	 * queue commands which compared with the RPTR value to signal the
+	 * fences.
+	 */
+	__u64	value;
+};
+
+struct drm_amdgpu_userq_wait {
+	/**
+	 * @syncobj_handles: The list of syncobj handles submitted by the user queue
+	 * job to get the va/value pairs.
+	 */
+	__u64	syncobj_handles;
+	/**
+	 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by
+	 * the user queue job to get the va/value pairs at given @syncobj_timeline_points.
+	 */
+	__u64	syncobj_timeline_handles;
+	/**
+	 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the
+	 * user queue job for the corresponding @syncobj_timeline_handles.
+	 */
+	__u64	syncobj_timeline_points;
+	/**
+	 * @bo_read_handles: The list of read BO handles submitted by the user queue
+	 * job to get the va/value pairs.
+	 */
+	__u64	bo_read_handles;
+	/**
+	 * @bo_write_handles: The list of write BO handles submitted by the user queue
+	 * job to get the va/value pairs.
+	 */
+	__u64	bo_write_handles;
+	/**
+	 * @num_syncobj_timeline_handles: A count that represents the number of timeline
+	 * syncobj handles in @syncobj_timeline_handles.
+	 */
+	__u16	num_syncobj_timeline_handles;
+	/**
+	 * @num_fences: This field can be used both as input and output. As input it defines
+	 * the maximum number of fences that can be returned and as output it will specify
+	 * how many fences were actually returned from the ioctl.
+	 */
+	__u16	num_fences;
+	/**
+	 * @num_syncobj_handles: A count that represents the number of syncobj handles in
+	 * @syncobj_handles.
+	 */
+	__u32	num_syncobj_handles;
+	/**
+	 * @num_bo_read_handles: A count that represents the number of read BO handles in
+	 * @bo_read_handles.
+	 */
+	__u32	num_bo_read_handles;
+	/**
+	 * @num_bo_write_handles: A count that represents the number of write BO handles in
+	 * @bo_write_handles.
+	 */
+	__u32	num_bo_write_handles;
+	/**
+	 * @out_fences: The field is a return value from the ioctl containing the list of
+	 * address/value pairs to wait for.
+	 */
+	__u64	out_fences;
+};
+
 /* vm ioctl */
 #define AMDGPU_VM_OP_RESERVE_VMID	1
 #define AMDGPU_VM_OP_UNRESERVE_VMID	2
-- 
2.43.0

[PATCH v3 03/19] lib/amdgpu: Add user mode queue support in ring context

[Sunil Khatri]

Add the meta data to support the user mode command
submission in the ring_context.

User mode command submission methods needs these
resources to be initialized and to create/destroy queues.

Also once we have the queue created the queue id is
used to submit the work load to the h/w.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 lib/amdgpu/amd_ip_blocks.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index fc9df6c78..577b38387 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -86,6 +86,14 @@ struct dynamic_test{
 	bool support_sdma;
 };
 
+struct amdgpu_userq_bo {
+	amdgpu_bo_handle handle;
+	amdgpu_va_handle va_handle;
+	uint64_t mc_addr;
+	uint64_t size;
+	void *ptr;
+};
+
 #define for_each_test(t, T) for(typeof(*T) *t = T; t->name; t++)
 
 /* set during execution */
@@ -141,6 +149,29 @@ struct amdgpu_ring_context {
 	struct amdgpu_cs_ib_info ib_info;     /* amdgpu_bo_list_create */
 	struct amdgpu_cs_request ibs_request; /* amdgpu_cs_query_fence_status */
 	struct amdgpu_cs_err_codes err_codes;
+
+	/* User queue resources */
+	struct  amdgpu_userq_bo queue;
+	struct  amdgpu_userq_bo shadow;
+	struct  amdgpu_userq_bo doorbell;
+	struct  amdgpu_userq_bo rptr;
+	struct  amdgpu_userq_bo wptr;
+	struct  amdgpu_userq_bo csa;
+	struct  amdgpu_userq_bo eop;
+
+	uint32_t *queue_cpu;
+	uint64_t *wptr_cpu;
+	uint64_t *doorbell_cpu;
+
+	uint32_t db_handle;
+	uint32_t queue_id;
+	uint32_t npkt;
+
+	uint32_t timeline_syncobj_handle;
+	uint64_t point;
+	bool user_queue;
+
+	struct drm_amdgpu_info_device dev_info;
 };
 
 
-- 
2.43.0

[PATCH v3 04/19] lib/amdgpu: Add support of amd user queues

[Sunil Khatri]

This is the first patch set to add support of
UMQ(User mode queues) submission in IGT.

UMQ allows users to directly create a user queue and
submit workload to the GPU h/w to directly instead
of sending the workload to kernel and then to GPU h/w.

This will be used by test cases which will be testing
the UMQ queues for gfx/compute and sdma to start with.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 lib/amdgpu/amd_PM4.h        |   3 +
 lib/amdgpu/amd_ip_blocks.h  |   5 +
 lib/amdgpu/amd_user_queue.c | 418 ++++++++++++++++++++++++++++++++++++
 lib/amdgpu/amd_user_queue.h |  48 +++++
 lib/meson.build             |   3 +-
 5 files changed, 476 insertions(+), 1 deletion(-)
 create mode 100644 lib/amdgpu/amd_user_queue.c
 create mode 100644 lib/amdgpu/amd_user_queue.h

diff --git a/lib/amdgpu/amd_PM4.h b/lib/amdgpu/amd_PM4.h
index 5bc3cb783..8f59b4223 100644
--- a/lib/amdgpu/amd_PM4.h
+++ b/lib/amdgpu/amd_PM4.h
@@ -192,6 +192,9 @@
 		 * 1 - pfp
 		 */
 
+#define PACKET3_INDIRECT_BUFFER                         0x3F
+#define PACKET3_PROTECTED_FENCE_SIGNAL                  0xd0
+
 #define	PACKET3_WRITE_DATA				0x37
 #define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
 		/* 0 - register
diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index 577b38387..85d69f5c6 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -27,6 +27,11 @@
 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */
 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */
 
+/* User queue */
+#define   S_3F3_INHERIT_VMID_MQD_GFX(x)        (((unsigned int)(x)&0x1) << 22)/* userqueue only */
+#define   S_3F3_VALID_COMPUTE(x)		(((unsigned int)(x)&0x1) << 23)/* userqueue only */
+#define   S_3F3_INHERIT_VMID_MQD_COMPUTE(x)	(((unsigned int)(x)&0x1) << 30)/* userqueue only */
+
 enum amd_ip_block_type {
 	AMD_IP_GFX = 0,
 	AMD_IP_COMPUTE,
diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c
new file mode 100644
index 000000000..9412a37e8
--- /dev/null
+++ b/lib/amdgpu/amd_user_queue.c
@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ */
+
+#include "amd_user_queue.h"
+#include "amd_memory.h"
+#include "amd_PM4.h"
+#include "ioctl_wrappers.h"
+
+void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle, struct amdgpu_userq_bo *doorbell_bo,
+			   unsigned int size, unsigned int domain)
+{
+	struct amdgpu_bo_alloc_request req = {0};
+	amdgpu_bo_handle buf_handle;
+	int r;
+
+	req.alloc_size = ALIGN(size, PAGE_SIZE);
+	req.preferred_heap = domain;
+	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
+	igt_assert_eq(r, 0);
+
+	doorbell_bo->handle = buf_handle;
+	doorbell_bo->size = req.alloc_size;
+
+	r = amdgpu_bo_cpu_map(doorbell_bo->handle,
+			      (void **)&doorbell_bo->ptr);
+	igt_assert_eq(r, 0);
+}
+
+int
+amdgpu_bo_alloc_and_map_uq(amdgpu_device_handle device_handle, unsigned int size,
+			   unsigned int alignment, unsigned int heap, uint64_t alloc_flags,
+			   uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
+			   uint64_t *mc_address, amdgpu_va_handle *va_handle,
+			   uint32_t timeline_syncobj_handle, uint64_t point)
+{
+	struct amdgpu_bo_alloc_request request = {};
+	amdgpu_bo_handle buf_handle;
+	uint64_t vmc_addr;
+	int r;
+
+	request.alloc_size = size;
+	request.phys_alignment = alignment;
+	request.preferred_heap = heap;
+	request.flags = alloc_flags;
+
+	r = amdgpu_bo_alloc(device_handle, &request, &buf_handle);
+	if (r)
+		return r;
+
+	r = amdgpu_va_range_alloc(device_handle,
+				  amdgpu_gpu_va_range_general,
+				  size, alignment, 0, &vmc_addr,
+				  va_handle, 0);
+	if (r)
+		goto error_va_alloc;
+
+	r = amdgpu_bo_va_op_raw2(device_handle, buf_handle, 0,
+				 ALIGN(size, getpagesize()), vmc_addr,
+				 AMDGPU_VM_PAGE_READABLE |
+				 AMDGPU_VM_PAGE_WRITEABLE |
+				 AMDGPU_VM_PAGE_EXECUTABLE |
+				 mapping_flags,
+				 AMDGPU_VA_OP_MAP,
+				 timeline_syncobj_handle,
+				 point, 0, 0);
+	if (r)
+		goto error_va_map;
+
+	if (cpu) {
+		r = amdgpu_bo_cpu_map(buf_handle, cpu);
+		if (r)
+			goto error_cpu_map;
+	}
+
+	*bo = buf_handle;
+	*mc_address = vmc_addr;
+
+	return 0;
+
+error_cpu_map:
+	amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
+error_va_map:
+	amdgpu_va_range_free(*va_handle);
+error_va_alloc:
+	amdgpu_bo_free(buf_handle);
+	return r;
+}
+
+void amdgpu_bo_unmap_and_free_uq(amdgpu_device_handle device_handle, amdgpu_bo_handle bo,
+			    amdgpu_va_handle va_handle, uint64_t mc_addr, uint64_t size,
+			    uint32_t timeline_syncobj_handle, uint64_t point,
+			    uint64_t syncobj_handles_array, uint32_t num_syncobj_handles)
+{
+	amdgpu_bo_cpu_unmap(bo);
+	amdgpu_bo_va_op_raw2(device_handle, bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP,
+				  timeline_syncobj_handle, point,
+				  syncobj_handles_array, num_syncobj_handles);
+	amdgpu_va_range_free(va_handle);
+	amdgpu_bo_free(bo);
+}
+
+int amdgpu_timeline_syncobj_wait(amdgpu_device_handle device_handle,
+				 uint32_t timeline_syncobj_handle, uint64_t point)
+{
+	uint32_t flags = DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED;
+	int r;
+
+	r = amdgpu_cs_syncobj_query2(device_handle, &timeline_syncobj_handle,
+				     &point, 1, flags);
+	if (r)
+		return r;
+
+	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &timeline_syncobj_handle,
+					    &point, 1, INT64_MAX,
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+					    NULL);
+	if (r)
+		igt_warn("Timeline timed out\n");
+	return r;
+}
+
+void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_context *ring_context,
+			      unsigned int ip_type, uint64_t mc_address)
+{
+	int r;
+	uint32_t *npkt = &ring_context->npkt;
+	uint32_t *queue_cpu = ring_context->queue_cpu;
+	uint32_t control = ring_context->pm4_dw;
+	uint32_t syncarray[1];
+
+	struct drm_amdgpu_userq_signal signal_data;
+
+	/* Prepare the Indirect IB to submit the IB to user queue */
+	queue_cpu[(*npkt)++] = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
+	queue_cpu[(*npkt)++] = lower_32_bits(mc_address);
+	queue_cpu[(*npkt)++] = upper_32_bits(mc_address);
+
+	if (ip_type == AMD_IP_GFX)
+		queue_cpu[(*npkt)++] = control | S_3F3_INHERIT_VMID_MQD_GFX(1);
+	else
+		queue_cpu[(*npkt)++] = control | S_3F3_VALID_COMPUTE(1)
+					       | S_3F3_INHERIT_VMID_MQD_COMPUTE(1);
+
+	queue_cpu[(*npkt)++] = PACKET3(PACKET3_PROTECTED_FENCE_SIGNAL, 0);
+	/* empty dword is needed for fence signal pm4 */
+	++*npkt;
+
+	*ring_context->wptr_cpu = *npkt;
+	ring_context->doorbell_cpu[DOORBELL_INDEX] = *npkt;
+
+	/* Add a fence packet for signal */
+	syncarray[0] = ring_context->timeline_syncobj_handle;
+	signal_data.queue_id = ring_context->queue_id;
+	signal_data.syncobj_handles = (uintptr_t)syncarray;
+	signal_data.num_syncobj_handles = 1;
+	signal_data.bo_read_handles = 0;
+	signal_data.bo_write_handles = 0;
+	signal_data.num_bo_read_handles = 0;
+	signal_data.num_bo_write_handles = 0;
+
+	r = amdgpu_userq_signal(device, &signal_data);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_cs_syncobj_wait(device, &ring_context->timeline_syncobj_handle, 1, INT64_MAX,
+				   DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL, NULL);
+	igt_assert_eq(r, 0);
+}
+
+void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
+			       unsigned int type)
+{
+	int r;
+
+	if (type > AMD_IP_DMA) {
+		igt_info("Invalid IP not supported for UMQ Submission\n");
+		return;
+	}
+
+	/* Free the Usermode Queue */
+	r = amdgpu_free_userqueue(device_handle, ctxt->queue_id);
+	igt_assert_eq(r, 0);
+
+	switch (type) {
+	case AMD_IP_GFX:
+		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->csa.handle,
+					    ctxt->csa.va_handle,
+					    ctxt->csa.mc_addr, ctxt->dev_info.csa_size,
+					    ctxt->timeline_syncobj_handle, ++ctxt->point,
+					    0, 0);
+
+		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->shadow.handle,
+					    ctxt->shadow.va_handle,
+					    ctxt->shadow.mc_addr, ctxt->dev_info.shadow_size,
+					    ctxt->timeline_syncobj_handle, ++ctxt->point,
+					    0, 0);
+
+		r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
+						 ctxt->point);
+		igt_assert_eq(r, 0);
+		break;
+
+	case AMD_IP_COMPUTE:
+		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->eop.handle,
+					    ctxt->eop.va_handle,
+					    ctxt->eop.mc_addr, 256,
+					    ctxt->timeline_syncobj_handle, ++ctxt->point,
+					    0, 0);
+
+		r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
+						 ctxt->point);
+		igt_assert_eq(r, 0);
+		break;
+
+	case AMD_IP_DMA:
+		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->csa.handle,
+					    ctxt->csa.va_handle,
+					    ctxt->csa.mc_addr, ctxt->dev_info.csa_size,
+					    ctxt->timeline_syncobj_handle, ++ctxt->point,
+					    0, 0);
+
+		r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
+						 ctxt->point);
+		igt_assert_eq(r, 0);
+		break;
+
+	default:
+		igt_info("IP invalid for cleanup\n");
+	}
+
+	r = amdgpu_cs_destroy_syncobj(device_handle, ctxt->timeline_syncobj_handle);
+	igt_assert_eq(r, 0);
+
+	/* Clean up doorbell*/
+	r = amdgpu_bo_cpu_unmap(ctxt->doorbell.handle);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_bo_free(ctxt->doorbell.handle);
+	igt_assert_eq(r, 0);
+
+	/* Clean up rptr wptr queue */
+	amdgpu_bo_unmap_and_free(ctxt->rptr.handle, ctxt->rptr.va_handle,
+				 ctxt->rptr.mc_addr, 8);
+
+	amdgpu_bo_unmap_and_free(ctxt->wptr.handle, ctxt->wptr.va_handle,
+				 ctxt->wptr.mc_addr, 8);
+
+	amdgpu_bo_unmap_and_free(ctxt->queue.handle, ctxt->queue.va_handle,
+				 ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE);
+}
+
+void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
+			      unsigned int type)
+{
+	int r;
+	uint64_t gtt_flags = 0;
+	struct drm_amdgpu_userq_mqd_gfx11 gfx_mqd;
+	struct drm_amdgpu_userq_mqd_sdma_gfx11 sdma_mqd;
+	struct drm_amdgpu_userq_mqd_compute_gfx11 compute_mqd;
+	void *mqd;
+
+	if (type > AMD_IP_DMA) {
+		igt_info("Invalid IP not supported for UMQ Submission\n");
+		return;
+	}
+
+	r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO,
+			      sizeof(ctxt->dev_info), &ctxt->dev_info);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_cs_create_syncobj2(device_handle, 0, &ctxt->timeline_syncobj_handle);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_bo_alloc_and_map_uq(device_handle, USERMODE_QUEUE_SIZE,
+				       ALIGNMENT,
+				       AMDGPU_GEM_DOMAIN_GTT,
+				       gtt_flags,
+				       AMDGPU_VM_MTYPE_UC,
+				       &ctxt->queue.handle, &ctxt->queue.ptr,
+				       &ctxt->queue.mc_addr, &ctxt->queue.va_handle,
+				       ctxt->timeline_syncobj_handle, ++ctxt->point);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_bo_alloc_and_map_uq(device_handle, 8,
+				       ALIGNMENT,
+				       AMDGPU_GEM_DOMAIN_GTT,
+				       gtt_flags,
+				       AMDGPU_VM_MTYPE_UC,
+				       &ctxt->wptr.handle, &ctxt->wptr.ptr,
+				       &ctxt->wptr.mc_addr, &ctxt->wptr.va_handle,
+				       ctxt->timeline_syncobj_handle, ++ctxt->point);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_bo_alloc_and_map_uq(device_handle, 8,
+				       ALIGNMENT,
+				       AMDGPU_GEM_DOMAIN_GTT,
+				       gtt_flags,
+				       AMDGPU_VM_MTYPE_UC,
+				       &ctxt->rptr.handle, &ctxt->rptr.ptr,
+				       &ctxt->rptr.mc_addr, &ctxt->rptr.va_handle,
+				       ctxt->timeline_syncobj_handle, ++ctxt->point);
+	igt_assert_eq(r, 0);
+
+	switch (type) {
+	case AMD_IP_GFX:
+		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.shadow_size,
+					       ctxt->dev_info.shadow_alignment,
+					       AMDGPU_GEM_DOMAIN_GTT,
+					       gtt_flags,
+					       AMDGPU_VM_MTYPE_UC,
+					       &ctxt->shadow.handle, NULL,
+					       &ctxt->shadow.mc_addr, &ctxt->shadow.va_handle,
+					       ctxt->timeline_syncobj_handle, ++ctxt->point);
+		igt_assert_eq(r, 0);
+
+		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.csa_size,
+					       ctxt->dev_info.csa_alignment,
+					       AMDGPU_GEM_DOMAIN_GTT,
+					       gtt_flags,
+					       AMDGPU_VM_MTYPE_UC,
+					       &ctxt->csa.handle, NULL,
+					       &ctxt->csa.mc_addr, &ctxt->csa.va_handle,
+					       ctxt->timeline_syncobj_handle, ++ctxt->point);
+		igt_assert_eq(r, 0);
+
+		gfx_mqd.shadow_va = ctxt->shadow.mc_addr;
+		gfx_mqd.csa_va = ctxt->csa.mc_addr;
+		mqd = &gfx_mqd;
+		break;
+
+	case AMD_IP_COMPUTE:
+		r = amdgpu_bo_alloc_and_map_uq(device_handle, 256,
+					       ALIGNMENT,
+					       AMDGPU_GEM_DOMAIN_GTT,
+					       gtt_flags,
+					       AMDGPU_VM_MTYPE_UC,
+					       &ctxt->eop.handle, NULL,
+					       &ctxt->eop.mc_addr, &ctxt->eop.va_handle,
+					       ctxt->timeline_syncobj_handle, ++ctxt->point);
+		igt_assert_eq(r, 0);
+		compute_mqd.eop_va = ctxt->eop.mc_addr;
+		mqd = &compute_mqd;
+		break;
+
+	case AMD_IP_DMA:
+		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.csa_size,
+					       ctxt->dev_info.csa_alignment,
+					       AMDGPU_GEM_DOMAIN_GTT,
+					       gtt_flags,
+					       AMDGPU_VM_MTYPE_UC,
+					       &ctxt->csa.handle, NULL,
+					       &ctxt->csa.mc_addr, &ctxt->csa.va_handle,
+					       ctxt->timeline_syncobj_handle, ++ctxt->point);
+		igt_assert_eq(r, 0);
+		sdma_mqd.csa_va = ctxt->csa.mc_addr;
+		mqd = &sdma_mqd;
+		break;
+
+	default:
+		igt_info("Unsupported IP for UMQ submission\n");
+		return;
+
+	}
+
+	r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
+					 ctxt->point);
+	igt_assert_eq(r, 0);
+
+	amdgpu_alloc_doorbell(device_handle, &ctxt->doorbell, PAGE_SIZE,
+			      AMDGPU_GEM_DOMAIN_DOORBELL);
+
+	ctxt->doorbell_cpu = (uint64_t *)ctxt->doorbell.ptr;
+
+	ctxt->wptr_cpu = (uint64_t *)ctxt->wptr.ptr;
+
+	ctxt->queue_cpu = (uint32_t *)ctxt->queue.ptr;
+	memset(ctxt->queue_cpu, 0, USERMODE_QUEUE_SIZE);
+
+	/* get db bo handle */
+	amdgpu_bo_export(ctxt->doorbell.handle, amdgpu_bo_handle_type_kms, &ctxt->db_handle);
+
+	/* Create the Usermode Queue */
+	switch (type) {
+	case AMD_IP_GFX:
+		r = amdgpu_create_userqueue(device_handle, AMDGPU_HW_IP_GFX,
+					    ctxt->db_handle, DOORBELL_INDEX,
+					    ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
+					    ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
+					    mqd, &ctxt->queue_id);
+		igt_assert_eq(r, 0);
+		break;
+
+	case AMD_IP_COMPUTE:
+		r = amdgpu_create_userqueue(device_handle, AMDGPU_HW_IP_COMPUTE,
+					    ctxt->db_handle, DOORBELL_INDEX,
+					    ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
+					    ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
+					    mqd, &ctxt->queue_id);
+		igt_assert_eq(r, 0);
+		break;
+
+	case AMD_IP_DMA:
+		r = amdgpu_create_userqueue(device_handle, AMDGPU_HW_IP_DMA,
+					    ctxt->db_handle, DOORBELL_INDEX,
+					    ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
+					    ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
+					    mqd, &ctxt->queue_id);
+		igt_assert_eq(r, 0);
+		break;
+
+	default:
+		igt_info("Unsupported IP, failed to create user queue\n");
+		return;
+
+	}
+}
diff --git a/lib/amdgpu/amd_user_queue.h b/lib/amdgpu/amd_user_queue.h
new file mode 100644
index 000000000..355f16f19
--- /dev/null
+++ b/lib/amdgpu/amd_user_queue.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AMD_USER_QUEUE_
+#define _AMD_USER_QUEUE_
+
+#include <amdgpu_drm.h>
+#include <amdgpu.h>
+#include <time.h>
+#include "amd_ip_blocks.h"
+
+
+#ifndef PAGE_SIZE
+#define PAGE_SIZE 4096
+#endif
+
+#define USERMODE_QUEUE_SIZE		(PAGE_SIZE * 256)   //In bytes
+#define ALIGNMENT			4096
+#define DOORBELL_INDEX			4
+
+void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle, struct amdgpu_userq_bo *doorbell_bo,
+			   unsigned int size, unsigned int domain);
+
+int amdgpu_bo_alloc_and_map_uq(amdgpu_device_handle device_handle, unsigned int size,
+			       unsigned int alignment, unsigned int heap, uint64_t alloc_flags,
+			       uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
+			       uint64_t *mc_address, amdgpu_va_handle *va_handle,
+			       uint32_t timeline_syncobj_handle, uint64_t point);
+
+void amdgpu_bo_unmap_and_free_uq(amdgpu_device_handle device_handle, amdgpu_bo_handle bo,
+				 amdgpu_va_handle va_handle, uint64_t mc_addr, uint64_t size,
+				 uint32_t timeline_syncobj_handle, uint64_t point,
+				 uint64_t syncobj_handles_array, uint32_t num_syncobj_handles);
+
+int amdgpu_timeline_syncobj_wait(amdgpu_device_handle device_handle,
+				 uint32_t timeline_syncobj_handle, uint64_t point);
+
+void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
+			      unsigned int ip_type);
+
+void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
+			       unsigned int ip_type);
+
+void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_context *ring_context,
+			      unsigned int ip_type, uint64_t mc_address);
+
+#endif
diff --git a/lib/meson.build b/lib/meson.build
index d01c90df9..d7bb72c57 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -165,7 +165,8 @@ if libdrm_amdgpu.found()
 		'amdgpu/xalloc.h',
 		'amdgpu/amd_cp_dma.c',
 		'amdgpu/amd_mem_leak.c',
-		'amdgpu/amd_mmd_shared.c'
+		'amdgpu/amd_mmd_shared.c',
+		'amdgpu/amd_user_queue.c'
 	]
 	if libdrm_amdgpu.version().version_compare('> 2.4.99')
 		lib_sources +=[ 'amdgpu/amd_dispatch.c',]
-- 
2.43.0

[PATCH v3 05/19] lib/amdgpu: add func amdgpu_bo_alloc_and_map_sync

[Sunil Khatri]

Add amdgpu_bo_alloc_and_map_sync func which
is synchronised version of amdgpu_bo_alloc_and_map.
It wait till the timeline is signaled and page tables
are updated for the bo.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 lib/amdgpu/amd_memory.c | 19 +++++++++++++++++++
 lib/amdgpu/amd_memory.h |  8 ++++++++
 2 files changed, 27 insertions(+)

diff --git a/lib/amdgpu/amd_memory.c b/lib/amdgpu/amd_memory.c
index 92ddc9fe2..d1ff57085 100644
--- a/lib/amdgpu/amd_memory.c
+++ b/lib/amdgpu/amd_memory.c
@@ -25,6 +25,8 @@
 
 #include "amd_memory.h"
 #include "amd_PM4.h"
+#include "amd_user_queue.h"
+
 /**
  *
  * @param device_handle
@@ -193,6 +195,23 @@ error_va_alloc:
 	return r;
 }
 
+int
+amdgpu_bo_alloc_and_map_sync(amdgpu_device_handle dev, unsigned int size,
+			     unsigned int alignment, unsigned int heap, uint64_t flags,
+			     uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
+			     uint64_t *mc_address, amdgpu_va_handle *va_handle,
+			     uint32_t timeline_syncobj_handle, uint64_t point, bool sync)
+{
+	if (sync)
+		return amdgpu_bo_alloc_and_map_uq(dev, size, alignment, heap, flags,
+						  mapping_flags, bo, cpu,
+						  mc_address, va_handle,
+						  timeline_syncobj_handle, point);
+	else
+		return amdgpu_bo_alloc_and_map(dev, size, alignment, heap, flags,
+					       bo, cpu, mc_address, va_handle);
+}
+
 int
 amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
 			unsigned alignment, unsigned heap, uint64_t alloc_flags,
diff --git a/lib/amdgpu/amd_memory.h b/lib/amdgpu/amd_memory.h
index a06f88923..9b0e3f392 100644
--- a/lib/amdgpu/amd_memory.h
+++ b/lib/amdgpu/amd_memory.h
@@ -55,6 +55,14 @@ amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
 			amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address,
 			amdgpu_va_handle *va_handle);
 
+int
+amdgpu_bo_alloc_and_map_sync(amdgpu_device_handle dev, unsigned int size,
+			     unsigned int alignment, unsigned int heap, uint64_t flags,
+			     uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
+			     uint64_t *mc_address, amdgpu_va_handle *va_handle,
+			     uint32_t timeline_syncobj_handle, uint64_t point,
+			     bool sync);
+
 int
 amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
 			unsigned alignment, unsigned heap, uint64_t alloc_flags,
-- 
2.43.0

[PATCH v3 06/19] tests/amdgpu: Add user queue support for gfx and compute

[Sunil Khatri]

Add support of user queue command submission for
a. amdgpu_command_submission_gfx
b. amdgpu_command_submission_compute

Also add support of user queues in all the helper
functions used by the above functions.

Also since helper functions are same for sdma too
so update the function call to accommodate the changes.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 lib/amdgpu/amd_command_submission.c | 313 +++++++++++++++++++---------
 lib/amdgpu/amd_command_submission.h |   8 +-
 lib/amdgpu/amd_compute.c            | 100 ++++++---
 lib/amdgpu/amd_compute.h            |   2 +-
 tests/amdgpu/amd_basic.c            |  58 ++++--
 tests/amdgpu/amd_security.c         |   4 +-
 6 files changed, 326 insertions(+), 159 deletions(-)

diff --git a/lib/amdgpu/amd_command_submission.c b/lib/amdgpu/amd_command_submission.c
index cd7240058..7550fa8bc 100644
--- a/lib/amdgpu/amd_command_submission.c
+++ b/lib/amdgpu/amd_command_submission.c
@@ -5,10 +5,14 @@
  * Copyright 2023 Advanced Micro Devices, Inc.
  */
 
+#include <amdgpu.h>
 #include "lib/amdgpu/amd_memory.h"
 #include "lib/amdgpu/amd_sdma.h"
 #include "lib/amdgpu/amd_PM4.h"
 #include "lib/amdgpu/amd_command_submission.h"
+#include "lib/amdgpu/amd_user_queue.h"
+#include "ioctl_wrappers.h"
+
 
 /*
  *
@@ -28,82 +32,100 @@ int amdgpu_test_exec_cs_helper(amdgpu_device_handle device, unsigned int ip_type
 	uint64_t ib_result_mc_address;
 	struct amdgpu_cs_fence fence_status = {0};
 	amdgpu_va_handle va_handle;
+	bool user_queue = ring_context->user_queue;
 
 	amdgpu_bo_handle *all_res = alloca(sizeof(ring_context->resources[0]) * (ring_context->res_cnt + 1));
 
 	if (expect_failure) {
 		/* allocate IB */
-		r = amdgpu_bo_alloc_and_map(device, ring_context->write_length, 4096,
-					    AMDGPU_GEM_DOMAIN_GTT, 0,
-					    &ib_result_handle, &ib_result_cpu,
-					    &ib_result_mc_address, &va_handle);
+		r = amdgpu_bo_alloc_and_map_sync(device, ring_context->write_length, 4096,
+						 AMDGPU_GEM_DOMAIN_GTT, 0, AMDGPU_VM_MTYPE_UC,
+						 &ib_result_handle, &ib_result_cpu,
+						 &ib_result_mc_address, &va_handle,
+						 ring_context->timeline_syncobj_handle,
+						 ++ring_context->point, user_queue);
 	} else {
 		/* prepare CS */
 		igt_assert(ring_context->pm4_dw <= 1024);
 		/* allocate IB */
-		r = amdgpu_bo_alloc_and_map(device, 4096, 4096,
-					    AMDGPU_GEM_DOMAIN_GTT, 0,
-					    &ib_result_handle, &ib_result_cpu,
-					    &ib_result_mc_address, &va_handle);
-
-
+		r = amdgpu_bo_alloc_and_map_sync(device, 4096, 4096,
+						 AMDGPU_GEM_DOMAIN_GTT, 0, AMDGPU_VM_MTYPE_UC,
+						 &ib_result_handle, &ib_result_cpu,
+						 &ib_result_mc_address, &va_handle,
+						 ring_context->timeline_syncobj_handle,
+						 ++ring_context->point, user_queue);
 	}
 	igt_assert_eq(r, 0);
 
+	if (user_queue) {
+		r = amdgpu_timeline_syncobj_wait(device, ring_context->timeline_syncobj_handle,
+						 ring_context->point);
+		igt_assert_eq(r, 0);
+	}
+
 	/* copy PM4 packet to ring from caller */
 	ring_ptr = ib_result_cpu;
 	memcpy(ring_ptr, ring_context->pm4, ring_context->pm4_dw * sizeof(*ring_context->pm4));
 
-	ring_context->ib_info.ib_mc_address = ib_result_mc_address;
-	ring_context->ib_info.size = ring_context->pm4_dw;
-	if (ring_context->secure)
-		ring_context->ib_info.flags |= AMDGPU_IB_FLAGS_SECURE;
-
-	ring_context->ibs_request.ip_type = ip_type;
-	ring_context->ibs_request.ring = ring_context->ring_id;
-	ring_context->ibs_request.number_of_ibs = 1;
-	ring_context->ibs_request.ibs = &ring_context->ib_info;
-	ring_context->ibs_request.fence_info.handle = NULL;
-
-	memcpy(all_res, ring_context->resources, sizeof(ring_context->resources[0]) * ring_context->res_cnt);
-	all_res[ring_context->res_cnt] = ib_result_handle;
-
-	r = amdgpu_bo_list_create(device, ring_context->res_cnt+1, all_res,
-				  NULL, &ring_context->ibs_request.resources);
-	igt_assert_eq(r, 0);
-
-	/* submit CS */
-	r = amdgpu_cs_submit(ring_context->context_handle, 0, &ring_context->ibs_request, 1);
-	ring_context->err_codes.err_code_cs_submit = r;
-	if (expect_failure)
-		igt_info("amdgpu_cs_submit %d PID %d\n", r, getpid());
+	if (user_queue)
+		amdgpu_user_queue_submit(device, ring_context, ip_type, ib_result_mc_address);
 	else {
-		if (r != -ECANCELED && r != -ENODATA && r != -EHWPOISON) /* we allow ECANCELED, ENODATA or -EHWPOISON for good jobs temporally */
-			igt_assert_eq(r, 0);
-	}
-
-
-	r = amdgpu_bo_list_destroy(ring_context->ibs_request.resources);
-	igt_assert_eq(r, 0);
+		ring_context->ib_info.ib_mc_address = ib_result_mc_address;
+		ring_context->ib_info.size = ring_context->pm4_dw;
+		if (ring_context->secure)
+			ring_context->ib_info.flags |= AMDGPU_IB_FLAGS_SECURE;
+
+		ring_context->ibs_request.ip_type = ip_type;
+		ring_context->ibs_request.ring = ring_context->ring_id;
+		ring_context->ibs_request.number_of_ibs = 1;
+		ring_context->ibs_request.ibs = &ring_context->ib_info;
+		ring_context->ibs_request.fence_info.handle = NULL;
+
+		memcpy(all_res, ring_context->resources,
+		       sizeof(ring_context->resources[0]) * ring_context->res_cnt);
+
+		all_res[ring_context->res_cnt] = ib_result_handle;
+
+		r = amdgpu_bo_list_create(device, ring_context->res_cnt + 1, all_res,
+					  NULL, &ring_context->ibs_request.resources);
+		igt_assert_eq(r, 0);
+
+		/* submit CS */
+		r = amdgpu_cs_submit(ring_context->context_handle, 0,
+				     &ring_context->ibs_request, 1);
+
+		ring_context->err_codes.err_code_cs_submit = r;
+		if (expect_failure)
+			igt_info("amdgpu_cs_submit %d PID %d\n", r, getpid());
+		else {
+			/* we allow ECANCELED, ENODATA or -EHWPOISON for good jobs temporally */
+			if (r != -ECANCELED && r != -ENODATA && r != -EHWPOISON)
+				igt_assert_eq(r, 0);
+		}
 
-	fence_status.ip_type = ip_type;
-	fence_status.ip_instance = 0;
-	fence_status.ring = ring_context->ibs_request.ring;
-	fence_status.context = ring_context->context_handle;
-	fence_status.fence = ring_context->ibs_request.seq_no;
-
-	/* wait for IB accomplished */
-	r = amdgpu_cs_query_fence_status(&fence_status,
-					 AMDGPU_TIMEOUT_INFINITE,
-					 0, &expired);
-	ring_context->err_codes.err_code_wait_for_fence = r;
-	if (expect_failure) {
-		igt_info("EXPECT FAILURE amdgpu_cs_query_fence_status %d expired %d PID %d\n", r,  expired, getpid());
-	} else {
-		if (r != -ECANCELED && r != -ENODATA) /* we allow ECANCELED or ENODATA for good jobs temporally */
-			igt_assert_eq(r, 0);
+		r = amdgpu_bo_list_destroy(ring_context->ibs_request.resources);
+		igt_assert_eq(r, 0);
+
+		fence_status.ip_type = ip_type;
+		fence_status.ip_instance = 0;
+		fence_status.ring = ring_context->ibs_request.ring;
+		fence_status.context = ring_context->context_handle;
+		fence_status.fence = ring_context->ibs_request.seq_no;
+
+		/* wait for IB accomplished */
+		r = amdgpu_cs_query_fence_status(&fence_status,
+						 AMDGPU_TIMEOUT_INFINITE,
+						 0, &expired);
+		ring_context->err_codes.err_code_wait_for_fence = r;
+		if (expect_failure) {
+			igt_info("EXPECT FAILURE amdgpu_cs_query_fence_status%d"
+				 "expired %d PID %d\n", r, expired, getpid());
+		} else {
+			/* we allow ECANCELED or ENODATA for good jobs temporally */
+			if (r != -ECANCELED && r != -ENODATA)
+				igt_assert_eq(r, 0);
+		}
 	}
-
 	amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
 				 ib_result_mc_address, 4096);
 	return r;
@@ -111,10 +133,9 @@ int amdgpu_test_exec_cs_helper(amdgpu_device_handle device, unsigned int ip_type
 
 void amdgpu_command_submission_write_linear_helper(amdgpu_device_handle device,
 						   const struct amdgpu_ip_block_version *ip_block,
-						   bool secure)
+						   bool secure, bool user_queue)
 
 {
-
 	const int sdma_write_length = 128;
 	const int pm4_dw = 256;
 
@@ -131,6 +152,7 @@ void amdgpu_command_submission_write_linear_helper(amdgpu_device_handle device,
 	ring_context->secure = secure;
 	ring_context->pm4_size = pm4_dw;
 	ring_context->res_cnt = 1;
+	ring_context->user_queue = user_queue;
 	igt_assert(ring_context->pm4);
 
 	r = amdgpu_query_hw_ip_info(device, ip_block->type, 0, &ring_context->hw_ip_info);
@@ -139,30 +161,51 @@ void amdgpu_command_submission_write_linear_helper(amdgpu_device_handle device,
 	for (i = 0; secure && (i < 2); i++)
 		gtt_flags[i] |= AMDGPU_GEM_CREATE_ENCRYPTED;
 
-	r = amdgpu_cs_ctx_create(device, &ring_context->context_handle);
+	if (user_queue) {
+		amdgpu_user_queue_create(device, ring_context, ip_block->type);
+	} else {
+		r = amdgpu_cs_ctx_create(device, &ring_context->context_handle);
+		igt_assert_eq(r, 0);
+	}
+
 
-	igt_assert_eq(r, 0);
 
+/* Dont need but check with vitaly if for KMS also we need ring id or not */
 	for (ring_id = 0; (1 << ring_id) & ring_context->hw_ip_info.available_rings; ring_id++) {
 		loop = 0;
 		ring_context->ring_id = ring_id;
 		while (loop < 2) {
 			/* allocate UC bo for sDMA use */
-			r = amdgpu_bo_alloc_and_map(device,
-						    ring_context->write_length * sizeof(uint32_t),
-						    4096, AMDGPU_GEM_DOMAIN_GTT,
-						    gtt_flags[loop], &ring_context->bo,
-						    (void **)&ring_context->bo_cpu,
-						    &ring_context->bo_mc,
-						    &ring_context->va_handle);
+			r = amdgpu_bo_alloc_and_map_sync(device,
+							 ring_context->write_length *
+							 sizeof(uint32_t),
+							 4096, AMDGPU_GEM_DOMAIN_GTT,
+							 gtt_flags[loop],
+							 AMDGPU_VM_MTYPE_UC,
+							 &ring_context->bo,
+							 (void **)&ring_context->bo_cpu,
+							 &ring_context->bo_mc,
+							 &ring_context->va_handle,
+							 ring_context->timeline_syncobj_handle,
+							 ++ring_context->point, user_queue);
+
 			igt_assert_eq(r, 0);
 
+			if (user_queue) {
+				r = amdgpu_timeline_syncobj_wait(device,
+					ring_context->timeline_syncobj_handle,
+					ring_context->point);
+				igt_assert_eq(r, 0);
+			}
+
 			/* clear bo */
-			memset((void *)ring_context->bo_cpu, 0, ring_context->write_length * sizeof(uint32_t));
+			memset((void *)ring_context->bo_cpu, 0,
+			       ring_context->write_length * sizeof(uint32_t));
 
 			ring_context->resources[0] = ring_context->bo;
 
-			ip_block->funcs->write_linear(ip_block->funcs, ring_context, &ring_context->pm4_dw);
+			ip_block->funcs->write_linear(ip_block->funcs, ring_context,
+						      &ring_context->pm4_dw);
 
 			ring_context->ring_id = ring_id;
 
@@ -200,9 +243,14 @@ void amdgpu_command_submission_write_linear_helper(amdgpu_device_handle device,
 	}
 	/* clean resources */
 	free(ring_context->pm4);
-	/* end of test */
-	r = amdgpu_cs_ctx_free(ring_context->context_handle);
-	igt_assert_eq(r, 0);
+
+	if (user_queue) {
+		amdgpu_user_queue_destroy(device, ring_context, ip_block->type);
+	} else {
+		r = amdgpu_cs_ctx_free(ring_context->context_handle);
+		igt_assert_eq(r, 0);
+	}
+
 	free(ring_context);
 }
 
@@ -211,9 +259,11 @@ void amdgpu_command_submission_write_linear_helper(amdgpu_device_handle device,
  *
  * @param device
  * @param ip_type
+ * @param user_queue
  */
 void amdgpu_command_submission_const_fill_helper(amdgpu_device_handle device,
-						 const struct amdgpu_ip_block_version *ip_block)
+						 const struct amdgpu_ip_block_version *ip_block,
+						 bool user_queue)
 {
 	const int sdma_write_length = 1024 * 1024;
 	const int pm4_dw = 256;
@@ -229,25 +279,43 @@ void amdgpu_command_submission_const_fill_helper(amdgpu_device_handle device,
 	ring_context->secure = false;
 	ring_context->pm4_size = pm4_dw;
 	ring_context->res_cnt = 1;
+	ring_context->user_queue = user_queue;
 	igt_assert(ring_context->pm4);
 	r = amdgpu_query_hw_ip_info(device, ip_block->type, 0, &ring_context->hw_ip_info);
 	igt_assert_eq(r, 0);
 
-	r = amdgpu_cs_ctx_create(device, &ring_context->context_handle);
-	igt_assert_eq(r, 0);
+	if (user_queue) {
+		amdgpu_user_queue_create(device, ring_context, ip_block->type);
+	} else {
+		r = amdgpu_cs_ctx_create(device, &ring_context->context_handle);
+		igt_assert_eq(r, 0);
+	}
+
 	for (ring_id = 0; (1 << ring_id) & ring_context->hw_ip_info.available_rings; ring_id++) {
 		/* prepare resource */
 		loop = 0;
 		ring_context->ring_id = ring_id;
 		while (loop < 2) {
 			/* allocate UC bo for sDMA use */
-			r = amdgpu_bo_alloc_and_map(device,
-					    ring_context->write_length, 4096,
-					    AMDGPU_GEM_DOMAIN_GTT,
-					    gtt_flags[loop], &ring_context->bo, (void **)&ring_context->bo_cpu,
-					    &ring_context->bo_mc, &ring_context->va_handle);
+			r = amdgpu_bo_alloc_and_map_sync(device, ring_context->write_length,
+							 4096, AMDGPU_GEM_DOMAIN_GTT,
+							 gtt_flags[loop],
+							 AMDGPU_VM_MTYPE_UC,
+							 &ring_context->bo,
+							 (void **)&ring_context->bo_cpu,
+							 &ring_context->bo_mc,
+							 &ring_context->va_handle,
+							 ring_context->timeline_syncobj_handle,
+							 ++ring_context->point, user_queue);
 			igt_assert_eq(r, 0);
 
+			if (user_queue) {
+				r = amdgpu_timeline_syncobj_wait(device,
+					ring_context->timeline_syncobj_handle,
+					ring_context->point);
+				igt_assert_eq(r, 0);
+			}
+
 			/* clear bo */
 			memset((void *)ring_context->bo_cpu, 0, ring_context->write_length);
 
@@ -270,9 +338,13 @@ void amdgpu_command_submission_const_fill_helper(amdgpu_device_handle device,
 	/* clean resources */
 	free(ring_context->pm4);
 
-	/* end of test */
-	r = amdgpu_cs_ctx_free(ring_context->context_handle);
-	igt_assert_eq(r, 0);
+	if (user_queue) {
+		amdgpu_user_queue_destroy(device, ring_context, ip_block->type);
+	} else {
+		r = amdgpu_cs_ctx_free(ring_context->context_handle);
+		igt_assert_eq(r, 0);
+	}
+
 	free(ring_context);
 }
 
@@ -280,9 +352,11 @@ void amdgpu_command_submission_const_fill_helper(amdgpu_device_handle device,
  *
  * @param device
  * @param ip_type
+ * @param user_queue
  */
 void amdgpu_command_submission_copy_linear_helper(amdgpu_device_handle device,
-						  const struct amdgpu_ip_block_version *ip_block)
+						  const struct amdgpu_ip_block_version *ip_block,
+						  bool user_queue)
 {
 	const int sdma_write_length = 1024;
 	const int pm4_dw = 256;
@@ -299,13 +373,18 @@ void amdgpu_command_submission_copy_linear_helper(amdgpu_device_handle device,
 	ring_context->secure = false;
 	ring_context->pm4_size = pm4_dw;
 	ring_context->res_cnt = 2;
+	ring_context->user_queue = user_queue;
 	igt_assert(ring_context->pm4);
 	r = amdgpu_query_hw_ip_info(device, ip_block->type, 0, &ring_context->hw_ip_info);
 	igt_assert_eq(r, 0);
 
 
-	r = amdgpu_cs_ctx_create(device, &ring_context->context_handle);
-	igt_assert_eq(r, 0);
+	if (user_queue) {
+		amdgpu_user_queue_create(device, ring_context, ip_block->type);
+	} else {
+		r = amdgpu_cs_ctx_create(device, &ring_context->context_handle);
+		igt_assert_eq(r, 0);
+	}
 
 	for (ring_id = 0; (1 << ring_id) & ring_context->hw_ip_info.available_rings; ring_id++) {
 		loop1 = loop2 = 0;
@@ -313,27 +392,50 @@ void amdgpu_command_submission_copy_linear_helper(amdgpu_device_handle device,
 	/* run 9 circle to test all mapping combination */
 		while (loop1 < 2) {
 			while (loop2 < 2) {
-			/* allocate UC bo1for sDMA use */
-				r = amdgpu_bo_alloc_and_map(device,
-						    ring_context->write_length, 4096,
-						    AMDGPU_GEM_DOMAIN_GTT,
-						    gtt_flags[loop1], &ring_context->bo,
-						    (void **)&ring_context->bo_cpu, &ring_context->bo_mc,
-						    &ring_context->va_handle);
+				/* allocate UC bo1for sDMA use */
+				r = amdgpu_bo_alloc_and_map_sync(device, ring_context->write_length,
+							4096, AMDGPU_GEM_DOMAIN_GTT,
+							gtt_flags[loop1],
+							AMDGPU_VM_MTYPE_UC,
+							&ring_context->bo,
+							(void **)&ring_context->bo_cpu,
+							&ring_context->bo_mc,
+							&ring_context->va_handle,
+							ring_context->timeline_syncobj_handle,
+							++ring_context->point, user_queue);
 				igt_assert_eq(r, 0);
 
+				if (user_queue) {
+					r = amdgpu_timeline_syncobj_wait(device,
+						ring_context->timeline_syncobj_handle,
+						ring_context->point);
+					igt_assert_eq(r, 0);
+				}
+
 				/* set bo_cpu */
 				memset((void *)ring_context->bo_cpu, ip_block->funcs->pattern, ring_context->write_length);
 
 				/* allocate UC bo2 for sDMA use */
-				r = amdgpu_bo_alloc_and_map(device,
-						    ring_context->write_length, 4096,
-						    AMDGPU_GEM_DOMAIN_GTT,
-						    gtt_flags[loop2], &ring_context->bo2,
-						    (void **)&ring_context->bo2_cpu, &ring_context->bo_mc2,
-						    &ring_context->va_handle2);
+				r = amdgpu_bo_alloc_and_map_sync(device,
+							ring_context->write_length,
+							4096, AMDGPU_GEM_DOMAIN_GTT,
+							gtt_flags[loop2],
+							AMDGPU_VM_MTYPE_UC,
+							&ring_context->bo2,
+							(void **)&ring_context->bo2_cpu,
+							&ring_context->bo_mc2,
+							&ring_context->va_handle2,
+							ring_context->timeline_syncobj_handle,
+							++ring_context->point, user_queue);
 				igt_assert_eq(r, 0);
 
+				if (user_queue) {
+					r = amdgpu_timeline_syncobj_wait(device,
+						ring_context->timeline_syncobj_handle,
+						ring_context->point);
+					igt_assert_eq(r, 0);
+				}
+
 				/* clear bo2_cpu */
 				memset((void *)ring_context->bo2_cpu, 0, ring_context->write_length);
 
@@ -357,11 +459,16 @@ void amdgpu_command_submission_copy_linear_helper(amdgpu_device_handle device,
 			loop1++;
 		}
 	}
+
 	/* clean resources */
 	free(ring_context->pm4);
 
-	/* end of test */
-	r = amdgpu_cs_ctx_free(ring_context->context_handle);
-	igt_assert_eq(r, 0);
+	if (user_queue) {
+		amdgpu_user_queue_destroy(device, ring_context, ip_block->type);
+	} else {
+		r = amdgpu_cs_ctx_free(ring_context->context_handle);
+		igt_assert_eq(r, 0);
+	}
+
 	free(ring_context);
 }
diff --git a/lib/amdgpu/amd_command_submission.h b/lib/amdgpu/amd_command_submission.h
index e3139a402..d0139b364 100644
--- a/lib/amdgpu/amd_command_submission.h
+++ b/lib/amdgpu/amd_command_submission.h
@@ -34,11 +34,13 @@ int amdgpu_test_exec_cs_helper(amdgpu_device_handle device,
 
 void amdgpu_command_submission_write_linear_helper(amdgpu_device_handle device,
 						   const struct amdgpu_ip_block_version *ip_block,
-						   bool secure);
+						   bool secure, bool user_queue);
 
 void amdgpu_command_submission_const_fill_helper(amdgpu_device_handle device,
-						 const struct amdgpu_ip_block_version *ip_block);
+						 const struct amdgpu_ip_block_version *ip_block,
+						 bool user_queue);
 
 void amdgpu_command_submission_copy_linear_helper(amdgpu_device_handle device,
-						 const struct amdgpu_ip_block_version *ip_block);
+						 const struct amdgpu_ip_block_version *ip_block,
+						 bool user_queue);
 #endif
diff --git a/lib/amdgpu/amd_compute.c b/lib/amdgpu/amd_compute.c
index 6e61f1820..5d7040d80 100644
--- a/lib/amdgpu/amd_compute.c
+++ b/lib/amdgpu/amd_compute.c
@@ -25,12 +25,14 @@
 #include "amd_PM4.h"
 #include "amd_memory.h"
 #include "amd_compute.h"
+#include "amd_user_queue.h"
 
 /**
  *
  * @param device
+ * @param user_queue
  */
-void amdgpu_command_submission_compute_nop(amdgpu_device_handle device)
+void amdgpu_command_submission_compute_nop(amdgpu_device_handle device, bool user_queue)
 {
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle ib_result_handle;
@@ -46,19 +48,38 @@ void amdgpu_command_submission_compute_nop(amdgpu_device_handle device)
 	amdgpu_bo_list_handle bo_list;
 	amdgpu_va_handle va_handle;
 
+	struct amdgpu_ring_context *ring_context;
+
+	ring_context = calloc(1, sizeof(*ring_context));
+	igt_assert(ring_context);
+
 	r = amdgpu_query_hw_ip_info(device, AMDGPU_HW_IP_COMPUTE, 0, &info);
 	igt_assert_eq(r, 0);
 
-	r = amdgpu_cs_ctx_create(device, &context_handle);
-	igt_assert_eq(r, 0);
+	if (user_queue) {
+		amdgpu_user_queue_create(device, ring_context, AMD_IP_COMPUTE);
+	} else {
+		r = amdgpu_cs_ctx_create(device, &context_handle);
+		igt_assert_eq(r, 0);
+	}
 
 	for (instance = 0; info.available_rings & (1 << instance); instance++) {
-		r = amdgpu_bo_alloc_and_map(device, 4096, 4096,
-					    AMDGPU_GEM_DOMAIN_GTT, 0,
-					    &ib_result_handle, &ib_result_cpu,
-					    &ib_result_mc_address, &va_handle);
+		r = amdgpu_bo_alloc_and_map_sync(device, 4096, 4096,
+						 AMDGPU_GEM_DOMAIN_GTT, 0,
+						 AMDGPU_VM_MTYPE_UC,
+						 &ib_result_handle, (void **)&ib_result_cpu,
+						 &ib_result_mc_address, &va_handle,
+						 ring_context->timeline_syncobj_handle,
+						 ++ring_context->point, user_queue);
 		igt_assert_eq(r, 0);
 
+		if (user_queue) {
+			r = amdgpu_timeline_syncobj_wait(device,
+							 ring_context->timeline_syncobj_handle,
+							 ring_context->point);
+			igt_assert_eq(r, 0);
+		}
+
 		r = amdgpu_get_bo_list(device, ib_result_handle, NULL,
 				       &bo_list);
 		igt_assert_eq(r, 0);
@@ -66,42 +87,53 @@ void amdgpu_command_submission_compute_nop(amdgpu_device_handle device)
 		ptr = ib_result_cpu;
 		memset(ptr, 0, 16);
 		ptr[0] = PACKET3(PACKET3_NOP, 14);
+		ring_context->pm4_dw = 16;
 
-		memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
-		ib_info.ib_mc_address = ib_result_mc_address;
-		ib_info.size = 16;
-
-		memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
-		ibs_request.ip_type = AMDGPU_HW_IP_COMPUTE;
-		ibs_request.ring = instance;
-		ibs_request.number_of_ibs = 1;
-		ibs_request.ibs = &ib_info;
-		ibs_request.resources = bo_list;
-		ibs_request.fence_info.handle = NULL;
+		if (user_queue) {
+			amdgpu_user_queue_submit(device, ring_context, AMD_IP_COMPUTE,
+						 ib_result_mc_address);
+		} else {
+			memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
+			ib_info.ib_mc_address = ib_result_mc_address;
+			ib_info.size = 16;
 
-		memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
-		r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
-		igt_assert_eq(r, 0);
+			memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
+			ibs_request.ip_type = AMDGPU_HW_IP_COMPUTE;
+			ibs_request.ring = instance;
+			ibs_request.number_of_ibs = 1;
+			ibs_request.ibs = &ib_info;
+			ibs_request.resources = bo_list;
+			ibs_request.fence_info.handle = NULL;
 
-		fence_status.context = context_handle;
-		fence_status.ip_type = AMDGPU_HW_IP_COMPUTE;
-		fence_status.ip_instance = 0;
-		fence_status.ring = instance;
-		fence_status.fence = ibs_request.seq_no;
+			memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+			r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
+			igt_assert_eq(r, 0);
 
-		r = amdgpu_cs_query_fence_status(&fence_status,
-						 AMDGPU_TIMEOUT_INFINITE,
-						 0, &expired);
-		igt_assert_eq(r, 0);
+			fence_status.context = context_handle;
+			fence_status.ip_type = AMDGPU_HW_IP_COMPUTE;
+			fence_status.ip_instance = 0;
+			fence_status.ring = instance;
+			fence_status.fence = ibs_request.seq_no;
 
-		r = amdgpu_bo_list_destroy(bo_list);
-		igt_assert_eq(r, 0);
+			r = amdgpu_cs_query_fence_status(&fence_status,
+							 AMDGPU_TIMEOUT_INFINITE,
+							 0, &expired);
+			igt_assert_eq(r, 0);
 
+			r = amdgpu_bo_list_destroy(bo_list);
+			igt_assert_eq(r, 0);
+		}
 		amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
 					 ib_result_mc_address, 4096);
 	}
 
-	r = amdgpu_cs_ctx_free(context_handle);
-	igt_assert_eq(r, 0);
+	if (user_queue) {
+		amdgpu_user_queue_destroy(device, ring_context, AMD_IP_COMPUTE);
+	} else {
+		r = amdgpu_cs_ctx_free(context_handle);
+		igt_assert_eq(r, 0);
+	}
+
+	free(ring_context);
 }
 
diff --git a/lib/amdgpu/amd_compute.h b/lib/amdgpu/amd_compute.h
index f27be5f17..41ed225b8 100644
--- a/lib/amdgpu/amd_compute.h
+++ b/lib/amdgpu/amd_compute.h
@@ -26,6 +26,6 @@
 #define AMD_COMPUTE_H
 
 
-void amdgpu_command_submission_compute_nop(amdgpu_device_handle device);
+void amdgpu_command_submission_compute_nop(amdgpu_device_handle device, bool user_queue);
 
 #endif
diff --git a/tests/amdgpu/amd_basic.c b/tests/amdgpu/amd_basic.c
index 8819b9cd4..b05633b8e 100644
--- a/tests/amdgpu/amd_basic.c
+++ b/tests/amdgpu/amd_basic.c
@@ -13,6 +13,7 @@
 #include "lib/amdgpu/amd_gfx.h"
 #include "lib/amdgpu/amd_shaders.h"
 #include "lib/amdgpu/amd_dispatch.h"
+#include "lib/amdgpu/amd_user_queue.h"
 
 #define BUFFER_SIZE (8 * 1024)
 
@@ -67,14 +68,25 @@ static void amdgpu_memory_alloc(amdgpu_device_handle device)
  * AMDGPU_HW_IP_GFX
  * @param device
  */
-static void amdgpu_command_submission_gfx(amdgpu_device_handle device, bool ce_avails)
+static void amdgpu_command_submission_gfx(amdgpu_device_handle device,
+					  bool ce_avails,
+					  bool user_queue)
 {
+
 	/* write data using the CP */
-	amdgpu_command_submission_write_linear_helper(device, get_ip_block(device, AMDGPU_HW_IP_GFX), false);
+	amdgpu_command_submission_write_linear_helper(device,
+						      get_ip_block(device, AMDGPU_HW_IP_GFX),
+						      false, user_queue);
+
 	/* const fill using the CP */
-	amdgpu_command_submission_const_fill_helper(device, get_ip_block(device, AMDGPU_HW_IP_GFX));
+	amdgpu_command_submission_const_fill_helper(device,
+						    get_ip_block(device, AMDGPU_HW_IP_GFX),
+						    user_queue);
+
 	/* copy data using the CP */
-	amdgpu_command_submission_copy_linear_helper(device, get_ip_block(device, AMDGPU_HW_IP_GFX));
+	amdgpu_command_submission_copy_linear_helper(device,
+						     get_ip_block(device, AMDGPU_HW_IP_GFX),
+						     user_queue);
 	if (ce_avails) {
 		/* separate IB buffers for multi-IB submission */
 		amdgpu_command_submission_gfx_separate_ibs(device);
@@ -89,27 +101,41 @@ static void amdgpu_command_submission_gfx(amdgpu_device_handle device, bool ce_a
  * AMDGPU_HW_IP_COMPUTE
  * @param device
  */
-static void amdgpu_command_submission_compute(amdgpu_device_handle device)
+static void amdgpu_command_submission_compute(amdgpu_device_handle device, bool user_queue)
 {
 	/* write data using the CP */
-	amdgpu_command_submission_write_linear_helper(device, get_ip_block(device, AMDGPU_HW_IP_COMPUTE), false);
+	amdgpu_command_submission_write_linear_helper(device,
+						      get_ip_block(device, AMDGPU_HW_IP_COMPUTE),
+						      false, user_queue);
 	/* const fill using the CP */
-	amdgpu_command_submission_const_fill_helper(device, get_ip_block(device, AMDGPU_HW_IP_COMPUTE));
+	amdgpu_command_submission_const_fill_helper(device,
+						    get_ip_block(device, AMDGPU_HW_IP_COMPUTE),
+						    user_queue);
 	/* copy data using the CP */
-	amdgpu_command_submission_copy_linear_helper(device, get_ip_block(device, AMDGPU_HW_IP_COMPUTE));
+	amdgpu_command_submission_copy_linear_helper(device,
+						     get_ip_block(device, AMDGPU_HW_IP_COMPUTE),
+						     user_queue);
 	/* nop test */
-	amdgpu_command_submission_compute_nop(device);
+	amdgpu_command_submission_compute_nop(device, user_queue);
 }
 
 /**
  * AMDGPU_HW_IP_DMA
  * @param device
  */
-static void amdgpu_command_submission_sdma(amdgpu_device_handle device)
+static void amdgpu_command_submission_sdma(amdgpu_device_handle device, bool user_queue)
 {
-	amdgpu_command_submission_write_linear_helper(device,  get_ip_block(device, AMDGPU_HW_IP_DMA), false);
-	amdgpu_command_submission_const_fill_helper(device,  get_ip_block(device, AMDGPU_HW_IP_DMA));
-	amdgpu_command_submission_copy_linear_helper(device,  get_ip_block(device, AMDGPU_HW_IP_DMA));
+	amdgpu_command_submission_write_linear_helper(device,
+						      get_ip_block(device, AMDGPU_HW_IP_DMA),
+						      false, user_queue);
+
+	amdgpu_command_submission_const_fill_helper(device,
+						    get_ip_block(device, AMDGPU_HW_IP_DMA),
+						    user_queue);
+
+	amdgpu_command_submission_copy_linear_helper(device,
+						     get_ip_block(device, AMDGPU_HW_IP_DMA),
+						     user_queue);
 }
 
 /**
@@ -667,7 +693,7 @@ igt_main
 	igt_subtest_with_dynamic("cs-gfx-with-IP-GFX") {
 		if (arr_cap[AMD_IP_GFX]) {
 			igt_dynamic_f("cs-gfx")
-			amdgpu_command_submission_gfx(device, info.hw_ip_version_major < 11);
+			amdgpu_command_submission_gfx(device, info.hw_ip_version_major < 11, false);
 		}
 	}
 
@@ -675,7 +701,7 @@ igt_main
 	igt_subtest_with_dynamic("cs-compute-with-IP-COMPUTE") {
 		if (arr_cap[AMD_IP_COMPUTE]) {
 			igt_dynamic_f("cs-compute")
-			amdgpu_command_submission_compute(device);
+			amdgpu_command_submission_compute(device, false);
 		}
 	}
 
@@ -693,7 +719,7 @@ igt_main
 	igt_subtest_with_dynamic("cs-sdma-with-IP-DMA") {
 		if (arr_cap[AMD_IP_DMA]) {
 			igt_dynamic_f("cs-sdma")
-			amdgpu_command_submission_sdma(device);
+			amdgpu_command_submission_sdma(device, false);
 		}
 	}
 
diff --git a/tests/amdgpu/amd_security.c b/tests/amdgpu/amd_security.c
index 024cadc05..19baaaea0 100644
--- a/tests/amdgpu/amd_security.c
+++ b/tests/amdgpu/amd_security.c
@@ -341,12 +341,12 @@ igt_main
 	igt_describe("amdgpu sdma command submission write linear helper");
 	igt_subtest("sdma-write-linear-helper-secure")
 	amdgpu_command_submission_write_linear_helper(device,
-			get_ip_block(device, AMDGPU_HW_IP_DMA), is_secure);
+			get_ip_block(device, AMDGPU_HW_IP_DMA), is_secure, false);
 
 	igt_describe("amdgpu gfx command submission write linear helper");
 	igt_subtest("gfx-write-linear-helper-secure")
 	 amdgpu_command_submission_write_linear_helper(device,
-			get_ip_block(device, AMDGPU_HW_IP_GFX), is_secure);
+			get_ip_block(device, AMDGPU_HW_IP_GFX), is_secure, false);
 
 	/* dynamic test based on sdma_info.available rings */
 	igt_describe("amdgpu secure bounce");
-- 
2.43.0

[PATCH v3 07/19] tests/amdgpu: Add UMQ submission tests for gfx and compute

[Sunil Khatri]

We already have the gfx and compute ip user mode submission
support added in the IGT and hence with this patch we are
adding a new test case for gfx and compute using UMQ
submission.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 tests/amdgpu/amd_basic.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/tests/amdgpu/amd_basic.c b/tests/amdgpu/amd_basic.c
index b05633b8e..2b339c74b 100644
--- a/tests/amdgpu/amd_basic.c
+++ b/tests/amdgpu/amd_basic.c
@@ -747,6 +747,22 @@ igt_main
 		}
 	}
 
+	igt_describe("Check-GFX-CS-for-every-available-ring-works-for-write-const-fill-and-copy-operation-using-more-than-one-IB-and-shared-IB");
+	igt_subtest_with_dynamic("cs-gfx-with-IP-GFX-UMQ") {
+		if (arr_cap[AMD_IP_GFX]) {
+			igt_dynamic_f("cs-gfx-with-umq")
+			amdgpu_command_submission_gfx(device, info.hw_ip_version_major < 11, true);
+		}
+	}
+
+	igt_describe("Check-COMPUTE-CS-for-every-available-ring-works-for-write-const-fill-copy-and-nop-operation");
+	igt_subtest_with_dynamic("cs-compute-with-IP-COMPUTE-UMQ") {
+		if (arr_cap[AMD_IP_COMPUTE]) {
+			igt_dynamic_f("cs-compute-with-umq")
+			amdgpu_command_submission_compute(device, true);
+		}
+	}
+
 	igt_fixture {
 		amdgpu_device_deinitialize(device);
 		drm_close_driver(fd);
-- 
2.43.0

[PATCH v3 08/19] tests/amdgpu: Add amdgpu_sync_dependency_test with UMQ

[Sunil Khatri]

Add UMQ support in amdgpu_sync_dependency_test and also
add a new test case which will run this test for UMQ
submission.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 tests/amdgpu/amd_basic.c | 95 ++++++++++++++++++++++++++++++----------
 1 file changed, 72 insertions(+), 23 deletions(-)

diff --git a/tests/amdgpu/amd_basic.c b/tests/amdgpu/amd_basic.c
index 2b339c74b..643a147f5 100644
--- a/tests/amdgpu/amd_basic.c
+++ b/tests/amdgpu/amd_basic.c
@@ -475,7 +475,7 @@ amdgpu_bo_eviction_test(amdgpu_device_handle device_handle)
 }
 
 static void
-amdgpu_sync_dependency_test(amdgpu_device_handle device_handle)
+amdgpu_sync_dependency_test(amdgpu_device_handle device_handle, bool user_queue)
 {
 	const unsigned const_size = 8192;
 	const unsigned const_alignment = 4096;
@@ -498,25 +498,44 @@ amdgpu_sync_dependency_test(amdgpu_device_handle device_handle)
 
 	uint32_t size_bytes, code_offset, data_offset;
 	const uint32_t *shader;
+	struct amdgpu_ring_context *ring_context;
 
 	struct amdgpu_cmd_base *base = get_cmd_base();
 	const struct amdgpu_ip_block_version *ip_block = get_ip_block(device_handle, AMD_IP_GFX);
 
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle[0]);
-	igt_assert_eq(r, 0);
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle[1]);
-	igt_assert_eq(r, 0);
+	ring_context = calloc(1, sizeof(*ring_context));
+	igt_assert(ring_context);
 
-	r = amdgpu_bo_alloc_and_map(device_handle, const_size, const_alignment,
-			AMDGPU_GEM_DOMAIN_GTT, 0,
-			&ib_result_handle, &ib_result_cpu,
-			&ib_result_mc_address, &va_handle);
+	if (user_queue) {
+		amdgpu_user_queue_create(device_handle, ring_context, ip_block->type);
+	} else {
+		r = amdgpu_cs_ctx_create(device_handle, &context_handle[0]);
+		igt_assert_eq(r, 0);
+
+		r = amdgpu_cs_ctx_create(device_handle, &context_handle[1]);
+		igt_assert_eq(r, 0);
+	}
+
+	r = amdgpu_bo_alloc_and_map_sync(device_handle, const_size,
+					 const_alignment, AMDGPU_GEM_DOMAIN_GTT, 0,
+					 AMDGPU_VM_MTYPE_UC,
+					 &ib_result_handle, &ib_result_cpu,
+					 &ib_result_mc_address, &va_handle,
+					 ring_context->timeline_syncobj_handle,
+					 ++ring_context->point, user_queue);
 
 	igt_assert_eq(r, 0);
 
-	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+	if (user_queue) {
+		r = amdgpu_timeline_syncobj_wait(device_handle,
+						 ring_context->timeline_syncobj_handle,
+						 ring_context->point);
+		igt_assert_eq(r, 0);
+	} else {
+		r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
 			       &bo_list);
-	igt_assert_eq(r, 0);
+		igt_assert_eq(r, 0);
+	}
 
 	shader = get_shader_bin(&size_bytes, &code_offset, &data_offset);
 
@@ -585,7 +604,14 @@ amdgpu_sync_dependency_test(amdgpu_device_handle device_handle)
 	ibs_request.resources = bo_list;
 	ibs_request.fence_info.handle = NULL;
 
-	r = amdgpu_cs_submit(context_handle[1], 0, &ibs_request, 1);
+	if (user_queue) {
+		ring_context->pm4_dw = ib_info.size;
+		amdgpu_user_queue_submit(device_handle, ring_context, ip_block->type,
+					 ib_result_mc_address);
+	} else {
+		r = amdgpu_cs_submit(context_handle[1], 0, &ibs_request, 1);
+	}
+
 	igt_assert_eq(r, 0);
 	seq_no = ibs_request.seq_no;
 
@@ -618,8 +644,14 @@ amdgpu_sync_dependency_test(amdgpu_device_handle device_handle)
 	ibs_request.dependencies[0].ring = 0;
 	ibs_request.dependencies[0].fence = seq_no;
 
-	r = amdgpu_cs_submit(context_handle[0], 0, &ibs_request, 1);
-	igt_assert_eq(r, 0);
+	if (user_queue) {
+		ring_context->pm4_dw = ib_info.size;
+		amdgpu_user_queue_submit(device_handle, ring_context, ip_block->type,
+					ib_info.ib_mc_address);
+	} else {
+		r = amdgpu_cs_submit(context_handle[0], 0, &ibs_request, 1);
+		igt_assert_eq(r, 0);
+	}
 
 	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
 	fence_status.context = context_handle[0];
@@ -628,24 +660,33 @@ amdgpu_sync_dependency_test(amdgpu_device_handle device_handle)
 	fence_status.ring = 0;
 	fence_status.fence = ibs_request.seq_no;
 
-	r = amdgpu_cs_query_fence_status(&fence_status,
+	if (!user_queue) {
+		r = amdgpu_cs_query_fence_status(&fence_status,
 		       AMDGPU_TIMEOUT_INFINITE, 0, &expired);
-	igt_assert_eq(r, 0);
+		igt_assert_eq(r, 0);
+	}
 
 	/* Expect the second command to wait for shader to complete */
 	igt_assert_eq(base->buf[data_offset], 99);
 
-	r = amdgpu_bo_list_destroy(bo_list);
-	igt_assert_eq(r, 0);
+	if (!user_queue) {
+		r = amdgpu_bo_list_destroy(bo_list);
+		igt_assert_eq(r, 0);
+	}
 
-	 amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
-				     ib_result_mc_address, const_alignment);
+	amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+				 ib_result_mc_address, const_alignment);
 
-	amdgpu_cs_ctx_free(context_handle[0]);
-	amdgpu_cs_ctx_free(context_handle[1]);
+	if (user_queue) {
+		amdgpu_user_queue_destroy(device_handle, ring_context, ip_block->type);
+	} else {
+		amdgpu_cs_ctx_free(context_handle[0]);
+		amdgpu_cs_ctx_free(context_handle[1]);
+	}
 
 	free(ibs_request.dependencies);
 	free_cmd_base(base);
+	free(ring_context);
 }
 
 igt_main
@@ -743,7 +784,7 @@ igt_main
 	igt_subtest_with_dynamic("sync-dependency-test-with-IP-GFX") {
 		if (arr_cap[AMD_IP_GFX]) {
 			igt_dynamic_f("sync-dependency-test")
-			amdgpu_sync_dependency_test(device);
+			amdgpu_sync_dependency_test(device, false);
 		}
 	}
 
@@ -763,6 +804,14 @@ igt_main
 		}
 	}
 
+	igt_describe("Check-sync-dependency-using-GFX-ring");
+	igt_subtest_with_dynamic("sync-dependency-test-with-IP-GFX-UMQ") {
+		if (arr_cap[AMD_IP_GFX]) {
+			igt_dynamic_f("sync-dependency-test-with-umq")
+			amdgpu_sync_dependency_test(device, true);
+		}
+	}
+
 	igt_fixture {
 		amdgpu_device_deinitialize(device);
 		drm_close_driver(fd);
-- 
2.43.0

[PATCH v3 09/19] tests/amdgpu: use memory API's from amd_memory.h

[Sunil Khatri]

Use memory allocation API's from memory.h library
header instead of using a local definition.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 tests/amdgpu/amd_cs_nop.c | 65 +--------------------------------------
 1 file changed, 1 insertion(+), 64 deletions(-)

diff --git a/tests/amdgpu/amd_cs_nop.c b/tests/amdgpu/amd_cs_nop.c
index 5f7acb497..720b276df 100644
--- a/tests/amdgpu/amd_cs_nop.c
+++ b/tests/amdgpu/amd_cs_nop.c
@@ -11,70 +11,7 @@
 #include <amdgpu_drm.h>
 #include "lib/amdgpu/amd_PM4.h"
 #include "lib/amdgpu/amd_ip_blocks.h"
-
-
-static int
-amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned int size,
-			unsigned int alignment, unsigned int heap, uint64_t flags,
-			amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address,
-			amdgpu_va_handle *va_handle)
-{
-	struct amdgpu_bo_alloc_request request = {
-		.alloc_size = size,
-		.phys_alignment = alignment,
-		.preferred_heap = heap,
-		.flags = flags,
-	};
-	amdgpu_bo_handle buf_handle;
-	amdgpu_va_handle handle;
-	uint64_t vmc_addr;
-	int r;
-
-	r = amdgpu_bo_alloc(dev, &request, &buf_handle);
-	if (r)
-		return r;
-
-	r = amdgpu_va_range_alloc(dev,
-				  amdgpu_gpu_va_range_general,
-				  size, alignment, 0, &vmc_addr,
-				  &handle, 0);
-	if (r)
-		goto error_va_alloc;
-
-	r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_MAP);
-	if (r)
-		goto error_va_map;
-
-	r = amdgpu_bo_cpu_map(buf_handle, cpu);
-	if (r)
-		goto error_cpu_map;
-
-	*bo = buf_handle;
-	*mc_address = vmc_addr;
-	*va_handle = handle;
-
-	return 0;
-
-error_cpu_map:
-	amdgpu_bo_cpu_unmap(buf_handle);
-
-error_va_map:
-	amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
-
-error_va_alloc:
-	amdgpu_bo_free(buf_handle);
-	return r;
-}
-
-static void
-amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, amdgpu_va_handle va_handle,
-			 uint64_t mc_addr, uint64_t size)
-{
-	amdgpu_bo_cpu_unmap(bo);
-	amdgpu_bo_va_op(bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP);
-	amdgpu_va_range_free(va_handle);
-	amdgpu_bo_free(bo);
-}
+#include "lib/amdgpu/amd_memory.h"
 
 static void amdgpu_cs_sync(amdgpu_context_handle context,
 			   unsigned int ip_type,
-- 
2.43.0

[PATCH v3 10/19] lib/amdgpu: add macro for adding cmds in user queue

[Sunil Khatri]

Add macros which enable adding cmds in user queue
for size more than ring size. Ring is treate as
a circular buffer and ovewrite from beginning
when write ptr reaches the end of queue.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 lib/amdgpu/amd_user_queue.h | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/lib/amdgpu/amd_user_queue.h b/lib/amdgpu/amd_user_queue.h
index 355f16f19..539a78819 100644
--- a/lib/amdgpu/amd_user_queue.h
+++ b/lib/amdgpu/amd_user_queue.h
@@ -15,9 +15,24 @@
 #define PAGE_SIZE 4096
 #endif
 
-#define USERMODE_QUEUE_SIZE		(PAGE_SIZE * 256)   //In bytes
+#define USERMODE_QUEUE_SIZE		(PAGE_SIZE * 256)   //In bytes with total size as 1 Mbyte
 #define ALIGNMENT			4096
 #define DOORBELL_INDEX			4
+#define USERMODE_QUEUE_SIZE_DW		(USERMODE_QUEUE_SIZE >> 2)
+#define USERMODE_QUEUE_SIZE_DW_MASK	(USERMODE_QUEUE_SIZE_DW - 1)
+
+#define amdgpu_pkt_begin() uint32_t __num_dw_written = 0; \
+	uint32_t __ring_start = *ring_context->wptr_cpu & USERMODE_QUEUE_SIZE_DW_MASK;
+
+#define amdgpu_pkt_add_dw(value) do { \
+	*(ring_context->queue_cpu + \
+	((__ring_start + __num_dw_written) & USERMODE_QUEUE_SIZE_DW_MASK)) \
+	= value; \
+	__num_dw_written++;\
+} while (0)
+
+#define amdgpu_pkt_end() \
+	*ring_context->wptr_cpu += __num_dw_written
 
 void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle, struct amdgpu_userq_bo *doorbell_bo,
 			   unsigned int size, unsigned int domain);
-- 
2.43.0

[PATCH v3 11/19] lib/amdgpu: use macro to add cmds in the user ring

[Sunil Khatri]

Use ring add cmds macros to add the cmds in the user
ring instead of directly using the queue ptr and wptr
ptr.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 lib/amdgpu/amd_ip_blocks.h  |  1 -
 lib/amdgpu/amd_user_queue.c | 28 +++++++++++++++-------------
 2 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index 85d69f5c6..e085f1618 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -170,7 +170,6 @@ struct amdgpu_ring_context {
 
 	uint32_t db_handle;
 	uint32_t queue_id;
-	uint32_t npkt;
 
 	uint32_t timeline_syncobj_handle;
 	uint64_t point;
diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c
index 9412a37e8..1bfc86949 100644
--- a/lib/amdgpu/amd_user_queue.c
+++ b/lib/amdgpu/amd_user_queue.c
@@ -126,30 +126,32 @@ void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_co
 			      unsigned int ip_type, uint64_t mc_address)
 {
 	int r;
-	uint32_t *npkt = &ring_context->npkt;
-	uint32_t *queue_cpu = ring_context->queue_cpu;
 	uint32_t control = ring_context->pm4_dw;
 	uint32_t syncarray[1];
-
 	struct drm_amdgpu_userq_signal signal_data;
 
+
+	amdgpu_pkt_begin();
 	/* Prepare the Indirect IB to submit the IB to user queue */
-	queue_cpu[(*npkt)++] = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
-	queue_cpu[(*npkt)++] = lower_32_bits(mc_address);
-	queue_cpu[(*npkt)++] = upper_32_bits(mc_address);
+	amdgpu_pkt_add_dw(PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+	amdgpu_pkt_add_dw(lower_32_bits(mc_address));
+	amdgpu_pkt_add_dw(upper_32_bits(mc_address));
 
 	if (ip_type == AMD_IP_GFX)
-		queue_cpu[(*npkt)++] = control | S_3F3_INHERIT_VMID_MQD_GFX(1);
+		amdgpu_pkt_add_dw(control | S_3F3_INHERIT_VMID_MQD_GFX(1));
 	else
-		queue_cpu[(*npkt)++] = control | S_3F3_VALID_COMPUTE(1)
-					       | S_3F3_INHERIT_VMID_MQD_COMPUTE(1);
+		amdgpu_pkt_add_dw(control | S_3F3_VALID_COMPUTE(1)
+					       | S_3F3_INHERIT_VMID_MQD_COMPUTE(1));
+
+	amdgpu_pkt_add_dw(PACKET3(PACKET3_PROTECTED_FENCE_SIGNAL, 0));
 
-	queue_cpu[(*npkt)++] = PACKET3(PACKET3_PROTECTED_FENCE_SIGNAL, 0);
 	/* empty dword is needed for fence signal pm4 */
-	++*npkt;
+	amdgpu_pkt_add_dw(0);
+
+	amdgpu_pkt_end();
 
-	*ring_context->wptr_cpu = *npkt;
-	ring_context->doorbell_cpu[DOORBELL_INDEX] = *npkt;
+	/* Update the door bell */
+	ring_context->doorbell_cpu[DOORBELL_INDEX] = *ring_context->wptr_cpu;
 
 	/* Add a fence packet for signal */
 	syncarray[0] = ring_context->timeline_syncobj_handle;
-- 
2.43.0

[PATCH v3 12/19] tests/amdgpu: Add amdgpu_cp_nops tests for UMQ

[Sunil Khatri]

Add new tests to support amdgpu_cs_nops tests for UMQ
submission by modifying the existing cs_nops tests
to support UMQ.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 tests/amdgpu/amd_cs_nop.c | 77 +++++++++++++++++++++++++++++++--------
 1 file changed, 61 insertions(+), 16 deletions(-)

diff --git a/tests/amdgpu/amd_cs_nop.c b/tests/amdgpu/amd_cs_nop.c
index 720b276df..96a15a029 100644
--- a/tests/amdgpu/amd_cs_nop.c
+++ b/tests/amdgpu/amd_cs_nop.c
@@ -12,6 +12,7 @@
 #include "lib/amdgpu/amd_PM4.h"
 #include "lib/amdgpu/amd_ip_blocks.h"
 #include "lib/amdgpu/amd_memory.h"
+#include "lib/amdgpu/amd_user_queue.h"
 
 static void amdgpu_cs_sync(amdgpu_context_handle context,
 			   unsigned int ip_type,
@@ -41,7 +42,8 @@ static void nop_cs(amdgpu_device_handle device,
 		   unsigned int ip_type,
 		   unsigned int ring,
 		   unsigned int timeout,
-		   unsigned int flags)
+		   unsigned int flags,
+		   bool user_queue)
 {
 	const int ncpus = flags & FORK ? sysconf(_SC_NPROCESSORS_ONLN) : 1;
 	amdgpu_bo_handle ib_result_handle;
@@ -51,19 +53,36 @@ static void nop_cs(amdgpu_device_handle device,
 	int i, r;
 	amdgpu_bo_list_handle bo_list;
 	amdgpu_va_handle va_handle;
+	struct amdgpu_ring_context *ring_context;
 
-	r = amdgpu_bo_alloc_and_map(device, 4096, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT, 0,
-				    &ib_result_handle, &ib_result_cpu,
-				    &ib_result_mc_address, &va_handle);
+	ring_context = calloc(1, sizeof(*ring_context));
+	igt_assert(ring_context);
+
+	if (user_queue)
+		amdgpu_user_queue_create(device, ring_context, ip_type);
+
+	r = amdgpu_bo_alloc_and_map_sync(device, 4096, 4096,
+					 AMDGPU_GEM_DOMAIN_GTT, 0, AMDGPU_VM_MTYPE_UC,
+					 &ib_result_handle, &ib_result_cpu,
+					 &ib_result_mc_address, &va_handle,
+					 ring_context->timeline_syncobj_handle,
+					 ++ring_context->point, user_queue);
 	igt_assert_eq(r, 0);
 
+	if (user_queue) {
+		r = amdgpu_timeline_syncobj_wait(device, ring_context->timeline_syncobj_handle,
+						 ring_context->point);
+		igt_assert_eq(r, 0);
+	}
+
 	ptr = ib_result_cpu;
 	for (i = 0; i < 16; ++i)
 		ptr[i] = GFX_COMPUTE_NOP;
 
-	r = amdgpu_bo_list_create(device, 1, &ib_result_handle, NULL, &bo_list);
-	igt_assert_eq(r, 0);
+	if (!user_queue) {
+		r = amdgpu_bo_list_create(device, 1, &ib_result_handle, NULL, &bo_list);
+		igt_assert_eq(r, 0);
+	}
 
 	igt_fork(child, ncpus) {
 		struct amdgpu_cs_request ibs_request;
@@ -86,16 +105,25 @@ static void nop_cs(amdgpu_device_handle device,
 		count = 0;
 		igt_nsec_elapsed(&tv);
 		igt_until_timeout(timeout) {
-			r = amdgpu_cs_submit(context, 0, &ibs_request, 1);
-			igt_assert_eq(r, 0);
-			if (flags & SYNC)
-				amdgpu_cs_sync(context, ip_type, ring,
-					       ibs_request.seq_no);
+			if (user_queue) {
+				ring_context->pm4_dw = ib_info.size;
+				amdgpu_user_queue_submit(device, ring_context, ip_type,
+							 ib_info.ib_mc_address);
+				igt_assert_eq(r, 0);
+			} else {
+				r = amdgpu_cs_submit(context, 0, &ibs_request, 1);
+				igt_assert_eq(r, 0);
+				if (flags & SYNC)
+					amdgpu_cs_sync(context, ip_type, ring,
+						       ibs_request.seq_no);
+			}
+
 			count++;
 		}
 		submit_ns = igt_nsec_elapsed(&tv);
+		if (!user_queue)
+			amdgpu_cs_sync(context, ip_type, ring, ibs_request.seq_no);
 
-		amdgpu_cs_sync(context, ip_type, ring, ibs_request.seq_no);
 		sync_ns = igt_nsec_elapsed(&tv);
 
 		igt_info("%s.%d: %'lu cycles, submit %.2fus, sync %.2fus\n",
@@ -104,11 +132,14 @@ static void nop_cs(amdgpu_device_handle device,
 	}
 	igt_waitchildren();
 
-	r = amdgpu_bo_list_destroy(bo_list);
-	igt_assert_eq(r, 0);
+	if (!user_queue) {
+		r = amdgpu_bo_list_destroy(bo_list);
+		igt_assert_eq(r, 0);
+	}
 
 	amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
 				 ib_result_mc_address, 4096);
+	free(ring_context);
 }
 
 igt_main
@@ -156,7 +187,21 @@ igt_main
 			igt_subtest_with_dynamic_f("cs-nops-with-%s-%s0", p->name, e->name) {
 				if (arr_cap[e->ip_type]) {
 					igt_dynamic_f("cs-nop-with-%s-%s0", p->name, e->name)
-					nop_cs(device, context, e->name, e->ip_type, 0, 20, p->flags);
+					nop_cs(device, context, e->name, e->ip_type, 0, 20,
+					       p->flags, 0);
+				}
+			}
+		}
+	}
+
+	for (p = phase; p->name; p++) {
+		for (e = engines; e->name; e++) {
+			igt_describe("Stressful-and-multiple-cs-of-nop-operations-using-multiple-processes-with-the-same-GPU-context-UMQ");
+			igt_subtest_with_dynamic_f("cs-nops-with-%s-%s0-with-UQ-Submission", p->name, e->name) {
+				if (arr_cap[e->ip_type]) {
+					igt_dynamic_f("cs-nop-with-%s-%s0-with-UQ-Submission", p->name, e->name)
+					nop_cs(device, context, e->name, e->ip_type, 0, 20,
+					       p->flags, 1);
 				}
 			}
 		}
-- 
2.43.0

[PATCH v3 13/19] drm-uapi/amdgpu: sync with drm-next

[Sunil Khatri]

Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")

Adds a new subquery (AMDGPU_INFO_UQ_FW_AREAS) in
AMDGPU_INFO_IOCTL to get the size and alignment of shadow
and csa objects from the FW setup. This information is
required for the userqueue consumers.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 include/drm-uapi/amdgpu_drm.h | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index fed39c9b4..8108c0c8a 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -1439,6 +1439,27 @@ struct drm_amdgpu_info_hw_ip {
 	__u32  ip_discovery_version;
 };
 
+/* GFX metadata BO sizes and alignment info (in bytes) */
+struct drm_amdgpu_info_uq_fw_areas_gfx {
+	/* shadow area size */
+	__u32 shadow_size;
+	/* shadow area base virtual mem alignment */
+	__u32 shadow_alignment;
+	/* context save area size */
+	__u32 csa_size;
+	/* context save area base virtual mem alignment */
+	__u32 csa_alignment;
+};
+
+/* IP specific metadata related information used in the
+ * subquery AMDGPU_INFO_UQ_FW_AREAS
+ */
+struct drm_amdgpu_info_uq_fw_areas {
+	union {
+		struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
+	};
+};
+
 struct drm_amdgpu_info_num_handles {
 	/** Max handles as supported by firmware for UVD */
 	__u32  uvd_max_handles;
-- 
2.43.0

[PATCH v3 14/19] lib/amdgpu: use right API to get the correct size

[Sunil Khatri]

Use amdgpu_query_uq_fw_area_info api to get the
sizes and alignment for shadow and csa.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 lib/amdgpu/amd_ip_blocks.h  |  2 +-
 lib/amdgpu/amd_user_queue.c | 21 ++++++++++-----------
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index e085f1618..231098eb8 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -175,7 +175,7 @@ struct amdgpu_ring_context {
 	uint64_t point;
 	bool user_queue;
 
-	struct drm_amdgpu_info_device dev_info;
+	struct drm_amdgpu_info_uq_fw_areas info;
 };
 
 
diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c
index 1bfc86949..d1763f5d6 100644
--- a/lib/amdgpu/amd_user_queue.c
+++ b/lib/amdgpu/amd_user_queue.c
@@ -189,13 +189,13 @@ void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu
 	case AMD_IP_GFX:
 		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->csa.handle,
 					    ctxt->csa.va_handle,
-					    ctxt->csa.mc_addr, ctxt->dev_info.csa_size,
+					    ctxt->csa.mc_addr, ctxt->info.gfx.csa_size,
 					    ctxt->timeline_syncobj_handle, ++ctxt->point,
 					    0, 0);
 
 		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->shadow.handle,
 					    ctxt->shadow.va_handle,
-					    ctxt->shadow.mc_addr, ctxt->dev_info.shadow_size,
+					    ctxt->shadow.mc_addr, ctxt->info.gfx.shadow_size,
 					    ctxt->timeline_syncobj_handle, ++ctxt->point,
 					    0, 0);
 
@@ -219,7 +219,7 @@ void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu
 	case AMD_IP_DMA:
 		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->csa.handle,
 					    ctxt->csa.va_handle,
-					    ctxt->csa.mc_addr, ctxt->dev_info.csa_size,
+					    ctxt->csa.mc_addr, ctxt->info.gfx.csa_size,
 					    ctxt->timeline_syncobj_handle, ++ctxt->point,
 					    0, 0);
 
@@ -268,8 +268,7 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
 		return;
 	}
 
-	r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO,
-			      sizeof(ctxt->dev_info), &ctxt->dev_info);
+	r = amdgpu_query_uq_fw_area_info(device_handle, AMD_IP_GFX, 0, &ctxt->info);
 	igt_assert_eq(r, 0);
 
 	r = amdgpu_cs_create_syncobj2(device_handle, 0, &ctxt->timeline_syncobj_handle);
@@ -307,8 +306,8 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
 
 	switch (type) {
 	case AMD_IP_GFX:
-		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.shadow_size,
-					       ctxt->dev_info.shadow_alignment,
+		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->info.gfx.shadow_size,
+					       ctxt->info.gfx.shadow_alignment,
 					       AMDGPU_GEM_DOMAIN_GTT,
 					       gtt_flags,
 					       AMDGPU_VM_MTYPE_UC,
@@ -317,8 +316,8 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
 					       ctxt->timeline_syncobj_handle, ++ctxt->point);
 		igt_assert_eq(r, 0);
 
-		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.csa_size,
-					       ctxt->dev_info.csa_alignment,
+		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->info.gfx.csa_size,
+					       ctxt->info.gfx.csa_alignment,
 					       AMDGPU_GEM_DOMAIN_GTT,
 					       gtt_flags,
 					       AMDGPU_VM_MTYPE_UC,
@@ -347,8 +346,8 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
 		break;
 
 	case AMD_IP_DMA:
-		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.csa_size,
-					       ctxt->dev_info.csa_alignment,
+		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->info.gfx.csa_size,
+					       ctxt->info.gfx.csa_alignment,
 					       AMDGPU_GEM_DOMAIN_GTT,
 					       gtt_flags,
 					       AMDGPU_VM_MTYPE_UC,
-- 
2.43.0

[PATCH v3 15/19] lib/amdgpu: use a memory fence to serialize write

[Sunil Khatri]

Use a memory fence to serialize all the writes in the
queue before updating wptr and ringing the doorbell

This ensures memory is written in same sequence as
intended to.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 lib/amdgpu/amd_user_queue.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c
index d1763f5d6..0235b07ac 100644
--- a/lib/amdgpu/amd_user_queue.c
+++ b/lib/amdgpu/amd_user_queue.c
@@ -148,8 +148,17 @@ void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_co
 	/* empty dword is needed for fence signal pm4 */
 	amdgpu_pkt_add_dw(0);
 
+#if DETECT_CC_GCC && (DETECT_ARCH_X86 || DETECT_ARCH_X86_64)
+	asm volatile ("mfence" : : : "memory");
+#endif
+
+	/* Below call update the wptr address so will wait till all writes are completed */
 	amdgpu_pkt_end();
 
+#if DETECT_CC_GCC && (DETECT_ARCH_X86 || DETECT_ARCH_X86_64)
+	asm volatile ("mfence" : : : "memory");
+#endif
+
 	/* Update the door bell */
 	ring_context->doorbell_cpu[DOORBELL_INDEX] = *ring_context->wptr_cpu;
 
-- 
2.43.0

[PATCH v3 16/19] tests/amdgpu: disable check for IP presense with no kernel queue

[Sunil Khatri]

With kernel queues disabled num_rings will be reported zero.
Enforce the condition to be always true till the time
we have IOCTL to read this information from kernel.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 tests/amdgpu/amd_basic.c  | 2 ++
 tests/amdgpu/amd_cs_nop.c | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/tests/amdgpu/amd_basic.c b/tests/amdgpu/amd_basic.c
index 643a147f5..f8886fab8 100644
--- a/tests/amdgpu/amd_basic.c
+++ b/tests/amdgpu/amd_basic.c
@@ -788,6 +788,8 @@ igt_main
 		}
 	}
 
+	arr_cap[AMD_IP_GFX] = 1;
+	arr_cap[AMD_IP_COMPUTE] = 1;
 	igt_describe("Check-GFX-CS-for-every-available-ring-works-for-write-const-fill-and-copy-operation-using-more-than-one-IB-and-shared-IB");
 	igt_subtest_with_dynamic("cs-gfx-with-IP-GFX-UMQ") {
 		if (arr_cap[AMD_IP_GFX]) {
diff --git a/tests/amdgpu/amd_cs_nop.c b/tests/amdgpu/amd_cs_nop.c
index 96a15a029..0b7c29421 100644
--- a/tests/amdgpu/amd_cs_nop.c
+++ b/tests/amdgpu/amd_cs_nop.c
@@ -185,7 +185,7 @@ igt_main
 		for (e = engines; e->name; e++) {
 			igt_describe("Stressful-and-multiple-cs-of-nop-operations-using-multiple-processes-with-the-same-GPU-context");
 			igt_subtest_with_dynamic_f("cs-nops-with-%s-%s0", p->name, e->name) {
-				if (arr_cap[e->ip_type]) {
+				if (!arr_cap[e->ip_type]) {
 					igt_dynamic_f("cs-nop-with-%s-%s0", p->name, e->name)
 					nop_cs(device, context, e->name, e->ip_type, 0, 20,
 					       p->flags, 0);
@@ -194,6 +194,8 @@ igt_main
 		}
 	}
 
+	arr_cap[AMDGPU_HW_IP_GFX] = 1;
+	arr_cap[AMDGPU_HW_IP_COMPUTE] = 1;
 	for (p = phase; p->name; p++) {
 		for (e = engines; e->name; e++) {
 			igt_describe("Stressful-and-multiple-cs-of-nop-operations-using-multiple-processes-with-the-same-GPU-context-UMQ");
-- 
2.43.0

[PATCH v3 17/19] lib/amdgpu: make the local functions as static

[Sunil Khatri]

functions like amdgpu_alloc_doorbell and
amdgpu_bo_unmap_and_free_uq are internal function
only hence making then static and removing from
amd_user_queue.h

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 lib/amdgpu/amd_user_queue.c | 15 +++++++++------
 lib/amdgpu/amd_user_queue.h |  8 --------
 2 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c
index 0235b07ac..5812a1be3 100644
--- a/lib/amdgpu/amd_user_queue.c
+++ b/lib/amdgpu/amd_user_queue.c
@@ -8,8 +8,9 @@
 #include "amd_PM4.h"
 #include "ioctl_wrappers.h"
 
-void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle, struct amdgpu_userq_bo *doorbell_bo,
-			   unsigned int size, unsigned int domain)
+static void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle,
+				  struct amdgpu_userq_bo *doorbell_bo,
+				  unsigned int size, unsigned int domain)
 {
 	struct amdgpu_bo_alloc_request req = {0};
 	amdgpu_bo_handle buf_handle;
@@ -88,10 +89,12 @@ error_va_alloc:
 	return r;
 }
 
-void amdgpu_bo_unmap_and_free_uq(amdgpu_device_handle device_handle, amdgpu_bo_handle bo,
-			    amdgpu_va_handle va_handle, uint64_t mc_addr, uint64_t size,
-			    uint32_t timeline_syncobj_handle, uint64_t point,
-			    uint64_t syncobj_handles_array, uint32_t num_syncobj_handles)
+static void amdgpu_bo_unmap_and_free_uq(amdgpu_device_handle device_handle,
+					amdgpu_bo_handle bo, amdgpu_va_handle va_handle,
+					uint64_t mc_addr, uint64_t size,
+					uint32_t timeline_syncobj_handle,
+					uint64_t point, uint64_t syncobj_handles_array,
+					uint32_t num_syncobj_handles)
 {
 	amdgpu_bo_cpu_unmap(bo);
 	amdgpu_bo_va_op_raw2(device_handle, bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP,
diff --git a/lib/amdgpu/amd_user_queue.h b/lib/amdgpu/amd_user_queue.h
index 539a78819..b29e97ccf 100644
--- a/lib/amdgpu/amd_user_queue.h
+++ b/lib/amdgpu/amd_user_queue.h
@@ -34,20 +34,12 @@
 #define amdgpu_pkt_end() \
 	*ring_context->wptr_cpu += __num_dw_written
 
-void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle, struct amdgpu_userq_bo *doorbell_bo,
-			   unsigned int size, unsigned int domain);
-
 int amdgpu_bo_alloc_and_map_uq(amdgpu_device_handle device_handle, unsigned int size,
 			       unsigned int alignment, unsigned int heap, uint64_t alloc_flags,
 			       uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
 			       uint64_t *mc_address, amdgpu_va_handle *va_handle,
 			       uint32_t timeline_syncobj_handle, uint64_t point);
 
-void amdgpu_bo_unmap_and_free_uq(amdgpu_device_handle device_handle, amdgpu_bo_handle bo,
-				 amdgpu_va_handle va_handle, uint64_t mc_addr, uint64_t size,
-				 uint32_t timeline_syncobj_handle, uint64_t point,
-				 uint64_t syncobj_handles_array, uint32_t num_syncobj_handles);
-
 int amdgpu_timeline_syncobj_wait(amdgpu_device_handle device_handle,
 				 uint32_t timeline_syncobj_handle, uint64_t point);
 
-- 
2.43.0

[PATCH v3 18/19] lib/amdgpu: enable UMQ function under macro

[Sunil Khatri]

Till the firmware and libdrm code is upstreamed
we disable the Usermode queue code by default
under a macro.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 lib/amdgpu/amd_user_queue.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c
index 5812a1be3..361f5acc6 100644
--- a/lib/amdgpu/amd_user_queue.c
+++ b/lib/amdgpu/amd_user_queue.c
@@ -8,6 +8,7 @@
 #include "amd_PM4.h"
 #include "ioctl_wrappers.h"
 
+#ifdef AMDGPU_USERQ_ENABLED
 static void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle,
 				  struct amdgpu_userq_bo *doorbell_bo,
 				  unsigned int size, unsigned int domain)
@@ -429,3 +430,36 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
 
 	}
 }
+#else
+int
+amdgpu_bo_alloc_and_map_uq(amdgpu_device_handle device_handle, unsigned int size,
+			   unsigned int alignment, unsigned int heap, uint64_t alloc_flags,
+			   uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
+			   uint64_t *mc_address, amdgpu_va_handle *va_handle,
+			   uint32_t timeline_syncobj_handle, uint64_t point)
+{
+	return 0;
+}
+
+int amdgpu_timeline_syncobj_wait(amdgpu_device_handle device_handle,
+	uint32_t timeline_syncobj_handle, uint64_t point)
+{
+	return 0;
+}
+
+void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_context *ring_context,
+	unsigned int ip_type, uint64_t mc_address)
+{
+}
+
+void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
+	unsigned int type)
+{
+}
+
+void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
+	unsigned int type)
+{
+}
+
+#endif
-- 
2.43.0

[PATCH v3 19/19] tests/amdgpu: Disable the UMQ tests under a macro

[Sunil Khatri]

disable the umq tests under a macro till we have all
dependencies resolved.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 tests/amdgpu/amd_basic.c  | 3 +++
 tests/amdgpu/amd_cs_nop.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/tests/amdgpu/amd_basic.c b/tests/amdgpu/amd_basic.c
index f8886fab8..eb8447220 100644
--- a/tests/amdgpu/amd_basic.c
+++ b/tests/amdgpu/amd_basic.c
@@ -788,8 +788,10 @@ igt_main
 		}
 	}
 
+#ifdef AMDGPU_USERQ_ENABLED
 	arr_cap[AMD_IP_GFX] = 1;
 	arr_cap[AMD_IP_COMPUTE] = 1;
+
 	igt_describe("Check-GFX-CS-for-every-available-ring-works-for-write-const-fill-and-copy-operation-using-more-than-one-IB-and-shared-IB");
 	igt_subtest_with_dynamic("cs-gfx-with-IP-GFX-UMQ") {
 		if (arr_cap[AMD_IP_GFX]) {
@@ -813,6 +815,7 @@ igt_main
 			amdgpu_sync_dependency_test(device, true);
 		}
 	}
+#endif
 
 	igt_fixture {
 		amdgpu_device_deinitialize(device);
diff --git a/tests/amdgpu/amd_cs_nop.c b/tests/amdgpu/amd_cs_nop.c
index 0b7c29421..c71a2b63d 100644
--- a/tests/amdgpu/amd_cs_nop.c
+++ b/tests/amdgpu/amd_cs_nop.c
@@ -194,8 +194,10 @@ igt_main
 		}
 	}
 
+#ifdef AMDGPU_USERQ_ENABLED
 	arr_cap[AMDGPU_HW_IP_GFX] = 1;
 	arr_cap[AMDGPU_HW_IP_COMPUTE] = 1;
+
 	for (p = phase; p->name; p++) {
 		for (e = engines; e->name; e++) {
 			igt_describe("Stressful-and-multiple-cs-of-nop-operations-using-multiple-processes-with-the-same-GPU-context-UMQ");
@@ -208,6 +210,7 @@ igt_main
 			}
 		}
 	}
+#endif
 
 	igt_fixture {
 		amdgpu_cs_ctx_free(context);
-- 
2.43.0

✓ Xe.CI.BAT: success for series starting with [v3,01/19] drm-uapi/amdgpu: sync with drm-next

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1091 bytes --]

== Series Details ==

Series: series starting with [v3,01/19] drm-uapi/amdgpu: sync with drm-next
URL   : https://patchwork.freedesktop.org/series/146929/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8291_BAT -> XEIGTPW_12872_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8291 -> IGTPW_12872
  * Linux: xe-2863-274d97eed4e8376b7a66b8904066baed6a1ae874 -> xe-2868-c66e1b5495eda37a602bf54a9f4f34d476d2f3d7

  IGTPW_12872: 12872
  IGT_8291: a1809bc9d786d9b37a22e3e5e4810c6a0c84480b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-2863-274d97eed4e8376b7a66b8904066baed6a1ae874: 274d97eed4e8376b7a66b8904066baed6a1ae874
  xe-2868-c66e1b5495eda37a602bf54a9f4f34d476d2f3d7: c66e1b5495eda37a602bf54a9f4f34d476d2f3d7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/index.html

[-- Attachment #2: Type: text/html, Size: 1650 bytes --]

✗ i915.CI.BAT: failure for series starting with [v3,01/19] drm-uapi/amdgpu: sync with drm-next

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9402 bytes --]

== Series Details ==

Series: series starting with [v3,01/19] drm-uapi/amdgpu: sync with drm-next
URL   : https://patchwork.freedesktop.org/series/146929/
State : failure

== Summary ==

CI Bug Log - changes from IGT_8291 -> IGTPW_12872
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_12872 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_12872, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/index.html

Participating hosts (40 -> 42)
------------------------------

  Additional (3): fi-glk-j4005 bat-atsm-1 fi-skl-6600u 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_12872:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@requests:
    - bat-atsm-1:         NOTRUN -> [INCOMPLETE][1] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@i915_selftest@live@requests.html

  
New tests
---------

  New tests have been introduced between IGT_8291 and IGTPW_12872:

### New IGT tests (4) ###

  * igt@i915_selftest@basic-await:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_selftest@basic-busy:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_selftest@basic-wait:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_selftest@nb-await:
    - Statuses :
    - Exec time: [None] s

  

Known issues
------------

  Here are the changes found in IGTPW_12872 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@info:
    - bat-atsm-1:         NOTRUN -> [SKIP][2] ([i915#1849] / [i915#2582])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@fbdev@info.html

  * igt@fbdev@read:
    - bat-atsm-1:         NOTRUN -> [SKIP][3] ([i915#2582]) +3 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@fbdev@read.html

  * igt@gem_huc_copy@huc-copy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
    - fi-glk-j4005:       NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/fi-glk-j4005/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-glk-j4005:       NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/fi-glk-j4005/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-skl-6600u:       NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-cfl-guc:         NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/fi-cfl-guc/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][9] ([i915#4083])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@gem_mmap@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][10] ([i915#4079]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][11] ([i915#4077]) +4 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@gem_tiled_fence_blits@basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-atsm-1:         NOTRUN -> [SKIP][12] ([i915#6621])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@workarounds:
    - bat-atsm-1:         NOTRUN -> [DMESG-FAIL][13] ([i915#12061])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@size-max:
    - bat-atsm-1:         NOTRUN -> [SKIP][14] ([i915#6077]) +37 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@kms_addfb_basic@size-max.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - bat-atsm-1:         NOTRUN -> [SKIP][15] ([i915#6078]) +22 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
    - fi-skl-6600u:       NOTRUN -> [SKIP][16] +9 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/fi-skl-6600u/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-atsm-1:         NOTRUN -> [SKIP][17] ([i915#6093]) +4 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence:
    - bat-atsm-1:         NOTRUN -> [SKIP][18] ([i915#1836]) +6 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html

  * igt@kms_prop_blob@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][19] ([i915#7357])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@kms_prop_blob@basic.html

  * igt@kms_psr@psr-primary-page-flip:
    - fi-glk-j4005:       NOTRUN -> [SKIP][20] +10 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/fi-glk-j4005/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-atsm-1:         NOTRUN -> [SKIP][21] ([i915#6094])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-write:
    - bat-atsm-1:         NOTRUN -> [SKIP][22] +2 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-atsm-1/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-cfl-guc:         [ABORT][23] ([i915#13571]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8291/fi-cfl-guc/igt@i915_module_load@reload.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/fi-cfl-guc/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@module-reload:
    - bat-adlp-6:         [DMESG-WARN][25] ([i915#13890]) -> [PASS][26] +78 other tests pass
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8291/bat-adlp-6/igt@i915_pm_rpm@module-reload.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-adlp-6/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-6:         [DMESG-FAIL][27] ([i915#12061]) -> [PASS][28] +1 other test pass
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8291/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/bat-mtlp-6/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13571]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13571
  [i915#13890]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13890
  [i915#1836]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1836
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#6077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6077
  [i915#6078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6078
  [i915#6093]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6093
  [i915#6094]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6094
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#7357]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7357


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8291 -> IGTPW_12872
  * Linux: CI_DRM_16330 -> CI_DRM_16335

  CI-20190529: 20190529
  CI_DRM_16330: 274d97eed4e8376b7a66b8904066baed6a1ae874 @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_16335: c66e1b5495eda37a602bf54a9f4f34d476d2f3d7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_12872: 12872
  IGT_8291: a1809bc9d786d9b37a22e3e5e4810c6a0c84480b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12872/index.html

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✗ Xe.CI.Full: failure for series starting with [v3,01/19] drm-uapi/amdgpu: sync with drm-next

[Patchwork]

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== Series Details ==

Series: series starting with [v3,01/19] drm-uapi/amdgpu: sync with drm-next
URL   : https://patchwork.freedesktop.org/series/146929/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8291_FULL -> XEIGTPW_12872_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_12872_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_12872_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_12872_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-lnl:          [PASS][1] -> [SKIP][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@xe_compute_preempt@compute-preempt-many:
    - shard-bmg:          [PASS][3] -> [FAIL][4] +2 other tests fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-7/igt@xe_compute_preempt@compute-preempt-many.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@xe_compute_preempt@compute-preempt-many.html

  
#### Warnings ####

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          [SKIP][5] ([Intel XE#4596]) -> [SKIP][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-y.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_plane_multiple@2x-tiling-y.html

  
Known issues
------------

  Here are the changes found in XEIGTPW_12872_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2233])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_async_flips@async-flip-with-page-flip-events:
    - shard-adlp:         [PASS][8] -> [DMESG-WARN][9] ([Intel XE#4543]) +3 other tests dmesg-warn
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-2/igt@kms_async_flips@async-flip-with-page-flip-events.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@kms_async_flips@async-flip-with-page-flip-events.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2327]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-adlp:         NOTRUN -> [SKIP][11] ([Intel XE#316]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-2/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#1407]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#316]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#1124]) +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#1428])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-5/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#1124]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#1124]) +6 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#607])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-adlp:         NOTRUN -> [SKIP][19] ([Intel XE#1124])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-bmg:          [PASS][20] -> [SKIP][21] ([Intel XE#2314] / [Intel XE#2894])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
    - shard-adlp:         NOTRUN -> [SKIP][22] ([Intel XE#2191])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#1512])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-4/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#2907]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][25] ([Intel XE#455] / [Intel XE#787]) +5 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-8/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2887]) +8 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_ccs@crc-primary-basic-y-tiled-ccs.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-hdmi-a-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#787]) +153 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#455] / [Intel XE#787]) +27 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#3432])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][31] ([Intel XE#787]) +8 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-2/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [PASS][32] -> [INCOMPLETE][33] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][34] -> [INCOMPLETE][35] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][36] -> [INCOMPLETE][37] ([Intel XE#1727] / [Intel XE#3113]) +1 other test incomplete
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-2:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][38] ([Intel XE#3113])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#2887]) +6 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-2/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][40] ([Intel XE#4416]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_cdclk@plane-scaling@pipe-b-dp-2.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-adlp:         NOTRUN -> [SKIP][41] ([Intel XE#306])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-4/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2325]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_chamelium_color@ctm-0-50.html
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#306]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-dg2-set2:     NOTRUN -> [SKIP][44] ([Intel XE#306])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2252]) +5 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#373]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-2/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-adlp:         NOTRUN -> [SKIP][47] ([Intel XE#373]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-4/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#373])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_content_protection@uevent:
    - shard-dg2-set2:     NOTRUN -> [FAIL][49] ([Intel XE#1188]) +1 other test fail
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_content_protection@uevent.html
    - shard-bmg:          NOTRUN -> [FAIL][50] ([Intel XE#1188]) +1 other test fail
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2320]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#1424]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2321]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#2321])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-3/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
    - shard-adlp:         [PASS][55] -> [DMESG-WARN][56] ([Intel XE#4173]) +3 other tests dmesg-warn
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-1/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-adlp:         NOTRUN -> [SKIP][57] ([Intel XE#323])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-bmg:          [PASS][58] -> [SKIP][59] ([Intel XE#2291]) +2 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-7/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-adlp:         NOTRUN -> [SKIP][60] ([Intel XE#309]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#309]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-4/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-dg2-set2:     [PASS][62] -> [SKIP][63] ([Intel XE#309]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-435/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#323])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#323]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#2286])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-bmg:          [PASS][67] -> [SKIP][68] ([Intel XE#4302])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_display_modes@extended-mode-basic.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_display_modes@extended-mode-basic.html
    - shard-dg2-set2:     [PASS][69] -> [SKIP][70] ([Intel XE#4302])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_display_modes@extended-mode-basic.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-bmg:          [PASS][71] -> [SKIP][72] ([Intel XE#4354])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-2/igt@kms_dp_link_training@non-uhbr-sst.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#2244]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#2244])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#4156])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#776])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@psr2:
    - shard-adlp:         NOTRUN -> [SKIP][77] ([Intel XE#1135])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-4/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank:
    - shard-dg2-set2:     [PASS][78] -> [SKIP][79] ([Intel XE#310]) +2 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_flip@2x-blocking-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3:
    - shard-bmg:          [PASS][80] -> [FAIL][81] ([Intel XE#3321])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][82] -> [FAIL][83] ([Intel XE#301]) +2 other tests fail
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-435/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a6-dp4.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a6-dp4.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-adlp:         NOTRUN -> [SKIP][84] ([Intel XE#310]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-4/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
    - shard-bmg:          [PASS][85] -> [SKIP][86] ([Intel XE#2316]) +3 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-bmg:          [PASS][87] -> [INCOMPLETE][88] ([Intel XE#2049])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@d-hdmi-a6:
    - shard-dg2-set2:     [PASS][89] -> [INCOMPLETE][90] ([Intel XE#2049]) +1 other test incomplete
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-466/igt@kms_flip@flip-vs-blocking-wf-vblank@d-hdmi-a6.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_flip@flip-vs-blocking-wf-vblank@d-hdmi-a6.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][91] -> [FAIL][92] ([Intel XE#301])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][93] -> [FAIL][94] ([Intel XE#301] / [Intel XE#3149])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate@a-edp1:
    - shard-lnl:          [PASS][95] -> [FAIL][96] ([Intel XE#886]) +2 other tests fail
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-2/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling:
    - shard-adlp:         [PASS][97] -> [DMESG-FAIL][98] ([Intel XE#324] / [Intel XE#4543]) +3 other tests dmesg-fail
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][99] ([Intel XE#2293] / [Intel XE#2380]) +2 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#1401]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][102] ([Intel XE#455]) +4 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][103] ([Intel XE#2293]) +2 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y:
    - shard-adlp:         [PASS][104] -> [FAIL][105] ([Intel XE#1874])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][106] ([Intel XE#2311]) +14 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][107] ([Intel XE#651]) +5 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-adlp:         NOTRUN -> [SKIP][108] ([Intel XE#656]) +10 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][109] ([Intel XE#651]) +6 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
    - shard-adlp:         [PASS][110] -> [DMESG-FAIL][111] ([Intel XE#4543]) +9 other tests dmesg-fail
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [PASS][112] -> [SKIP][113] ([Intel XE#656]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#4141]) +7 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][115] ([Intel XE#2312]) +6 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#656]) +17 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-suspend:
    - shard-adlp:         NOTRUN -> [SKIP][117] ([Intel XE#651]) +2 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][118] ([Intel XE#653]) +6 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][119] ([Intel XE#2313]) +13 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][120] ([Intel XE#653]) +3 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][121] ([Intel XE#656])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-bmg:          [PASS][122] -> [SKIP][123] ([Intel XE#1503])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-1/igt@kms_hdr@invalid-metadata-sizes.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [ABORT][124] ([Intel XE#4502] / [Intel XE#4540])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
    - shard-bmg:          NOTRUN -> [SKIP][125] ([Intel XE#2763]) +4 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c:
    - shard-lnl:          NOTRUN -> [SKIP][126] ([Intel XE#2763]) +11 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2-set2:     NOTRUN -> [SKIP][127] ([Intel XE#3309])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][128] ([Intel XE#908])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg2-set2:     [PASS][129] -> [SKIP][130] ([Intel XE#836])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-436/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-adlp:         NOTRUN -> [SKIP][131] ([Intel XE#1489])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-8/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [FAIL][132] ([Intel XE#4570]) +5 other tests fail
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][133] ([Intel XE#1489]) +4 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][134] ([Intel XE#1489]) +3 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][135] ([Intel XE#2893])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-bmg:          NOTRUN -> [SKIP][136] ([Intel XE#2387])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-sprite-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][137] ([Intel XE#1406])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-3/igt@kms_psr@fbc-pr-sprite-plane-onoff.html

  * igt@kms_psr@fbc-psr-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][138] ([Intel XE#2234] / [Intel XE#2850]) +6 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_psr@fbc-psr-primary-render.html

  * igt@kms_psr@fbc-psr2-cursor-plane-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][139] ([Intel XE#2850] / [Intel XE#929]) +4 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_psr@fbc-psr2-cursor-plane-onoff.html

  * igt@kms_psr@fbc-psr2-sprite-blt:
    - shard-adlp:         NOTRUN -> [SKIP][140] ([Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-4/igt@kms_psr@fbc-psr2-sprite-blt.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-adlp:         NOTRUN -> [SKIP][141] ([Intel XE#3414])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
    - shard-lnl:          NOTRUN -> [SKIP][142] ([Intel XE#3414] / [Intel XE#3904])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][143] ([Intel XE#1435])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-dg2-set2:     [PASS][144] -> [SKIP][145] ([Intel XE#455])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_setmode@invalid-clone-single-crtc.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-adlp:         NOTRUN -> [SKIP][146] ([Intel XE#362])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-lnl:          NOTRUN -> [SKIP][147] ([Intel XE#330])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_tv_load_detect@load-detect.html
    - shard-bmg:          NOTRUN -> [SKIP][148] ([Intel XE#2450])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_tv_load_detect@load-detect.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-dg2-set2:     NOTRUN -> [SKIP][149] ([Intel XE#1091] / [Intel XE#2849])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@xe_compute_preempt@compute-preempt-many:
    - shard-adlp:         NOTRUN -> [SKIP][150] ([Intel XE#455]) +3 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-8/igt@xe_compute_preempt@compute-preempt-many.html

  * igt@xe_eudebug@basic-vm-bind-metadata-discovery:
    - shard-adlp:         NOTRUN -> [SKIP][151] ([Intel XE#2905]) +2 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-8/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html

  * igt@xe_eudebug@basic-vm-bind-ufence:
    - shard-bmg:          NOTRUN -> [SKIP][152] ([Intel XE#2905]) +6 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@xe_eudebug@basic-vm-bind-ufence.html

  * igt@xe_eudebug@basic-vm-bind-ufence-reconnect:
    - shard-bmg:          NOTRUN -> [SKIP][153] ([Intel XE#2905] / [Intel XE#3889]) +1 other test skip
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@xe_eudebug@basic-vm-bind-ufence-reconnect.html
    - shard-lnl:          NOTRUN -> [SKIP][154] ([Intel XE#2905] / [Intel XE#3889]) +1 other test skip
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@xe_eudebug@basic-vm-bind-ufence-reconnect.html

  * igt@xe_eudebug@multigpu-basic-client-many:
    - shard-dg2-set2:     NOTRUN -> [SKIP][155] ([Intel XE#2905]) +2 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@xe_eudebug@multigpu-basic-client-many.html

  * igt@xe_eudebug_online@preempt-breakpoint:
    - shard-lnl:          NOTRUN -> [SKIP][156] ([Intel XE#2905]) +2 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-4/igt@xe_eudebug_online@preempt-breakpoint.html

  * igt@xe_eudebug_sriov@deny-sriov:
    - shard-bmg:          NOTRUN -> [SKIP][157] ([Intel XE#4518])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@xe_eudebug_sriov@deny-sriov.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][158] ([Intel XE#4518])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@xe_eudebug_sriov@deny-sriov.html

  * igt@xe_evict@evict-beng-small-external:
    - shard-lnl:          NOTRUN -> [SKIP][159] ([Intel XE#688])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-2/igt@xe_evict@evict-beng-small-external.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate-race:
    - shard-adlp:         NOTRUN -> [SKIP][160] ([Intel XE#1392]) +1 other test skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-4/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][161] ([Intel XE#1392]) +3 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-1/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
    - shard-dg2-set2:     [PASS][162] -> [SKIP][163] ([Intel XE#1392]) +5 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][164] ([Intel XE#2322]) +5 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate:
    - shard-dg2-set2:     NOTRUN -> [SKIP][165] ([Intel XE#288]) +8 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate.html

  * igt@xe_exec_fault_mode@once-userptr-invalidate:
    - shard-adlp:         NOTRUN -> [SKIP][166] ([Intel XE#288]) +8 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@xe_exec_fault_mode@once-userptr-invalidate.html

  * igt@xe_exec_reset@cm-cat-error:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][167] ([Intel XE#3868])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@xe_exec_reset@cm-cat-error.html

  * igt@xe_oa@non-privileged-map-oa-buffer:
    - shard-dg2-set2:     NOTRUN -> [SKIP][168] ([Intel XE#2541] / [Intel XE#3573])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@xe_oa@non-privileged-map-oa-buffer.html

  * igt@xe_oa@syncs-syncobj-wait:
    - shard-adlp:         NOTRUN -> [SKIP][169] ([Intel XE#2541] / [Intel XE#3573] / [Intel XE#4501])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-8/igt@xe_oa@syncs-syncobj-wait.html

  * igt@xe_pat@pat-index-xe2:
    - shard-adlp:         NOTRUN -> [SKIP][170] ([Intel XE#977])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@xe_pat@pat-index-xe2.html

  * igt@xe_peer2peer@write:
    - shard-bmg:          NOTRUN -> [SKIP][171] ([Intel XE#2427])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@xe_peer2peer@write.html

  * igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p:
    - shard-dg2-set2:     NOTRUN -> [FAIL][172] ([Intel XE#1173]) +1 other test fail
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-bmg:          NOTRUN -> [SKIP][173] ([Intel XE#2284])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@xe_pm@d3cold-multiple-execs.html
    - shard-lnl:          NOTRUN -> [SKIP][174] ([Intel XE#2284] / [Intel XE#366])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-4/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_pm@d3hot-mmap-system:
    - shard-bmg:          [PASS][175] -> [FAIL][176] ([Intel XE#3290])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@xe_pm@d3hot-mmap-system.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@xe_pm@d3hot-mmap-system.html

  * igt@xe_pm@s4-basic:
    - shard-adlp:         [PASS][177] -> [ABORT][178] ([Intel XE#1794])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-2/igt@xe_pm@s4-basic.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-9/igt@xe_pm@s4-basic.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-lnl:          NOTRUN -> [SKIP][179] ([Intel XE#579])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@xe_pm@vram-d3cold-threshold.html
    - shard-bmg:          NOTRUN -> [SKIP][180] ([Intel XE#579])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-adlp:         NOTRUN -> [SKIP][181] ([Intel XE#944])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-4/igt@xe_query@multigpu-query-hwconfig.html
    - shard-lnl:          NOTRUN -> [SKIP][182] ([Intel XE#944])
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-2/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_query@multigpu-query-topology:
    - shard-bmg:          NOTRUN -> [SKIP][183] ([Intel XE#944])
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@xe_query@multigpu-query-topology.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][184] ([Intel XE#944]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_sriov_scheduling@equal-throughput:
    - shard-bmg:          NOTRUN -> [SKIP][185] ([Intel XE#4351])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@xe_sriov_scheduling@equal-throughput.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic:
    - shard-lnl:          [FAIL][186] ([Intel XE#3719] / [Intel XE#911]) -> [PASS][187] +3 other tests pass
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-4/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear:
    - shard-lnl:          [FAIL][188] ([Intel XE#911]) -> [PASS][189] +3 other tests pass
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html

  * igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1:
    - shard-adlp:         [FAIL][190] ([Intel XE#3884]) -> [PASS][191] +1 other test pass
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-6/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-adlp:         [DMESG-FAIL][192] ([Intel XE#4543]) -> [PASS][193] +5 other tests pass
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [SKIP][194] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][195]
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-bmg:          [SKIP][196] ([Intel XE#2291]) -> [PASS][197] +1 other test pass
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-dg2-set2:     [SKIP][198] ([Intel XE#309]) -> [PASS][199] +3 other tests pass
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_dp_aux_dev:
    - shard-dg2-set2:     [SKIP][200] ([Intel XE#3009]) -> [PASS][201]
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_dp_aux_dev.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_dp_aux_dev.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-dg2-set2:     [SKIP][202] ([Intel XE#4354]) -> [PASS][203]
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_dp_link_training@non-uhbr-sst.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible:
    - shard-dg2-set2:     [SKIP][204] ([Intel XE#310]) -> [PASS][205] +5 other tests pass
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-hdmi-a6-dp4:
    - shard-dg2-set2:     [FAIL][206] ([Intel XE#301]) -> [PASS][207] +1 other test pass
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-435/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-hdmi-a6-dp4.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][208] ([Intel XE#3321]) -> [PASS][209] +1 other test pass
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-bmg:          [SKIP][210] ([Intel XE#2316]) -> [PASS][211] +7 other tests pass
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][212] ([Intel XE#301]) -> [PASS][213] +3 other tests pass
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode:
    - shard-adlp:         [DMESG-FAIL][214] ([Intel XE#324] / [Intel XE#4543]) -> [PASS][215] +1 other test pass
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [SKIP][216] ([Intel XE#656]) -> [PASS][217] +7 other tests pass
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_plane_cursor@viewport:
    - shard-adlp:         [FAIL][218] ([Intel XE#1471]) -> [PASS][219] +1 other test pass
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-8/igt@kms_plane_cursor@viewport.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-4/igt@kms_plane_cursor@viewport.html
    - shard-dg2-set2:     [FAIL][220] ([Intel XE#616]) -> [PASS][221]
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@kms_plane_cursor@viewport.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_plane_cursor@viewport.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-dg2-set2:     [SKIP][222] ([Intel XE#4596]) -> [PASS][223]
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_plane_multiple@2x-tiling-4.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-bmg:          [SKIP][224] ([Intel XE#4596]) -> [PASS][225] +1 other test pass
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-x.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-dg2-set2:     [SKIP][226] ([Intel XE#836]) -> [PASS][227]
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-dg2-set2:     [INCOMPLETE][228] -> [PASS][229]
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-dg2-set2:     [SKIP][230] ([Intel XE#455]) -> [PASS][231] +1 other test pass
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@xe_exec_basic@multigpu-once-rebind:
    - shard-dg2-set2:     [SKIP][232] ([Intel XE#1392]) -> [PASS][233] +6 other tests pass
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@xe_exec_basic@multigpu-once-rebind.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@xe_exec_basic@multigpu-once-rebind.html

  * igt@xe_exec_threads@threads-bal-mixed-userptr-invalidate:
    - shard-bmg:          [INCOMPLETE][234] -> [PASS][235]
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-7/igt@xe_exec_threads@threads-bal-mixed-userptr-invalidate.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@xe_exec_threads@threads-bal-mixed-userptr-invalidate.html

  * igt@xe_oa@buffer-size:
    - shard-lnl:          [FAIL][236] ([Intel XE#4541]) -> [PASS][237]
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-2/igt@xe_oa@buffer-size.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@xe_oa@buffer-size.html

  * igt@xe_pm@s4-basic-exec:
    - shard-adlp:         [ABORT][238] ([Intel XE#1794]) -> [PASS][239] +1 other test pass
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-9/igt@xe_pm@s4-basic-exec.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@xe_pm@s4-basic-exec.html
    - shard-lnl:          [ABORT][240] ([Intel XE#1794]) -> [PASS][241]
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-2/igt@xe_pm@s4-basic-exec.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-1/igt@xe_pm@s4-basic-exec.html

  * igt@xe_wedged@basic-wedged:
    - shard-adlp:         [DMESG-WARN][242] ([Intel XE#4173]) -> [PASS][243] +7 other tests pass
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-2/igt@xe_wedged@basic-wedged.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-8/igt@xe_wedged@basic-wedged.html

  
#### Warnings ####

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][244] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][245] ([Intel XE#787]) +6 other tests skip
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [DMESG-WARN][246] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212]) -> [INCOMPLETE][247] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345])
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][248] ([Intel XE#787]) -> [SKIP][249] ([Intel XE#455] / [Intel XE#787]) +3 other tests skip
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-436/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][250] ([Intel XE#301]) -> [FAIL][251] ([Intel XE#301] / [Intel XE#3149])
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][252] ([Intel XE#2312]) -> [SKIP][253] ([Intel XE#2311]) +15 other tests skip
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     [SKIP][254] ([Intel XE#651]) -> [SKIP][255] ([Intel XE#656]) +3 other tests skip
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][256] ([Intel XE#4141]) -> [SKIP][257] ([Intel XE#2312]) +5 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][258] ([Intel XE#2312]) -> [SKIP][259] ([Intel XE#4141]) +9 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][260] ([Intel XE#2311]) -> [SKIP][261] ([Intel XE#2312]) +11 other tests skip
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][262] ([Intel XE#656]) -> [SKIP][263] ([Intel XE#651]) +10 other tests skip
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
    - shard-dg2-set2:     [SKIP][264] ([Intel XE#653]) -> [SKIP][265] ([Intel XE#656]) +5 other tests skip
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render:
    - shard-dg2-set2:     [SKIP][266] ([Intel XE#656]) -> [SKIP][267] ([Intel XE#653]) +7 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][268] ([Intel XE#2313]) -> [SKIP][269] ([Intel XE#2312]) +11 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][270] ([Intel XE#2312]) -> [SKIP][271] ([Intel XE#2313]) +13 other tests skip
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          [SKIP][272] -> [SKIP][273] ([Intel XE#4596])
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-yf.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2-set2:     [ABORT][274] ([Intel XE#4540]) -> [ABORT][275] ([Intel XE#2705] / [Intel XE#4540])
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@kms_plane_scaling@intel-max-src-size.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-lnl:          [FAIL][276] ([Intel XE#4568]) -> [FAIL][277] ([Intel XE#3924]) +1 other test fail
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-4/igt@kms_psr@fbc-psr2-primary-render.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_psr@fbc-psr2-primary-render.html

  
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1471]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1471
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
  [Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
  [Intel XE#3290]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3290
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#3719]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3719
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
  [Intel XE#3889]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3889
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#3924]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3924
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4501
  [Intel XE#4502]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4502
  [Intel XE#4518]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4518
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4540
  [Intel XE#4541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4541
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4568]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4568
  [Intel XE#4570]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4570
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * IGT: IGT_8291 -> IGTPW_12872
  * Linux: xe-2863-274d97eed4e8376b7a66b8904066baed6a1ae874 -> xe-2868-c66e1b5495eda37a602bf54a9f4f34d476d2f3d7

  IGTPW_12872: 12872
  IGT_8291: a1809bc9d786d9b37a22e3e5e4810c6a0c84480b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-2863-274d97eed4e8376b7a66b8904066baed6a1ae874: 274d97eed4e8376b7a66b8904066baed6a1ae874
  xe-2868-c66e1b5495eda37a602bf54a9f4f34d476d2f3d7: c66e1b5495eda37a602bf54a9f4f34d476d2f3d7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/index.html

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Re: [PATCH v3 02/19] drm-uapi/amdgpu: sync with drm-next

[vitaly prosyak]

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On 2025-03-28 04:23, Sunil Khatri wrote:
> Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")
>
> Added support of UAPI for user queue secure semaphore.
> The semaphore is used to synchronize between the caller and
> the gpu hw and user wait for the semaphore.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  include/drm-uapi/amdgpu_drm.h | 117 ++++++++++++++++++++++++++++++++++
>  1 file changed, 117 insertions(+)
>
> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
> index d780e1f2a..fed39c9b4 100644
> --- a/include/drm-uapi/amdgpu_drm.h
> +++ b/include/drm-uapi/amdgpu_drm.h
> @@ -55,6 +55,8 @@ extern "C" {
>  #define DRM_AMDGPU_FENCE_TO_HANDLE	0x14
>  #define DRM_AMDGPU_SCHED		0x15
>  #define DRM_AMDGPU_USERQ		0x16
> +#define DRM_AMDGPU_USERQ_SIGNAL		0x17
> +#define DRM_AMDGPU_USERQ_WAIT		0x18
>  
>  #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>  #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
> @@ -73,6 +75,8 @@ extern "C" {
>  #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
>  #define DRM_IOCTL_AMDGPU_SCHED		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
>  #define DRM_IOCTL_AMDGPU_USERQ		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
> +#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
> +#define DRM_IOCTL_AMDGPU_USERQ_WAIT	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
>  
>  /**
>   * DOC: memory domains
> @@ -442,6 +446,119 @@ struct drm_amdgpu_userq_mqd_compute_gfx11 {
>  	__u64   eop_va;
>  };
>  
> +/* userq signal/wait ioctl */
> +struct drm_amdgpu_userq_signal {
> +	/**
> +	 * @queue_id: Queue handle used by the userq fence creation function
> +	 * to retrieve the WPTR.
> +	 */
> +	__u32	queue_id;
> +	__u32	pad;
> +	/**
> +	 * @syncobj_handles: The list of syncobj handles submitted by the user queue
> +	 * job to be signaled.
> +	 */

I am not sure about the correctness of the 'list of syncobj handles.' If it is a list, the field should be of type |list_head|; if it's an array, it should be |__u64*|, since the next field declares |num_syncobj_handles|. Could you clarify this?

There are several fields like this ?

> +	__u64	syncobj_handles;
> +	/**
> +	 * @num_syncobj_handles: A count that represents the number of syncobj handles in
> +	 * @syncobj_handles.
> +	 */
> +	__u64	num_syncobj_handles;
> +	/**
> +	 * @bo_read_handles: The list of BO handles that the submitted user queue job
> +	 * is using for read only. This will update BO fences in the kernel.
> +	 */
> +	__u64	bo_read_handles;
> +	/**
> +	 * @bo_write_handles: The list of BO handles that the submitted user queue job
> +	 * is using for write only. This will update BO fences in the kernel.
> +	 */
> +	__u64	bo_write_handles;
> +	/**
> +	 * @num_bo_read_handles: A count that represents the number of read BO handles in
> +	 * @bo_read_handles.
> +	 */
> +	__u32	num_bo_read_handles;
> +	/**
> +	 * @num_bo_write_handles: A count that represents the number of write BO handles in
> +	 * @bo_write_handles.
> +	 */
> +	__u32	num_bo_write_handles;
> +};
> +
> +struct drm_amdgpu_userq_fence_info {
> +	/**
> +	 * @va: A gpu address allocated for each queue which stores the
> +	 * read pointer (RPTR) value.
> +	 */
> +	__u64	va;
> +	/**
> +	 * @value: A 64 bit value represents the write pointer (WPTR) of the
> +	 * queue commands which compared with the RPTR value to signal the
> +	 * fences.
> +	 */
> +	__u64	value;
> +};
> +
> +struct drm_amdgpu_userq_wait {
> +	/**
> +	 * @syncobj_handles: The list of syncobj handles submitted by the user queue
> +	 * job to get the va/value pairs.
> +	 */
> +	__u64	syncobj_handles;
> +	/**
> +	 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by
> +	 * the user queue job to get the va/value pairs at given @syncobj_timeline_points.
> +	 */
> +	__u64	syncobj_timeline_handles;
> +	/**
> +	 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the
> +	 * user queue job for the corresponding @syncobj_timeline_handles.
> +	 */
> +	__u64	syncobj_timeline_points;
> +	/**
> +	 * @bo_read_handles: The list of read BO handles submitted by the user queue
> +	 * job to get the va/value pairs.
> +	 */
> +	__u64	bo_read_handles;
> +	/**
> +	 * @bo_write_handles: The list of write BO handles submitted by the user queue
> +	 * job to get the va/value pairs.
> +	 */
> +	__u64	bo_write_handles;
> +	/**
> +	 * @num_syncobj_timeline_handles: A count that represents the number of timeline
> +	 * syncobj handles in @syncobj_timeline_handles.
> +	 */
> +	__u16	num_syncobj_timeline_handles;
> +	/**
> +	 * @num_fences: This field can be used both as input and output. As input it defines
> +	 * the maximum number of fences that can be returned and as output it will specify
> +	 * how many fences were actually returned from the ioctl.
> +	 */
> +	__u16	num_fences;
> +	/**
> +	 * @num_syncobj_handles: A count that represents the number of syncobj handles in
> +	 * @syncobj_handles.
> +	 */
> +	__u32	num_syncobj_handles;
> +	/**
> +	 * @num_bo_read_handles: A count that represents the number of read BO handles in
> +	 * @bo_read_handles.
> +	 */
> +	__u32	num_bo_read_handles;
> +	/**
> +	 * @num_bo_write_handles: A count that represents the number of write BO handles in
> +	 * @bo_write_handles.
> +	 */
> +	__u32	num_bo_write_handles;
> +	/**
> +	 * @out_fences: The field is a return value from the ioctl containing the list of
> +	 * address/value pairs to wait for.
> +	 */
> +	__u64	out_fences;
> +};
> +
>  /* vm ioctl */
>  #define AMDGPU_VM_OP_RESERVE_VMID	1
>  #define AMDGPU_VM_OP_UNRESERVE_VMID	2

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Re: [PATCH v3 04/19] lib/amdgpu: Add support of amd user queues

[vitaly prosyak]

On 2025-03-28 04:24, Sunil Khatri wrote:
> This is the first patch set to add support of
> UMQ(User mode queues) submission in IGT.
>
> UMQ allows users to directly create a user queue and
> submit workload to the GPU h/w to directly instead
> of sending the workload to kernel and then to GPU h/w.
>
> This will be used by test cases which will be testing
> the UMQ queues for gfx/compute and sdma to start with.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  lib/amdgpu/amd_PM4.h        |   3 +
>  lib/amdgpu/amd_ip_blocks.h  |   5 +
>  lib/amdgpu/amd_user_queue.c | 418 ++++++++++++++++++++++++++++++++++++
>  lib/amdgpu/amd_user_queue.h |  48 +++++
>  lib/meson.build             |   3 +-
>  5 files changed, 476 insertions(+), 1 deletion(-)
>  create mode 100644 lib/amdgpu/amd_user_queue.c
>  create mode 100644 lib/amdgpu/amd_user_queue.h
>
> diff --git a/lib/amdgpu/amd_PM4.h b/lib/amdgpu/amd_PM4.h
> index 5bc3cb783..8f59b4223 100644
> --- a/lib/amdgpu/amd_PM4.h
> +++ b/lib/amdgpu/amd_PM4.h
> @@ -192,6 +192,9 @@
>  		 * 1 - pfp
>  		 */
>  
> +#define PACKET3_INDIRECT_BUFFER                         0x3F
> +#define PACKET3_PROTECTED_FENCE_SIGNAL                  0xd0
> +
>  #define	PACKET3_WRITE_DATA				0x37
>  #define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
>  		/* 0 - register
> diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
> index 577b38387..85d69f5c6 100644
> --- a/lib/amdgpu/amd_ip_blocks.h
> +++ b/lib/amdgpu/amd_ip_blocks.h
> @@ -27,6 +27,11 @@
>  #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */
>  #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */
>  
> +/* User queue */
> +#define   S_3F3_INHERIT_VMID_MQD_GFX(x)        (((unsigned int)(x)&0x1) << 22)/* userqueue only */
> +#define   S_3F3_VALID_COMPUTE(x)		(((unsigned int)(x)&0x1) << 23)/* userqueue only */
> +#define   S_3F3_INHERIT_VMID_MQD_COMPUTE(x)	(((unsigned int)(x)&0x1) << 30)/* userqueue only */
> +
>  enum amd_ip_block_type {
>  	AMD_IP_GFX = 0,
>  	AMD_IP_COMPUTE,
> diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c
> new file mode 100644
> index 000000000..9412a37e8
> --- /dev/null
> +++ b/lib/amdgpu/amd_user_queue.c
> @@ -0,0 +1,418 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2025 Advanced Micro Devices, Inc.
> + */
> +
> +#include "amd_user_queue.h"
> +#include "amd_memory.h"
> +#include "amd_PM4.h"
> +#include "ioctl_wrappers.h"
> +
> +void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle, struct amdgpu_userq_bo *doorbell_bo,
> +			   unsigned int size, unsigned int domain)
> +{
> +	struct amdgpu_bo_alloc_request req = {0};
> +	amdgpu_bo_handle buf_handle;
> +	int r;
> +
> +	req.alloc_size = ALIGN(size, PAGE_SIZE);
> +	req.preferred_heap = domain;
> +	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
> +	igt_assert_eq(r, 0);
> +
> +	doorbell_bo->handle = buf_handle;
> +	doorbell_bo->size = req.alloc_size;
> +
> +	r = amdgpu_bo_cpu_map(doorbell_bo->handle,
> +			      (void **)&doorbell_bo->ptr);
> +	igt_assert_eq(r, 0);
> +}
> +
> +int
> +amdgpu_bo_alloc_and_map_uq(amdgpu_device_handle device_handle, unsigned int size,
> +			   unsigned int alignment, unsigned int heap, uint64_t alloc_flags,
> +			   uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
> +			   uint64_t *mc_address, amdgpu_va_handle *va_handle,
> +			   uint32_t timeline_syncobj_handle, uint64_t point)
> +{
> +	struct amdgpu_bo_alloc_request request = {};
> +	amdgpu_bo_handle buf_handle;
> +	uint64_t vmc_addr;
> +	int r;
> +
> +	request.alloc_size = size;
> +	request.phys_alignment = alignment;
> +	request.preferred_heap = heap;
> +	request.flags = alloc_flags;
> +
> +	r = amdgpu_bo_alloc(device_handle, &request, &buf_handle);
> +	if (r)
> +		return r;
> +
> +	r = amdgpu_va_range_alloc(device_handle,
> +				  amdgpu_gpu_va_range_general,
> +				  size, alignment, 0, &vmc_addr,
> +				  va_handle, 0);
> +	if (r)
> +		goto error_va_alloc;
> +
> +	r = amdgpu_bo_va_op_raw2(device_handle, buf_handle, 0,
> +				 ALIGN(size, getpagesize()), vmc_addr,
> +				 AMDGPU_VM_PAGE_READABLE |
> +				 AMDGPU_VM_PAGE_WRITEABLE |
> +				 AMDGPU_VM_PAGE_EXECUTABLE |
> +				 mapping_flags,
> +				 AMDGPU_VA_OP_MAP,
> +				 timeline_syncobj_handle,
> +				 point, 0, 0);
> +	if (r)
> +		goto error_va_map;
> +
> +	if (cpu) {
> +		r = amdgpu_bo_cpu_map(buf_handle, cpu);
> +		if (r)
> +			goto error_cpu_map;
> +	}
> +
> +	*bo = buf_handle;
> +	*mc_address = vmc_addr;
> +
> +	return 0;
> +
> +error_cpu_map:
> +	amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
> +error_va_map:
> +	amdgpu_va_range_free(*va_handle);
> +error_va_alloc:
> +	amdgpu_bo_free(buf_handle);
> +	return r;
> +}
> +
> +void amdgpu_bo_unmap_and_free_uq(amdgpu_device_handle device_handle, amdgpu_bo_handle bo,
> +			    amdgpu_va_handle va_handle, uint64_t mc_addr, uint64_t size,
> +			    uint32_t timeline_syncobj_handle, uint64_t point,
> +			    uint64_t syncobj_handles_array, uint32_t num_syncobj_handles)
> +{
> +	amdgpu_bo_cpu_unmap(bo);
> +	amdgpu_bo_va_op_raw2(device_handle, bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP,
> +				  timeline_syncobj_handle, point,
> +				  syncobj_handles_array, num_syncobj_handles);
> +	amdgpu_va_range_free(va_handle);
> +	amdgpu_bo_free(bo);
> +}
> +
> +int amdgpu_timeline_syncobj_wait(amdgpu_device_handle device_handle,
> +				 uint32_t timeline_syncobj_handle, uint64_t point)
> +{
> +	uint32_t flags = DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED;
> +	int r;
> +
> +	r = amdgpu_cs_syncobj_query2(device_handle, &timeline_syncobj_handle,
> +				     &point, 1, flags);
> +	if (r)
> +		return r;
> +
> +	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &timeline_syncobj_handle,
> +					    &point, 1, INT64_MAX,
> +					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> +					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> +					    NULL);
> +	if (r)
> +		igt_warn("Timeline timed out\n");
> +	return r;
> +}
> +
> +void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_context *ring_context,
> +			      unsigned int ip_type, uint64_t mc_address)
> +{
> +	int r;
> +	uint32_t *npkt = &ring_context->npkt;
> +	uint32_t *queue_cpu = ring_context->queue_cpu;
> +	uint32_t control = ring_context->pm4_dw;
> +	uint32_t syncarray[1];
> +
> +	struct drm_amdgpu_userq_signal signal_data;
> +
> +	/* Prepare the Indirect IB to submit the IB to user queue */
> +	queue_cpu[(*npkt)++] = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
> +	queue_cpu[(*npkt)++] = lower_32_bits(mc_address);
> +	queue_cpu[(*npkt)++] = upper_32_bits(mc_address);
> +
> +	if (ip_type == AMD_IP_GFX)
> +		queue_cpu[(*npkt)++] = control | S_3F3_INHERIT_VMID_MQD_GFX(1);
> +	else
> +		queue_cpu[(*npkt)++] = control | S_3F3_VALID_COMPUTE(1)
> +					       | S_3F3_INHERIT_VMID_MQD_COMPUTE(1);
> +
> +	queue_cpu[(*npkt)++] = PACKET3(PACKET3_PROTECTED_FENCE_SIGNAL, 0);
> +	/* empty dword is needed for fence signal pm4 */
> +	++*npkt;
> +
> +	*ring_context->wptr_cpu = *npkt;
> +	ring_context->doorbell_cpu[DOORBELL_INDEX] = *npkt;
> +
> +	/* Add a fence packet for signal */
> +	syncarray[0] = ring_context->timeline_syncobj_handle;
> +	signal_data.queue_id = ring_context->queue_id;
> +	signal_data.syncobj_handles = (uintptr_t)syncarray;
> +	signal_data.num_syncobj_handles = 1;
> +	signal_data.bo_read_handles = 0;
> +	signal_data.bo_write_handles = 0;
> +	signal_data.num_bo_read_handles = 0;
> +	signal_data.num_bo_write_handles = 0;
> +
> +	r = amdgpu_userq_signal(device, &signal_data);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_cs_syncobj_wait(device, &ring_context->timeline_syncobj_handle, 1, INT64_MAX,
> +				   DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL, NULL);
> +	igt_assert_eq(r, 0);
> +}
> +
> +void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
> +			       unsigned int type)
> +{
> +	int r;
> +
> +	if (type > AMD_IP_DMA) {
> +		igt_info("Invalid IP not supported for UMQ Submission\n");
> +		return;
> +	}
> +
> +	/* Free the Usermode Queue */
> +	r = amdgpu_free_userqueue(device_handle, ctxt->queue_id);
> +	igt_assert_eq(r, 0);
> +
> +	switch (type) {
> +	case AMD_IP_GFX:
> +		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->csa.handle,
> +					    ctxt->csa.va_handle,
> +					    ctxt->csa.mc_addr, ctxt->dev_info.csa_size,
> +					    ctxt->timeline_syncobj_handle, ++ctxt->point,
> +					    0, 0);
> +
> +		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->shadow.handle,
> +					    ctxt->shadow.va_handle,
> +					    ctxt->shadow.mc_addr, ctxt->dev_info.shadow_size,
> +					    ctxt->timeline_syncobj_handle, ++ctxt->point,
> +					    0, 0);
> +
> +		r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
> +						 ctxt->point);
> +		igt_assert_eq(r, 0);
> +		break;
> +
> +	case AMD_IP_COMPUTE:
> +		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->eop.handle,
> +					    ctxt->eop.va_handle,
> +					    ctxt->eop.mc_addr, 256,
> +					    ctxt->timeline_syncobj_handle, ++ctxt->point,
> +					    0, 0);
> +
> +		r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
> +						 ctxt->point);
> +		igt_assert_eq(r, 0);
> +		break;
> +
> +	case AMD_IP_DMA:
> +		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->csa.handle,
> +					    ctxt->csa.va_handle,
> +					    ctxt->csa.mc_addr, ctxt->dev_info.csa_size,
> +					    ctxt->timeline_syncobj_handle, ++ctxt->point,
> +					    0, 0);
> +
> +		r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
> +						 ctxt->point);
> +		igt_assert_eq(r, 0);
> +		break;
> +
> +	default:
> +		igt_info("IP invalid for cleanup\n");
> +	}
> +
> +	r = amdgpu_cs_destroy_syncobj(device_handle, ctxt->timeline_syncobj_handle);
> +	igt_assert_eq(r, 0);
> +
> +	/* Clean up doorbell*/
> +	r = amdgpu_bo_cpu_unmap(ctxt->doorbell.handle);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_bo_free(ctxt->doorbell.handle);
> +	igt_assert_eq(r, 0);
> +
> +	/* Clean up rptr wptr queue */
> +	amdgpu_bo_unmap_and_free(ctxt->rptr.handle, ctxt->rptr.va_handle,
> +				 ctxt->rptr.mc_addr, 8);
> +
> +	amdgpu_bo_unmap_and_free(ctxt->wptr.handle, ctxt->wptr.va_handle,
> +				 ctxt->wptr.mc_addr, 8);
> +
> +	amdgpu_bo_unmap_and_free(ctxt->queue.handle, ctxt->queue.va_handle,
> +				 ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE);
> +}
> +
> +void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
> +			      unsigned int type)
> +{
> +	int r;
> +	uint64_t gtt_flags = 0;
> +	struct drm_amdgpu_userq_mqd_gfx11 gfx_mqd;
> +	struct drm_amdgpu_userq_mqd_sdma_gfx11 sdma_mqd;
> +	struct drm_amdgpu_userq_mqd_compute_gfx11 compute_mqd;
> +	void *mqd;
> +
> +	if (type > AMD_IP_DMA) {
> +		igt_info("Invalid IP not supported for UMQ Submission\n");
> +		return;
> +	}
> +
> +	r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO,
> +			      sizeof(ctxt->dev_info), &ctxt->dev_info);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_cs_create_syncobj2(device_handle, 0, &ctxt->timeline_syncobj_handle);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_bo_alloc_and_map_uq(device_handle, USERMODE_QUEUE_SIZE,
> +				       ALIGNMENT,
> +				       AMDGPU_GEM_DOMAIN_GTT,
> +				       gtt_flags,
> +				       AMDGPU_VM_MTYPE_UC,
> +				       &ctxt->queue.handle, &ctxt->queue.ptr,
> +				       &ctxt->queue.mc_addr, &ctxt->queue.va_handle,
> +				       ctxt->timeline_syncobj_handle, ++ctxt->point);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_bo_alloc_and_map_uq(device_handle, 8,
> +				       ALIGNMENT,
> +				       AMDGPU_GEM_DOMAIN_GTT,
> +				       gtt_flags,
> +				       AMDGPU_VM_MTYPE_UC,
> +				       &ctxt->wptr.handle, &ctxt->wptr.ptr,
> +				       &ctxt->wptr.mc_addr, &ctxt->wptr.va_handle,
> +				       ctxt->timeline_syncobj_handle, ++ctxt->point);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_bo_alloc_and_map_uq(device_handle, 8,
> +				       ALIGNMENT,
> +				       AMDGPU_GEM_DOMAIN_GTT,
> +				       gtt_flags,
> +				       AMDGPU_VM_MTYPE_UC,
> +				       &ctxt->rptr.handle, &ctxt->rptr.ptr,
> +				       &ctxt->rptr.mc_addr, &ctxt->rptr.va_handle,
> +				       ctxt->timeline_syncobj_handle, ++ctxt->point);
> +	igt_assert_eq(r, 0);
> +
> +	switch (type) {
> +	case AMD_IP_GFX:
> +		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.shadow_size,
> +					       ctxt->dev_info.shadow_alignment,
> +					       AMDGPU_GEM_DOMAIN_GTT,
> +					       gtt_flags,
> +					       AMDGPU_VM_MTYPE_UC,
> +					       &ctxt->shadow.handle, NULL,
> +					       &ctxt->shadow.mc_addr, &ctxt->shadow.va_handle,
> +					       ctxt->timeline_syncobj_handle, ++ctxt->point);
> +		igt_assert_eq(r, 0);
> +
> +		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.csa_size,
> +					       ctxt->dev_info.csa_alignment,
> +					       AMDGPU_GEM_DOMAIN_GTT,
> +					       gtt_flags,
> +					       AMDGPU_VM_MTYPE_UC,
> +					       &ctxt->csa.handle, NULL,
> +					       &ctxt->csa.mc_addr, &ctxt->csa.va_handle,
> +					       ctxt->timeline_syncobj_handle, ++ctxt->point);
> +		igt_assert_eq(r, 0);
> +
> +		gfx_mqd.shadow_va = ctxt->shadow.mc_addr;
> +		gfx_mqd.csa_va = ctxt->csa.mc_addr;
> +		mqd = &gfx_mqd;
> +		break;
> +
> +	case AMD_IP_COMPUTE:
> +		r = amdgpu_bo_alloc_and_map_uq(device_handle, 256,
> +					       ALIGNMENT,
> +					       AMDGPU_GEM_DOMAIN_GTT,
> +					       gtt_flags,
> +					       AMDGPU_VM_MTYPE_UC,
> +					       &ctxt->eop.handle, NULL,
> +					       &ctxt->eop.mc_addr, &ctxt->eop.va_handle,
> +					       ctxt->timeline_syncobj_handle, ++ctxt->point);
> +		igt_assert_eq(r, 0);
> +		compute_mqd.eop_va = ctxt->eop.mc_addr;
> +		mqd = &compute_mqd;
> +		break;
> +
> +	case AMD_IP_DMA:
> +		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.csa_size,
> +					       ctxt->dev_info.csa_alignment,
> +					       AMDGPU_GEM_DOMAIN_GTT,
> +					       gtt_flags,
> +					       AMDGPU_VM_MTYPE_UC,
> +					       &ctxt->csa.handle, NULL,
> +					       &ctxt->csa.mc_addr, &ctxt->csa.va_handle,
> +					       ctxt->timeline_syncobj_handle, ++ctxt->point);
> +		igt_assert_eq(r, 0);
> +		sdma_mqd.csa_va = ctxt->csa.mc_addr;
> +		mqd = &sdma_mqd;
> +		break;
> +
> +	default:
> +		igt_info("Unsupported IP for UMQ submission\n");
> +		return;
> +
> +	}
> +
> +	r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
> +					 ctxt->point);
> +	igt_assert_eq(r, 0);
> +
> +	amdgpu_alloc_doorbell(device_handle, &ctxt->doorbell, PAGE_SIZE,
> +			      AMDGPU_GEM_DOMAIN_DOORBELL);
> +
> +	ctxt->doorbell_cpu = (uint64_t *)ctxt->doorbell.ptr;
> +
> +	ctxt->wptr_cpu = (uint64_t *)ctxt->wptr.ptr;
> +
> +	ctxt->queue_cpu = (uint32_t *)ctxt->queue.ptr;
> +	memset(ctxt->queue_cpu, 0, USERMODE_QUEUE_SIZE);
> +
> +	/* get db bo handle */
> +	amdgpu_bo_export(ctxt->doorbell.handle, amdgpu_bo_handle_type_kms, &ctxt->db_handle);
> +
> +	/* Create the Usermode Queue */
> +	switch (type) {
> +	case AMD_IP_GFX:
> +		r = amdgpu_create_userqueue(device_handle, AMDGPU_HW_IP_GFX,
> +					    ctxt->db_handle, DOORBELL_INDEX,
> +					    ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
> +					    ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
> +					    mqd, &ctxt->queue_id);
> +		igt_assert_eq(r, 0);
> +		break;
> +
> +	case AMD_IP_COMPUTE:
> +		r = amdgpu_create_userqueue(device_handle, AMDGPU_HW_IP_COMPUTE,
> +					    ctxt->db_handle, DOORBELL_INDEX,
> +					    ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
> +					    ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
> +					    mqd, &ctxt->queue_id);
> +		igt_assert_eq(r, 0);
> +		break;
> +
> +	case AMD_IP_DMA:
> +		r = amdgpu_create_userqueue(device_handle, AMDGPU_HW_IP_DMA,
> +					    ctxt->db_handle, DOORBELL_INDEX,
> +					    ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
> +					    ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
> +					    mqd, &ctxt->queue_id);
> +		igt_assert_eq(r, 0);
> +		break;
> +
> +	default:
> +		igt_info("Unsupported IP, failed to create user queue\n");
> +		return;
> +
> +	}
> +}
> diff --git a/lib/amdgpu/amd_user_queue.h b/lib/amdgpu/amd_user_queue.h
> new file mode 100644
> index 000000000..355f16f19
> --- /dev/null
> +++ b/lib/amdgpu/amd_user_queue.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: MIT
> + * Copyright 2025 Advanced Micro Devices, Inc.
> + */
> +
> +#ifndef _AMD_USER_QUEUE_
> +#define _AMD_USER_QUEUE_
> +
> +#include <amdgpu_drm.h>
> +#include <amdgpu.h>
> +#include <time.h>
> +#include "amd_ip_blocks.h"
> +
> +
> +#ifndef PAGE_SIZE
> +#define PAGE_SIZE 4096
> +#endif
> +
> +#define USERMODE_QUEUE_SIZE		(PAGE_SIZE * 256)   //In bytes
> +#define ALIGNMENT			4096
> +#define DOORBELL_INDEX			4
> +
> +void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle, struct amdgpu_userq_bo *doorbell_bo,
> +			   unsigned int size, unsigned int domain);
> +
> +int amdgpu_bo_alloc_and_map_uq(amdgpu_device_handle device_handle, unsigned int size,
> +			       unsigned int alignment, unsigned int heap, uint64_t alloc_flags,
> +			       uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
> +			       uint64_t *mc_address, amdgpu_va_handle *va_handle,
> +			       uint32_t timeline_syncobj_handle, uint64_t point);
> +
> +void amdgpu_bo_unmap_and_free_uq(amdgpu_device_handle device_handle, amdgpu_bo_handle bo,
> +				 amdgpu_va_handle va_handle, uint64_t mc_addr, uint64_t size,
> +				 uint32_t timeline_syncobj_handle, uint64_t point,
> +				 uint64_t syncobj_handles_array, uint32_t num_syncobj_handles);
> +
> +int amdgpu_timeline_syncobj_wait(amdgpu_device_handle device_handle,
> +				 uint32_t timeline_syncobj_handle, uint64_t point);
> +
> +void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
> +			      unsigned int ip_type);
> +
> +void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
> +			       unsigned int ip_type);
> +
> +void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_context *ring_context,
> +			      unsigned int ip_type, uint64_t mc_address);
> +
> +#endif
> diff --git a/lib/meson.build b/lib/meson.build
> index d01c90df9..d7bb72c57 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -165,7 +165,8 @@ if libdrm_amdgpu.found()
>  		'amdgpu/xalloc.h',
>  		'amdgpu/amd_cp_dma.c',
>  		'amdgpu/amd_mem_leak.c',
> -		'amdgpu/amd_mmd_shared.c'
> +		'amdgpu/amd_mmd_shared.c',
The inclusion of this new file should be guarded by the libdrm version or a compiler check. Either way, it's great to have a separate file for better organization and maintenance.
> +		'amdgpu/amd_user_queue.c'
>  	]
>  	if libdrm_amdgpu.version().version_compare('> 2.4.99')
>  		lib_sources +=[ 'amdgpu/amd_dispatch.c',]

RE: [PATCH v3 02/19] drm-uapi/amdgpu: sync with drm-next

[Khatri, Sunil]

[-- Attachment #1: Type: text/plain, Size: 7014 bytes --]

[AMD Official Use Only - AMD Internal Distribution Only]



From: Prosyak, Vitaly <Vitaly.Prosyak@amd.com>
Sent: Tuesday, April 1, 2025 12:42 AM
To: Khatri, Sunil <Sunil.Khatri@amd.com>; igt-dev@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Prosyak, Vitaly <Vitaly.Prosyak@amd.com>; Zhang, Jesse(Jie) <Jesse.Zhang@amd.com>
Subject: Re: [PATCH v3 02/19] drm-uapi/amdgpu: sync with drm-next



On 2025-03-28 04:23, Sunil Khatri wrote:

Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")



Added support of UAPI for user queue secure semaphore.

The semaphore is used to synchronize between the caller and

the gpu hw and user wait for the semaphore.



Signed-off-by: Sunil Khatri <sunil.khatri@amd.com><mailto:sunil.khatri@amd.com>

---

 include/drm-uapi/amdgpu_drm.h | 117 ++++++++++++++++++++++++++++++++++

 1 file changed, 117 insertions(+)



diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h

index d780e1f2a..fed39c9b4 100644

--- a/include/drm-uapi/amdgpu_drm.h

+++ b/include/drm-uapi/amdgpu_drm.h

@@ -55,6 +55,8 @@ extern "C" {

 #define DRM_AMDGPU_FENCE_TO_HANDLE     0x14

 #define DRM_AMDGPU_SCHED               0x15

 #define DRM_AMDGPU_USERQ               0x16

+#define DRM_AMDGPU_USERQ_SIGNAL        0x17

+#define DRM_AMDGPU_USERQ_WAIT          0x18



 #define DRM_IOCTL_AMDGPU_GEM_CREATE  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)

 #define DRM_IOCTL_AMDGPU_GEM_MMAP  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)

@@ -73,6 +75,8 @@ extern "C" {

 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)

 #define DRM_IOCTL_AMDGPU_SCHED   DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)

 #define DRM_IOCTL_AMDGPU_USERQ   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)

+#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)

+#define DRM_IOCTL_AMDGPU_USERQ_WAIT  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)



 /**

  * DOC: memory domains

@@ -442,6 +446,119 @@ struct drm_amdgpu_userq_mqd_compute_gfx11 {

  __u64   eop_va;

 };



+/* userq signal/wait ioctl */

+struct drm_amdgpu_userq_signal {

+ /**

+  * @queue_id: Queue handle used by the userq fence creation function

+  * to retrieve the WPTR.

+  */

+ __u32   queue_id;

+ __u32   pad;

+ /**

+  * @syncobj_handles: The list of syncobj handles submitted by the user queue

+  * job to be signaled.

+  */

I am not sure about the correctness of the 'list of syncobj handles.' If it is a list, the field should be of type list_head; if it's an array, it should be __u64*, since the next field declares num_syncobj_handles. Could you clarify this?

There are several fields like this ?

Hello Vitaly

These are the headers defined in the kernel and directly ported to the IGT lib drm header as various others in past.

These are being discussed between various stake holders like Marel, Alex and Christian and then these types and objects are defined.

Regards
Sunil khatri



+ __u64   syncobj_handles;

+ /**

+  * @num_syncobj_handles: A count that represents the number of syncobj handles in

+  * @syncobj_handles.

+  */

+ __u64   num_syncobj_handles;

+ /**

+  * @bo_read_handles: The list of BO handles that the submitted user queue job

+  * is using for read only. This will update BO fences in the kernel.

+  */

+ __u64   bo_read_handles;

+ /**

+  * @bo_write_handles: The list of BO handles that the submitted user queue job

+  * is using for write only. This will update BO fences in the kernel.

+  */

+ __u64   bo_write_handles;

+ /**

+  * @num_bo_read_handles: A count that represents the number of read BO handles in

+  * @bo_read_handles.

+  */

+ __u32   num_bo_read_handles;

+ /**

+  * @num_bo_write_handles: A count that represents the number of write BO handles in

+  * @bo_write_handles.

+  */

+ __u32   num_bo_write_handles;

+};

+

+struct drm_amdgpu_userq_fence_info {

+ /**

+  * @va: A gpu address allocated for each queue which stores the

+  * read pointer (RPTR) value.

+  */

+ __u64   va;

+ /**

+  * @value: A 64 bit value represents the write pointer (WPTR) of the

+  * queue commands which compared with the RPTR value to signal the

+  * fences.

+  */

+ __u64   value;

+};

+

+struct drm_amdgpu_userq_wait {

+ /**

+  * @syncobj_handles: The list of syncobj handles submitted by the user queue

+  * job to get the va/value pairs.

+  */

+ __u64   syncobj_handles;

+ /**

+  * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by

+  * the user queue job to get the va/value pairs at given @syncobj_timeline_points.

+  */

+ __u64   syncobj_timeline_handles;

+ /**

+  * @syncobj_timeline_points: The list of timeline syncobj points submitted by the

+  * user queue job for the corresponding @syncobj_timeline_handles.

+  */

+ __u64   syncobj_timeline_points;

+ /**

+  * @bo_read_handles: The list of read BO handles submitted by the user queue

+  * job to get the va/value pairs.

+  */

+ __u64   bo_read_handles;

+ /**

+  * @bo_write_handles: The list of write BO handles submitted by the user queue

+  * job to get the va/value pairs.

+  */

+ __u64   bo_write_handles;

+ /**

+  * @num_syncobj_timeline_handles: A count that represents the number of timeline

+  * syncobj handles in @syncobj_timeline_handles.

+  */

+ __u16   num_syncobj_timeline_handles;

+ /**

+  * @num_fences: This field can be used both as input and output. As input it defines

+  * the maximum number of fences that can be returned and as output it will specify

+  * how many fences were actually returned from the ioctl.

+  */

+ __u16   num_fences;

+ /**

+  * @num_syncobj_handles: A count that represents the number of syncobj handles in

+  * @syncobj_handles.

+  */

+ __u32   num_syncobj_handles;

+ /**

+  * @num_bo_read_handles: A count that represents the number of read BO handles in

+  * @bo_read_handles.

+  */

+ __u32   num_bo_read_handles;

+ /**

+  * @num_bo_write_handles: A count that represents the number of write BO handles in

+  * @bo_write_handles.

+  */

+ __u32   num_bo_write_handles;

+ /**

+  * @out_fences: The field is a return value from the ioctl containing the list of

+  * address/value pairs to wait for.

+  */

+ __u64   out_fences;

+};

+

 /* vm ioctl */

 #define AMDGPU_VM_OP_RESERVE_VMID      1

 #define AMDGPU_VM_OP_UNRESERVE_VMID    2

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RE: [PATCH v3 04/19] lib/amdgpu: Add support of amd user queues

[Khatri, Sunil]

[AMD Official Use Only - AMD Internal Distribution Only]

-----Original Message-----
From: Prosyak, Vitaly <Vitaly.Prosyak@amd.com>
Sent: Tuesday, April 1, 2025 9:52 AM
To: Khatri, Sunil <Sunil.Khatri@amd.com>; igt-dev@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Prosyak, Vitaly <Vitaly.Prosyak@amd.com>
Subject: Re: [PATCH v3 04/19] lib/amdgpu: Add support of amd user queues


On 2025-03-28 04:24, Sunil Khatri wrote:
> This is the first patch set to add support of UMQ(User mode queues)
> submission in IGT.
>
> UMQ allows users to directly create a user queue and submit workload
> to the GPU h/w to directly instead of sending the workload to kernel
> and then to GPU h/w.
>
> This will be used by test cases which will be testing the UMQ queues
> for gfx/compute and sdma to start with.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  lib/amdgpu/amd_PM4.h        |   3 +
>  lib/amdgpu/amd_ip_blocks.h  |   5 +
>  lib/amdgpu/amd_user_queue.c | 418
> ++++++++++++++++++++++++++++++++++++
>  lib/amdgpu/amd_user_queue.h |  48 +++++
>  lib/meson.build             |   3 +-
>  5 files changed, 476 insertions(+), 1 deletion(-)  create mode 100644
> lib/amdgpu/amd_user_queue.c  create mode 100644
> lib/amdgpu/amd_user_queue.h
>
> diff --git a/lib/amdgpu/amd_PM4.h b/lib/amdgpu/amd_PM4.h index
> 5bc3cb783..8f59b4223 100644
> --- a/lib/amdgpu/amd_PM4.h
> +++ b/lib/amdgpu/amd_PM4.h
> @@ -192,6 +192,9 @@
>                * 1 - pfp
>                */
>
> +#define PACKET3_INDIRECT_BUFFER                         0x3F
> +#define PACKET3_PROTECTED_FENCE_SIGNAL                  0xd0
> +
>  #define      PACKET3_WRITE_DATA                              0x37
>  #define              WRITE_DATA_DST_SEL(x)                   ((x) << 8)
>               /* 0 - register
> diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
> index 577b38387..85d69f5c6 100644
> --- a/lib/amdgpu/amd_ip_blocks.h
> +++ b/lib/amdgpu/amd_ip_blocks.h
> @@ -27,6 +27,11 @@
>  #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */  #define
> AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */
>
> +/* User queue */
> +#define   S_3F3_INHERIT_VMID_MQD_GFX(x)        (((unsigned int)(x)&0x1) << 22)/* userqueue only */
> +#define   S_3F3_VALID_COMPUTE(x)             (((unsigned int)(x)&0x1) << 23)/* userqueue only */
> +#define   S_3F3_INHERIT_VMID_MQD_COMPUTE(x)  (((unsigned int)(x)&0x1) << 30)/* userqueue only */
> +
>  enum amd_ip_block_type {
>       AMD_IP_GFX = 0,
>       AMD_IP_COMPUTE,
> diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c
> new file mode 100644 index 000000000..9412a37e8
> --- /dev/null
> +++ b/lib/amdgpu/amd_user_queue.c
> @@ -0,0 +1,418 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2025 Advanced Micro Devices, Inc.
> + */
> +
> +#include "amd_user_queue.h"
> +#include "amd_memory.h"
> +#include "amd_PM4.h"
> +#include "ioctl_wrappers.h"
> +
> +void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle, struct amdgpu_userq_bo *doorbell_bo,
> +                        unsigned int size, unsigned int domain) {
> +     struct amdgpu_bo_alloc_request req = {0};
> +     amdgpu_bo_handle buf_handle;
> +     int r;
> +
> +     req.alloc_size = ALIGN(size, PAGE_SIZE);
> +     req.preferred_heap = domain;
> +     r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
> +     igt_assert_eq(r, 0);
> +
> +     doorbell_bo->handle = buf_handle;
> +     doorbell_bo->size = req.alloc_size;
> +
> +     r = amdgpu_bo_cpu_map(doorbell_bo->handle,
> +                           (void **)&doorbell_bo->ptr);
> +     igt_assert_eq(r, 0);
> +}
> +
> +int
> +amdgpu_bo_alloc_and_map_uq(amdgpu_device_handle device_handle, unsigned int size,
> +                        unsigned int alignment, unsigned int heap, uint64_t alloc_flags,
> +                        uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
> +                        uint64_t *mc_address, amdgpu_va_handle *va_handle,
> +                        uint32_t timeline_syncobj_handle, uint64_t point) {
> +     struct amdgpu_bo_alloc_request request = {};
> +     amdgpu_bo_handle buf_handle;
> +     uint64_t vmc_addr;
> +     int r;
> +
> +     request.alloc_size = size;
> +     request.phys_alignment = alignment;
> +     request.preferred_heap = heap;
> +     request.flags = alloc_flags;
> +
> +     r = amdgpu_bo_alloc(device_handle, &request, &buf_handle);
> +     if (r)
> +             return r;
> +
> +     r = amdgpu_va_range_alloc(device_handle,
> +                               amdgpu_gpu_va_range_general,
> +                               size, alignment, 0, &vmc_addr,
> +                               va_handle, 0);
> +     if (r)
> +             goto error_va_alloc;
> +
> +     r = amdgpu_bo_va_op_raw2(device_handle, buf_handle, 0,
> +                              ALIGN(size, getpagesize()), vmc_addr,
> +                              AMDGPU_VM_PAGE_READABLE |
> +                              AMDGPU_VM_PAGE_WRITEABLE |
> +                              AMDGPU_VM_PAGE_EXECUTABLE |
> +                              mapping_flags,
> +                              AMDGPU_VA_OP_MAP,
> +                              timeline_syncobj_handle,
> +                              point, 0, 0);
> +     if (r)
> +             goto error_va_map;
> +
> +     if (cpu) {
> +             r = amdgpu_bo_cpu_map(buf_handle, cpu);
> +             if (r)
> +                     goto error_cpu_map;
> +     }
> +
> +     *bo = buf_handle;
> +     *mc_address = vmc_addr;
> +
> +     return 0;
> +
> +error_cpu_map:
> +     amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0,
> +AMDGPU_VA_OP_UNMAP);
> +error_va_map:
> +     amdgpu_va_range_free(*va_handle);
> +error_va_alloc:
> +     amdgpu_bo_free(buf_handle);
> +     return r;
> +}
> +
> +void amdgpu_bo_unmap_and_free_uq(amdgpu_device_handle device_handle, amdgpu_bo_handle bo,
> +                         amdgpu_va_handle va_handle, uint64_t mc_addr, uint64_t size,
> +                         uint32_t timeline_syncobj_handle, uint64_t point,
> +                         uint64_t syncobj_handles_array, uint32_t num_syncobj_handles)
> +{
> +     amdgpu_bo_cpu_unmap(bo);
> +     amdgpu_bo_va_op_raw2(device_handle, bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP,
> +                               timeline_syncobj_handle, point,
> +                               syncobj_handles_array, num_syncobj_handles);
> +     amdgpu_va_range_free(va_handle);
> +     amdgpu_bo_free(bo);
> +}
> +
> +int amdgpu_timeline_syncobj_wait(amdgpu_device_handle device_handle,
> +                              uint32_t timeline_syncobj_handle, uint64_t point) {
> +     uint32_t flags = DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED;
> +     int r;
> +
> +     r = amdgpu_cs_syncobj_query2(device_handle, &timeline_syncobj_handle,
> +                                  &point, 1, flags);
> +     if (r)
> +             return r;
> +
> +     r = amdgpu_cs_syncobj_timeline_wait(device_handle, &timeline_syncobj_handle,
> +                                         &point, 1, INT64_MAX,
> +                                         DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> +                                         DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> +                                         NULL);
> +     if (r)
> +             igt_warn("Timeline timed out\n");
> +     return r;
> +}
> +
> +void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_context *ring_context,
> +                           unsigned int ip_type, uint64_t mc_address) {
> +     int r;
> +     uint32_t *npkt = &ring_context->npkt;
> +     uint32_t *queue_cpu = ring_context->queue_cpu;
> +     uint32_t control = ring_context->pm4_dw;
> +     uint32_t syncarray[1];
> +
> +     struct drm_amdgpu_userq_signal signal_data;
> +
> +     /* Prepare the Indirect IB to submit the IB to user queue */
> +     queue_cpu[(*npkt)++] = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
> +     queue_cpu[(*npkt)++] = lower_32_bits(mc_address);
> +     queue_cpu[(*npkt)++] = upper_32_bits(mc_address);
> +
> +     if (ip_type == AMD_IP_GFX)
> +             queue_cpu[(*npkt)++] = control | S_3F3_INHERIT_VMID_MQD_GFX(1);
> +     else
> +             queue_cpu[(*npkt)++] = control | S_3F3_VALID_COMPUTE(1)
> +                                            | S_3F3_INHERIT_VMID_MQD_COMPUTE(1);
> +
> +     queue_cpu[(*npkt)++] = PACKET3(PACKET3_PROTECTED_FENCE_SIGNAL, 0);
> +     /* empty dword is needed for fence signal pm4 */
> +     ++*npkt;
> +
> +     *ring_context->wptr_cpu = *npkt;
> +     ring_context->doorbell_cpu[DOORBELL_INDEX] = *npkt;
> +
> +     /* Add a fence packet for signal */
> +     syncarray[0] = ring_context->timeline_syncobj_handle;
> +     signal_data.queue_id = ring_context->queue_id;
> +     signal_data.syncobj_handles = (uintptr_t)syncarray;
> +     signal_data.num_syncobj_handles = 1;
> +     signal_data.bo_read_handles = 0;
> +     signal_data.bo_write_handles = 0;
> +     signal_data.num_bo_read_handles = 0;
> +     signal_data.num_bo_write_handles = 0;
> +
> +     r = amdgpu_userq_signal(device, &signal_data);
> +     igt_assert_eq(r, 0);
> +
> +     r = amdgpu_cs_syncobj_wait(device, &ring_context->timeline_syncobj_handle, 1, INT64_MAX,
> +                                DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL, NULL);
> +     igt_assert_eq(r, 0);
> +}
> +
> +void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
> +                            unsigned int type)
> +{
> +     int r;
> +
> +     if (type > AMD_IP_DMA) {
> +             igt_info("Invalid IP not supported for UMQ Submission\n");
> +             return;
> +     }
> +
> +     /* Free the Usermode Queue */
> +     r = amdgpu_free_userqueue(device_handle, ctxt->queue_id);
> +     igt_assert_eq(r, 0);
> +
> +     switch (type) {
> +     case AMD_IP_GFX:
> +             amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->csa.handle,
> +                                         ctxt->csa.va_handle,
> +                                         ctxt->csa.mc_addr, ctxt->dev_info.csa_size,
> +                                         ctxt->timeline_syncobj_handle, ++ctxt->point,
> +                                         0, 0);
> +
> +             amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->shadow.handle,
> +                                         ctxt->shadow.va_handle,
> +                                         ctxt->shadow.mc_addr, ctxt->dev_info.shadow_size,
> +                                         ctxt->timeline_syncobj_handle, ++ctxt->point,
> +                                         0, 0);
> +
> +             r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
> +                                              ctxt->point);
> +             igt_assert_eq(r, 0);
> +             break;
> +
> +     case AMD_IP_COMPUTE:
> +             amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->eop.handle,
> +                                         ctxt->eop.va_handle,
> +                                         ctxt->eop.mc_addr, 256,
> +                                         ctxt->timeline_syncobj_handle, ++ctxt->point,
> +                                         0, 0);
> +
> +             r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
> +                                              ctxt->point);
> +             igt_assert_eq(r, 0);
> +             break;
> +
> +     case AMD_IP_DMA:
> +             amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->csa.handle,
> +                                         ctxt->csa.va_handle,
> +                                         ctxt->csa.mc_addr, ctxt->dev_info.csa_size,
> +                                         ctxt->timeline_syncobj_handle, ++ctxt->point,
> +                                         0, 0);
> +
> +             r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
> +                                              ctxt->point);
> +             igt_assert_eq(r, 0);
> +             break;
> +
> +     default:
> +             igt_info("IP invalid for cleanup\n");
> +     }
> +
> +     r = amdgpu_cs_destroy_syncobj(device_handle, ctxt->timeline_syncobj_handle);
> +     igt_assert_eq(r, 0);
> +
> +     /* Clean up doorbell*/
> +     r = amdgpu_bo_cpu_unmap(ctxt->doorbell.handle);
> +     igt_assert_eq(r, 0);
> +
> +     r = amdgpu_bo_free(ctxt->doorbell.handle);
> +     igt_assert_eq(r, 0);
> +
> +     /* Clean up rptr wptr queue */
> +     amdgpu_bo_unmap_and_free(ctxt->rptr.handle, ctxt->rptr.va_handle,
> +                              ctxt->rptr.mc_addr, 8);
> +
> +     amdgpu_bo_unmap_and_free(ctxt->wptr.handle, ctxt->wptr.va_handle,
> +                              ctxt->wptr.mc_addr, 8);
> +
> +     amdgpu_bo_unmap_and_free(ctxt->queue.handle, ctxt->queue.va_handle,
> +                              ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE); }
> +
> +void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
> +                           unsigned int type)
> +{
> +     int r;
> +     uint64_t gtt_flags = 0;
> +     struct drm_amdgpu_userq_mqd_gfx11 gfx_mqd;
> +     struct drm_amdgpu_userq_mqd_sdma_gfx11 sdma_mqd;
> +     struct drm_amdgpu_userq_mqd_compute_gfx11 compute_mqd;
> +     void *mqd;
> +
> +     if (type > AMD_IP_DMA) {
> +             igt_info("Invalid IP not supported for UMQ Submission\n");
> +             return;
> +     }
> +
> +     r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO,
> +                           sizeof(ctxt->dev_info), &ctxt->dev_info);
> +     igt_assert_eq(r, 0);
> +
> +     r = amdgpu_cs_create_syncobj2(device_handle, 0, &ctxt->timeline_syncobj_handle);
> +     igt_assert_eq(r, 0);
> +
> +     r = amdgpu_bo_alloc_and_map_uq(device_handle, USERMODE_QUEUE_SIZE,
> +                                    ALIGNMENT,
> +                                    AMDGPU_GEM_DOMAIN_GTT,
> +                                    gtt_flags,
> +                                    AMDGPU_VM_MTYPE_UC,
> +                                    &ctxt->queue.handle, &ctxt->queue.ptr,
> +                                    &ctxt->queue.mc_addr, &ctxt->queue.va_handle,
> +                                    ctxt->timeline_syncobj_handle, ++ctxt->point);
> +     igt_assert_eq(r, 0);
> +
> +     r = amdgpu_bo_alloc_and_map_uq(device_handle, 8,
> +                                    ALIGNMENT,
> +                                    AMDGPU_GEM_DOMAIN_GTT,
> +                                    gtt_flags,
> +                                    AMDGPU_VM_MTYPE_UC,
> +                                    &ctxt->wptr.handle, &ctxt->wptr.ptr,
> +                                    &ctxt->wptr.mc_addr, &ctxt->wptr.va_handle,
> +                                    ctxt->timeline_syncobj_handle, ++ctxt->point);
> +     igt_assert_eq(r, 0);
> +
> +     r = amdgpu_bo_alloc_and_map_uq(device_handle, 8,
> +                                    ALIGNMENT,
> +                                    AMDGPU_GEM_DOMAIN_GTT,
> +                                    gtt_flags,
> +                                    AMDGPU_VM_MTYPE_UC,
> +                                    &ctxt->rptr.handle, &ctxt->rptr.ptr,
> +                                    &ctxt->rptr.mc_addr, &ctxt->rptr.va_handle,
> +                                    ctxt->timeline_syncobj_handle, ++ctxt->point);
> +     igt_assert_eq(r, 0);
> +
> +     switch (type) {
> +     case AMD_IP_GFX:
> +             r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.shadow_size,
> +                                            ctxt->dev_info.shadow_alignment,
> +                                            AMDGPU_GEM_DOMAIN_GTT,
> +                                            gtt_flags,
> +                                            AMDGPU_VM_MTYPE_UC,
> +                                            &ctxt->shadow.handle, NULL,
> +                                            &ctxt->shadow.mc_addr, &ctxt->shadow.va_handle,
> +                                            ctxt->timeline_syncobj_handle, ++ctxt->point);
> +             igt_assert_eq(r, 0);
> +
> +             r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.csa_size,
> +                                            ctxt->dev_info.csa_alignment,
> +                                            AMDGPU_GEM_DOMAIN_GTT,
> +                                            gtt_flags,
> +                                            AMDGPU_VM_MTYPE_UC,
> +                                            &ctxt->csa.handle, NULL,
> +                                            &ctxt->csa.mc_addr, &ctxt->csa.va_handle,
> +                                            ctxt->timeline_syncobj_handle, ++ctxt->point);
> +             igt_assert_eq(r, 0);
> +
> +             gfx_mqd.shadow_va = ctxt->shadow.mc_addr;
> +             gfx_mqd.csa_va = ctxt->csa.mc_addr;
> +             mqd = &gfx_mqd;
> +             break;
> +
> +     case AMD_IP_COMPUTE:
> +             r = amdgpu_bo_alloc_and_map_uq(device_handle, 256,
> +                                            ALIGNMENT,
> +                                            AMDGPU_GEM_DOMAIN_GTT,
> +                                            gtt_flags,
> +                                            AMDGPU_VM_MTYPE_UC,
> +                                            &ctxt->eop.handle, NULL,
> +                                            &ctxt->eop.mc_addr, &ctxt->eop.va_handle,
> +                                            ctxt->timeline_syncobj_handle, ++ctxt->point);
> +             igt_assert_eq(r, 0);
> +             compute_mqd.eop_va = ctxt->eop.mc_addr;
> +             mqd = &compute_mqd;
> +             break;
> +
> +     case AMD_IP_DMA:
> +             r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.csa_size,
> +                                            ctxt->dev_info.csa_alignment,
> +                                            AMDGPU_GEM_DOMAIN_GTT,
> +                                            gtt_flags,
> +                                            AMDGPU_VM_MTYPE_UC,
> +                                            &ctxt->csa.handle, NULL,
> +                                            &ctxt->csa.mc_addr, &ctxt->csa.va_handle,
> +                                            ctxt->timeline_syncobj_handle, ++ctxt->point);
> +             igt_assert_eq(r, 0);
> +             sdma_mqd.csa_va = ctxt->csa.mc_addr;
> +             mqd = &sdma_mqd;
> +             break;
> +
> +     default:
> +             igt_info("Unsupported IP for UMQ submission\n");
> +             return;
> +
> +     }
> +
> +     r = amdgpu_timeline_syncobj_wait(device_handle, ctxt->timeline_syncobj_handle,
> +                                      ctxt->point);
> +     igt_assert_eq(r, 0);
> +
> +     amdgpu_alloc_doorbell(device_handle, &ctxt->doorbell, PAGE_SIZE,
> +                           AMDGPU_GEM_DOMAIN_DOORBELL);
> +
> +     ctxt->doorbell_cpu = (uint64_t *)ctxt->doorbell.ptr;
> +
> +     ctxt->wptr_cpu = (uint64_t *)ctxt->wptr.ptr;
> +
> +     ctxt->queue_cpu = (uint32_t *)ctxt->queue.ptr;
> +     memset(ctxt->queue_cpu, 0, USERMODE_QUEUE_SIZE);
> +
> +     /* get db bo handle */
> +     amdgpu_bo_export(ctxt->doorbell.handle, amdgpu_bo_handle_type_kms,
> +&ctxt->db_handle);
> +
> +     /* Create the Usermode Queue */
> +     switch (type) {
> +     case AMD_IP_GFX:
> +             r = amdgpu_create_userqueue(device_handle, AMDGPU_HW_IP_GFX,
> +                                         ctxt->db_handle, DOORBELL_INDEX,
> +                                         ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
> +                                         ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
> +                                         mqd, &ctxt->queue_id);
> +             igt_assert_eq(r, 0);
> +             break;
> +
> +     case AMD_IP_COMPUTE:
> +             r = amdgpu_create_userqueue(device_handle, AMDGPU_HW_IP_COMPUTE,
> +                                         ctxt->db_handle, DOORBELL_INDEX,
> +                                         ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
> +                                         ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
> +                                         mqd, &ctxt->queue_id);
> +             igt_assert_eq(r, 0);
> +             break;
> +
> +     case AMD_IP_DMA:
> +             r = amdgpu_create_userqueue(device_handle, AMDGPU_HW_IP_DMA,
> +                                         ctxt->db_handle, DOORBELL_INDEX,
> +                                         ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
> +                                         ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
> +                                         mqd, &ctxt->queue_id);
> +             igt_assert_eq(r, 0);
> +             break;
> +
> +     default:
> +             igt_info("Unsupported IP, failed to create user queue\n");
> +             return;
> +
> +     }
> +}
> diff --git a/lib/amdgpu/amd_user_queue.h b/lib/amdgpu/amd_user_queue.h
> new file mode 100644 index 000000000..355f16f19
> --- /dev/null
> +++ b/lib/amdgpu/amd_user_queue.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: MIT
> + * Copyright 2025 Advanced Micro Devices, Inc.
> + */
> +
> +#ifndef _AMD_USER_QUEUE_
> +#define _AMD_USER_QUEUE_
> +
> +#include <amdgpu_drm.h>
> +#include <amdgpu.h>
> +#include <time.h>
> +#include "amd_ip_blocks.h"
> +
> +
> +#ifndef PAGE_SIZE
> +#define PAGE_SIZE 4096
> +#endif
> +
> +#define USERMODE_QUEUE_SIZE          (PAGE_SIZE * 256)   //In bytes
> +#define ALIGNMENT                    4096
> +#define DOORBELL_INDEX                       4
> +
> +void amdgpu_alloc_doorbell(amdgpu_device_handle device_handle, struct amdgpu_userq_bo *doorbell_bo,
> +                        unsigned int size, unsigned int domain);
> +
> +int amdgpu_bo_alloc_and_map_uq(amdgpu_device_handle device_handle, unsigned int size,
> +                            unsigned int alignment, unsigned int heap, uint64_t alloc_flags,
> +                            uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
> +                            uint64_t *mc_address, amdgpu_va_handle *va_handle,
> +                            uint32_t timeline_syncobj_handle, uint64_t point);
> +
> +void amdgpu_bo_unmap_and_free_uq(amdgpu_device_handle device_handle, amdgpu_bo_handle bo,
> +                              amdgpu_va_handle va_handle, uint64_t mc_addr, uint64_t size,
> +                              uint32_t timeline_syncobj_handle, uint64_t point,
> +                              uint64_t syncobj_handles_array, uint32_t num_syncobj_handles);
> +
> +int amdgpu_timeline_syncobj_wait(amdgpu_device_handle device_handle,
> +                              uint32_t timeline_syncobj_handle, uint64_t point);
> +
> +void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
> +                           unsigned int ip_type);
> +
> +void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu_ring_context *ctxt,
> +                            unsigned int ip_type);
> +
> +void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_context *ring_context,
> +                           unsigned int ip_type, uint64_t mc_address);
> +
> +#endif
> diff --git a/lib/meson.build b/lib/meson.build index
> d01c90df9..d7bb72c57 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -165,7 +165,8 @@ if libdrm_amdgpu.found()
>               'amdgpu/xalloc.h',
>               'amdgpu/amd_cp_dma.c',
>               'amdgpu/amd_mem_leak.c',
> -             'amdgpu/amd_mmd_shared.c'
> +             'amdgpu/amd_mmd_shared.c',
The inclusion of this new file should be guarded by the libdrm version or a compiler check. Either way, it's great to have a separate file for better organization and maintenance.
> +             'amdgpu/amd_user_queue.c'
I agree to it but this file does have dependency on libdrm and which is yet to be upstreamed. That the reason of code being covered under a macro and later once we have fw and libdrm changes merged we could add the libdrm version check for this file. For now, this will not break any build for older/newer librm.

Regards
Sunil Khatri
>       ]
>       if libdrm_amdgpu.version().version_compare('> 2.4.99')
>               lib_sources +=[ 'amdgpu/amd_dispatch.c',]

Re: [PATCH v3 02/19] drm-uapi/amdgpu: sync with drm-next

[vitaly prosyak]

[-- Attachment #1: Type: text/plain, Size: 8311 bytes --]


On 2025-04-01 00:39, Khatri, Sunil wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
>
>  
>
>  
>
> *From:*Prosyak, Vitaly <Vitaly.Prosyak@amd.com>
> *Sent:* Tuesday, April 1, 2025 12:42 AM
> *To:* Khatri, Sunil <Sunil.Khatri@amd.com>; igt-dev@lists.freedesktop.org
> *Cc:* Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Prosyak, Vitaly <Vitaly.Prosyak@amd.com>; Zhang, Jesse(Jie) <Jesse.Zhang@amd.com>
> *Subject:* Re: [PATCH v3 02/19] drm-uapi/amdgpu: sync with drm-next
>
>  
>
>  
>
> On 2025-03-28 04:23, Sunil Khatri wrote:
>
>     Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")
>
>      
>
>     Added support of UAPI for user queue secure semaphore.
>
>     The semaphore is used to synchronize between the caller and
>
>     the gpu hw and user wait for the semaphore.
>
>      
>
>     Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> <mailto:sunil.khatri@amd.com>
>
>     ---
>
>      include/drm-uapi/amdgpu_drm.h | 117 ++++++++++++++++++++++++++++++++++
>
>      1 file changed, 117 insertions(+)
>
>      
>
>     diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
>
>     index d780e1f2a..fed39c9b4 100644
>
>     --- a/include/drm-uapi/amdgpu_drm.h
>
>     +++ b/include/drm-uapi/amdgpu_drm.h
>
>     @@ -55,6 +55,8 @@ extern "C" {
>
>      #define DRM_AMDGPU_FENCE_TO_HANDLE     0x14
>
>      #define DRM_AMDGPU_SCHED               0x15
>
>      #define DRM_AMDGPU_USERQ               0x16
>
>     +#define DRM_AMDGPU_USERQ_SIGNAL        0x17
>
>     +#define DRM_AMDGPU_USERQ_WAIT          0x18
>
>      
>
>      #define DRM_IOCTL_AMDGPU_GEM_CREATE  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>
>      #define DRM_IOCTL_AMDGPU_GEM_MMAP  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
>
>     @@ -73,6 +75,8 @@ extern "C" {
>
>      #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
>
>      #define DRM_IOCTL_AMDGPU_SCHED   DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
>
>      #define DRM_IOCTL_AMDGPU_USERQ   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
>
>     +#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
>
>     +#define DRM_IOCTL_AMDGPU_USERQ_WAIT  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
>
>      
>
>      /**
>
>       * DOC: memory domains
>
>     @@ -442,6 +446,119 @@ struct drm_amdgpu_userq_mqd_compute_gfx11 {
>
>       __u64   eop_va;
>
>      };
>
>      
>
>     +/* userq signal/wait ioctl */
>
>     +struct drm_amdgpu_userq_signal {
>
>     + /**
>
>     +  * @queue_id: Queue handle used by the userq fence creation function
>
>     +  * to retrieve the WPTR.
>
>     +  */
>
>     + __u32   queue_id;
>
>     + __u32   pad;
>
>     + /**
>
>     +  * @syncobj_handles: The list of syncobj handles submitted by the user queue
>
>     +  * job to be signaled.
>
>     +  */
>
> I am not sure about the correctness of the 'list of syncobj handles.' If it is a list, the field should be of type |list_head|; if it's an array, it should be |__u64*|, since the next field declares |num_syncobj_handles|. Could you clarify this?
>
> There are several fields like this ?
>
> Hello Vitaly
>
> These are the headers defined in the kernel and directly ported to the IGT lib drm header as various others in past.
>
> These are being discussed between various stake holders like Marel, Alex and Christian and then these types and objects are defined.
>
> Regards
> Sunil khatri
>

Hi Sunil, I got it. My question is about the comment: 'The list of BO handles.' Does this refer to an array of |__u64 bo_write_handles|, where |__u64| represents an address? Maybe, for historical reasons, it ended up being called a 'list'? Since it's already ported, there's nothing to discuss or change :)

>      
>
>     + __u64   syncobj_handles;
>
>     + /**
>
>     +  * @num_syncobj_handles: A count that represents the number of syncobj handles in
>
>     +  * @syncobj_handles.
>
>     +  */
>
>     + __u64   num_syncobj_handles;
>
>     + /**
>
>     +  * @bo_read_handles: The list of BO handles that the submitted user queue job
>
>     +  * is using for read only. This will update BO fences in the kernel.
>
>     +  */
>
>     + __u64   bo_read_handles;
>
>     + /**
>
>     +  * @bo_write_handles: The list of BO handles that the submitted user queue job
>
>     +  * is using for write only. This will update BO fences in the kernel.
>
>     +  */
>
>     + __u64   bo_write_handles;
>
>     + /**
>
>     +  * @num_bo_read_handles: A count that represents the number of read BO handles in
>
>     +  * @bo_read_handles.
>
>     +  */
>
>     + __u32   num_bo_read_handles;
>
>     + /**
>
>     +  * @num_bo_write_handles: A count that represents the number of write BO handles in
>
>     +  * @bo_write_handles.
>
>     +  */
>
>     + __u32   num_bo_write_handles;
>
>     +};
>
>     +
>
>     +struct drm_amdgpu_userq_fence_info {
>
>     + /**
>
>     +  * @va: A gpu address allocated for each queue which stores the
>
>     +  * read pointer (RPTR) value.
>
>     +  */
>
>     + __u64   va;
>
>     + /**
>
>     +  * @value: A 64 bit value represents the write pointer (WPTR) of the
>
>     +  * queue commands which compared with the RPTR value to signal the
>
>     +  * fences.
>
>     +  */
>
>     + __u64   value;
>
>     +};
>
>     +
>
>     +struct drm_amdgpu_userq_wait {
>
>     + /**
>
>     +  * @syncobj_handles: The list of syncobj handles submitted by the user queue
>
>     +  * job to get the va/value pairs.
>
>     +  */
>
>     + __u64   syncobj_handles;
>
>     + /**
>
>     +  * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by
>
>     +  * the user queue job to get the va/value pairs at given @syncobj_timeline_points.
>
>     +  */
>
>     + __u64   syncobj_timeline_handles;
>
>     + /**
>
>     +  * @syncobj_timeline_points: The list of timeline syncobj points submitted by the
>
>     +  * user queue job for the corresponding @syncobj_timeline_handles.
>
>     +  */
>
>     + __u64   syncobj_timeline_points;
>
>     + /**
>
>     +  * @bo_read_handles: The list of read BO handles submitted by the user queue
>
>     +  * job to get the va/value pairs.
>
>     +  */
>
>     + __u64   bo_read_handles;
>
>     + /**
>
>     +  * @bo_write_handles: The list of write BO handles submitted by the user queue
>
>     +  * job to get the va/value pairs.
>
>     +  */
>
>     + __u64   bo_write_handles;
>
>     + /**
>
>     +  * @num_syncobj_timeline_handles: A count that represents the number of timeline
>
>     +  * syncobj handles in @syncobj_timeline_handles.
>
>     +  */
>
>     + __u16   num_syncobj_timeline_handles;
>
>     + /**
>
>     +  * @num_fences: This field can be used both as input and output. As input it defines
>
>     +  * the maximum number of fences that can be returned and as output it will specify
>
>     +  * how many fences were actually returned from the ioctl.
>
>     +  */
>
>     + __u16   num_fences;
>
>     + /**
>
>     +  * @num_syncobj_handles: A count that represents the number of syncobj handles in
>
>     +  * @syncobj_handles.
>
>     +  */
>
>     + __u32   num_syncobj_handles;
>
>     + /**
>
>     +  * @num_bo_read_handles: A count that represents the number of read BO handles in
>
>     +  * @bo_read_handles.
>
>     +  */
>
>     + __u32   num_bo_read_handles;
>
>     + /**
>
>     +  * @num_bo_write_handles: A count that represents the number of write BO handles in
>
>     +  * @bo_write_handles.
>
>     +  */
>
>     + __u32   num_bo_write_handles;
>
>     + /**
>
>     +  * @out_fences: The field is a return value from the ioctl containing the list of
>
>     +  * address/value pairs to wait for.
>
>     +  */
>
>     + __u64   out_fences;
>
>     +};
>
>     +
>
>      /* vm ioctl */
>
>      #define AMDGPU_VM_OP_RESERVE_VMID      1
>
>      #define AMDGPU_VM_OP_UNRESERVE_VMID    2
>

[-- Attachment #2: Type: text/html, Size: 17572 bytes --]

RE: [PATCH v3 02/19] drm-uapi/amdgpu: sync with drm-next

[Khatri, Sunil]

[-- Attachment #1: Type: text/plain, Size: 8270 bytes --]

[AMD Official Use Only - AMD Internal Distribution Only]



From: Prosyak, Vitaly <Vitaly.Prosyak@amd.com>
Sent: Tuesday, April 1, 2025 10:20 AM
To: Khatri, Sunil <Sunil.Khatri@amd.com>; Prosyak, Vitaly <Vitaly.Prosyak@amd.com>; igt-dev@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Zhang, Jesse(Jie) <Jesse.Zhang@amd.com>
Subject: Re: [PATCH v3 02/19] drm-uapi/amdgpu: sync with drm-next



On 2025-04-01 00:39, Khatri, Sunil wrote:

[AMD Official Use Only - AMD Internal Distribution Only]



From: Prosyak, Vitaly <Vitaly.Prosyak@amd.com><mailto:Vitaly.Prosyak@amd.com>
Sent: Tuesday, April 1, 2025 12:42 AM
To: Khatri, Sunil <Sunil.Khatri@amd.com><mailto:Sunil.Khatri@amd.com>; igt-dev@lists.freedesktop.org<mailto:igt-dev@lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com><mailto:Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com><mailto:Christian.Koenig@amd.com>; Prosyak, Vitaly <Vitaly.Prosyak@amd.com><mailto:Vitaly.Prosyak@amd.com>; Zhang, Jesse(Jie) <Jesse.Zhang@amd.com><mailto:Jesse.Zhang@amd.com>
Subject: Re: [PATCH v3 02/19] drm-uapi/amdgpu: sync with drm-next



On 2025-03-28 04:23, Sunil Khatri wrote:

Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")



Added support of UAPI for user queue secure semaphore.

The semaphore is used to synchronize between the caller and

the gpu hw and user wait for the semaphore.



Signed-off-by: Sunil Khatri <sunil.khatri@amd.com><mailto:sunil.khatri@amd.com>

---

 include/drm-uapi/amdgpu_drm.h | 117 ++++++++++++++++++++++++++++++++++

 1 file changed, 117 insertions(+)



diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h

index d780e1f2a..fed39c9b4 100644

--- a/include/drm-uapi/amdgpu_drm.h

+++ b/include/drm-uapi/amdgpu_drm.h

@@ -55,6 +55,8 @@ extern "C" {

 #define DRM_AMDGPU_FENCE_TO_HANDLE     0x14

 #define DRM_AMDGPU_SCHED               0x15

 #define DRM_AMDGPU_USERQ               0x16

+#define DRM_AMDGPU_USERQ_SIGNAL        0x17

+#define DRM_AMDGPU_USERQ_WAIT          0x18



 #define DRM_IOCTL_AMDGPU_GEM_CREATE  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)

 #define DRM_IOCTL_AMDGPU_GEM_MMAP  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)

@@ -73,6 +75,8 @@ extern "C" {

 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)

 #define DRM_IOCTL_AMDGPU_SCHED   DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)

 #define DRM_IOCTL_AMDGPU_USERQ   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)

+#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)

+#define DRM_IOCTL_AMDGPU_USERQ_WAIT  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)



 /**

  * DOC: memory domains

@@ -442,6 +446,119 @@ struct drm_amdgpu_userq_mqd_compute_gfx11 {

  __u64   eop_va;

 };



+/* userq signal/wait ioctl */

+struct drm_amdgpu_userq_signal {

+ /**

+  * @queue_id: Queue handle used by the userq fence creation function

+  * to retrieve the WPTR.

+  */

+ __u32   queue_id;

+ __u32   pad;

+ /**

+  * @syncobj_handles: The list of syncobj handles submitted by the user queue

+  * job to be signaled.

+  */

I am not sure about the correctness of the 'list of syncobj handles.' If it is a list, the field should be of type list_head; if it's an array, it should be __u64*, since the next field declares num_syncobj_handles. Could you clarify this?

There are several fields like this ?

Hello Vitaly

These are the headers defined in the kernel and directly ported to the IGT lib drm header as various others in past.

These are being discussed between various stake holders like Marel, Alex and Christian and then these types and objects are defined.

Regards
Sunil khatri



Hi Sunil, I got it. My question is about the comment: 'The list of BO handles.' Does this refer to an array of __u64 bo_write_handles, where __u64 represents an address? Maybe, for historical reasons, it ended up being called a 'list'? Since it's already ported, there's nothing to discuss or change :)

No, bo_write_handles it’s just an integer not an array or list.  syncobj_handles is holding the address of an array which will be used by kernel to do a copy_from_user.

Regards
Sunil Khatri



+ __u64   syncobj_handles;

+ /**

+  * @num_syncobj_handles: A count that represents the number of syncobj handles in

+  * @syncobj_handles.

+  */

+ __u64   num_syncobj_handles;

+ /**

+  * @bo_read_handles: The list of BO handles that the submitted user queue job

+  * is using for read only. This will update BO fences in the kernel.

+  */

+ __u64   bo_read_handles;

+ /**

+  * @bo_write_handles: The list of BO handles that the submitted user queue job

+  * is using for write only. This will update BO fences in the kernel.

+  */

+ __u64   bo_write_handles;

+ /**

+  * @num_bo_read_handles: A count that represents the number of read BO handles in

+  * @bo_read_handles.

+  */

+ __u32   num_bo_read_handles;

+ /**

+  * @num_bo_write_handles: A count that represents the number of write BO handles in

+  * @bo_write_handles.

+  */

+ __u32   num_bo_write_handles;

+};

+

+struct drm_amdgpu_userq_fence_info {

+ /**

+  * @va: A gpu address allocated for each queue which stores the

+  * read pointer (RPTR) value.

+  */

+ __u64   va;

+ /**

+  * @value: A 64 bit value represents the write pointer (WPTR) of the

+  * queue commands which compared with the RPTR value to signal the

+  * fences.

+  */

+ __u64   value;

+};

+

+struct drm_amdgpu_userq_wait {

+ /**

+  * @syncobj_handles: The list of syncobj handles submitted by the user queue

+  * job to get the va/value pairs.

+  */

+ __u64   syncobj_handles;

+ /**

+  * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by

+  * the user queue job to get the va/value pairs at given @syncobj_timeline_points.

+  */

+ __u64   syncobj_timeline_handles;

+ /**

+  * @syncobj_timeline_points: The list of timeline syncobj points submitted by the

+  * user queue job for the corresponding @syncobj_timeline_handles.

+  */

+ __u64   syncobj_timeline_points;

+ /**

+  * @bo_read_handles: The list of read BO handles submitted by the user queue

+  * job to get the va/value pairs.

+  */

+ __u64   bo_read_handles;

+ /**

+  * @bo_write_handles: The list of write BO handles submitted by the user queue

+  * job to get the va/value pairs.

+  */

+ __u64   bo_write_handles;

+ /**

+  * @num_syncobj_timeline_handles: A count that represents the number of timeline

+  * syncobj handles in @syncobj_timeline_handles.

+  */

+ __u16   num_syncobj_timeline_handles;

+ /**

+  * @num_fences: This field can be used both as input and output. As input it defines

+  * the maximum number of fences that can be returned and as output it will specify

+  * how many fences were actually returned from the ioctl.

+  */

+ __u16   num_fences;

+ /**

+  * @num_syncobj_handles: A count that represents the number of syncobj handles in

+  * @syncobj_handles.

+  */

+ __u32   num_syncobj_handles;

+ /**

+  * @num_bo_read_handles: A count that represents the number of read BO handles in

+  * @bo_read_handles.

+  */

+ __u32   num_bo_read_handles;

+ /**

+  * @num_bo_write_handles: A count that represents the number of write BO handles in

+  * @bo_write_handles.

+  */

+ __u32   num_bo_write_handles;

+ /**

+  * @out_fences: The field is a return value from the ioctl containing the list of

+  * address/value pairs to wait for.

+  */

+ __u64   out_fences;

+};

+

 /* vm ioctl */

 #define AMDGPU_VM_OP_RESERVE_VMID      1

 #define AMDGPU_VM_OP_UNRESERVE_VMID    2

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Re: [PATCH v3 13/19] drm-uapi/amdgpu: sync with drm-next

[Kamil Konieczny]

Hi Sunil,
On 2025-03-28 at 13:54:10 +0530, Sunil Khatri wrote:
> Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")
> 

I could not find this commit in drm-next nor drm-tip,
please add also subject to hash, like

Align with kernel commit cd5bbb2532f2 ("drm/xe/uapi: Add a device query to
get EU stall sampling information").

One more point, you could also consider adding all in one patch
unless they come from different trees, then please indicate from which
ones they come.

Regards,
Kamil

> Adds a new subquery (AMDGPU_INFO_UQ_FW_AREAS) in
> AMDGPU_INFO_IOCTL to get the size and alignment of shadow
> and csa objects from the FW setup. This information is
> required for the userqueue consumers.
> 
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  include/drm-uapi/amdgpu_drm.h | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
> index fed39c9b4..8108c0c8a 100644
> --- a/include/drm-uapi/amdgpu_drm.h
> +++ b/include/drm-uapi/amdgpu_drm.h
> @@ -1439,6 +1439,27 @@ struct drm_amdgpu_info_hw_ip {
>  	__u32  ip_discovery_version;
>  };
>  
> +/* GFX metadata BO sizes and alignment info (in bytes) */
> +struct drm_amdgpu_info_uq_fw_areas_gfx {
> +	/* shadow area size */
> +	__u32 shadow_size;
> +	/* shadow area base virtual mem alignment */
> +	__u32 shadow_alignment;
> +	/* context save area size */
> +	__u32 csa_size;
> +	/* context save area base virtual mem alignment */
> +	__u32 csa_alignment;
> +};
> +
> +/* IP specific metadata related information used in the
> + * subquery AMDGPU_INFO_UQ_FW_AREAS
> + */
> +struct drm_amdgpu_info_uq_fw_areas {
> +	union {
> +		struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
> +	};
> +};
> +
>  struct drm_amdgpu_info_num_handles {
>  	/** Max handles as supported by firmware for UVD */
>  	__u32  uvd_max_handles;
> -- 
> 2.43.0
> 

Re: [PATCH v3 02/19] drm-uapi/amdgpu: sync with drm-next

[Kamil Konieczny]

Hi Sunil,
On 2025-03-28 at 13:53:59 +0530, Sunil Khatri wrote:
> Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")
> 

This also do not come from drm-tip nor drm-next ?
Am I missing something?

Could you give a link to lore.kernel.org to this patch?

Regards,
Kamil

> Added support of UAPI for user queue secure semaphore.
> The semaphore is used to synchronize between the caller and
> the gpu hw and user wait for the semaphore.
> 
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  include/drm-uapi/amdgpu_drm.h | 117 ++++++++++++++++++++++++++++++++++
>  1 file changed, 117 insertions(+)
> 
> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
> index d780e1f2a..fed39c9b4 100644
> --- a/include/drm-uapi/amdgpu_drm.h
> +++ b/include/drm-uapi/amdgpu_drm.h
> @@ -55,6 +55,8 @@ extern "C" {
>  #define DRM_AMDGPU_FENCE_TO_HANDLE	0x14
>  #define DRM_AMDGPU_SCHED		0x15
>  #define DRM_AMDGPU_USERQ		0x16
> +#define DRM_AMDGPU_USERQ_SIGNAL		0x17
> +#define DRM_AMDGPU_USERQ_WAIT		0x18
>  
>  #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>  #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
> @@ -73,6 +75,8 @@ extern "C" {
>  #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
>  #define DRM_IOCTL_AMDGPU_SCHED		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
>  #define DRM_IOCTL_AMDGPU_USERQ		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
> +#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
> +#define DRM_IOCTL_AMDGPU_USERQ_WAIT	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
>  
>  /**
>   * DOC: memory domains
> @@ -442,6 +446,119 @@ struct drm_amdgpu_userq_mqd_compute_gfx11 {
>  	__u64   eop_va;
>  };
>  
> +/* userq signal/wait ioctl */
> +struct drm_amdgpu_userq_signal {
> +	/**
> +	 * @queue_id: Queue handle used by the userq fence creation function
> +	 * to retrieve the WPTR.
> +	 */
> +	__u32	queue_id;
> +	__u32	pad;
> +	/**
> +	 * @syncobj_handles: The list of syncobj handles submitted by the user queue
> +	 * job to be signaled.
> +	 */
> +	__u64	syncobj_handles;
> +	/**
> +	 * @num_syncobj_handles: A count that represents the number of syncobj handles in
> +	 * @syncobj_handles.
> +	 */
> +	__u64	num_syncobj_handles;
> +	/**
> +	 * @bo_read_handles: The list of BO handles that the submitted user queue job
> +	 * is using for read only. This will update BO fences in the kernel.
> +	 */
> +	__u64	bo_read_handles;
> +	/**
> +	 * @bo_write_handles: The list of BO handles that the submitted user queue job
> +	 * is using for write only. This will update BO fences in the kernel.
> +	 */
> +	__u64	bo_write_handles;
> +	/**
> +	 * @num_bo_read_handles: A count that represents the number of read BO handles in
> +	 * @bo_read_handles.
> +	 */
> +	__u32	num_bo_read_handles;
> +	/**
> +	 * @num_bo_write_handles: A count that represents the number of write BO handles in
> +	 * @bo_write_handles.
> +	 */
> +	__u32	num_bo_write_handles;
> +};
> +
> +struct drm_amdgpu_userq_fence_info {
> +	/**
> +	 * @va: A gpu address allocated for each queue which stores the
> +	 * read pointer (RPTR) value.
> +	 */
> +	__u64	va;
> +	/**
> +	 * @value: A 64 bit value represents the write pointer (WPTR) of the
> +	 * queue commands which compared with the RPTR value to signal the
> +	 * fences.
> +	 */
> +	__u64	value;
> +};
> +
> +struct drm_amdgpu_userq_wait {
> +	/**
> +	 * @syncobj_handles: The list of syncobj handles submitted by the user queue
> +	 * job to get the va/value pairs.
> +	 */
> +	__u64	syncobj_handles;
> +	/**
> +	 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by
> +	 * the user queue job to get the va/value pairs at given @syncobj_timeline_points.
> +	 */
> +	__u64	syncobj_timeline_handles;
> +	/**
> +	 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the
> +	 * user queue job for the corresponding @syncobj_timeline_handles.
> +	 */
> +	__u64	syncobj_timeline_points;
> +	/**
> +	 * @bo_read_handles: The list of read BO handles submitted by the user queue
> +	 * job to get the va/value pairs.
> +	 */
> +	__u64	bo_read_handles;
> +	/**
> +	 * @bo_write_handles: The list of write BO handles submitted by the user queue
> +	 * job to get the va/value pairs.
> +	 */
> +	__u64	bo_write_handles;
> +	/**
> +	 * @num_syncobj_timeline_handles: A count that represents the number of timeline
> +	 * syncobj handles in @syncobj_timeline_handles.
> +	 */
> +	__u16	num_syncobj_timeline_handles;
> +	/**
> +	 * @num_fences: This field can be used both as input and output. As input it defines
> +	 * the maximum number of fences that can be returned and as output it will specify
> +	 * how many fences were actually returned from the ioctl.
> +	 */
> +	__u16	num_fences;
> +	/**
> +	 * @num_syncobj_handles: A count that represents the number of syncobj handles in
> +	 * @syncobj_handles.
> +	 */
> +	__u32	num_syncobj_handles;
> +	/**
> +	 * @num_bo_read_handles: A count that represents the number of read BO handles in
> +	 * @bo_read_handles.
> +	 */
> +	__u32	num_bo_read_handles;
> +	/**
> +	 * @num_bo_write_handles: A count that represents the number of write BO handles in
> +	 * @bo_write_handles.
> +	 */
> +	__u32	num_bo_write_handles;
> +	/**
> +	 * @out_fences: The field is a return value from the ioctl containing the list of
> +	 * address/value pairs to wait for.
> +	 */
> +	__u64	out_fences;
> +};
> +
>  /* vm ioctl */
>  #define AMDGPU_VM_OP_RESERVE_VMID	1
>  #define AMDGPU_VM_OP_UNRESERVE_VMID	2
> -- 
> 2.43.0
> 

Re: [PATCH v3 01/19] drm-uapi/amdgpu: sync with drm-next

[vitaly prosyak]

The entire series of 19 patches looks very good to me—thanks for the great work!

There are a few to-do items, such as making amdgpu_user_queue_submit an ASIC-specific hook due to the new parameters for futures ASIC's , and adding another function accordingly. 

Additionally, there are some hacks in amdgpu-disable-check-for-IP-presence-with-no-kernel-queue.patch.

However, given the urgency and the need to unblock Jesse for additional tests, I’d like to proceed with merging your patches.

Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>

On 2025-03-28 04:23, Sunil Khatri wrote:
> Sync with drm-next commit ("e0400bf7d91ed477b827a674e5d64406c78ffd48")
>
> This patch introduces new UAPI/IOCTL for usermode graphics
> queue. IGT test cases fill this structure and request
> the graphics driver to add a graphics work queue for it.
> The output of this UAPI is a queue id.
>
> This UAPI maps the queue into GPU, so the graphics app can start
> submitting work to the queue as soon as the call returns.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  include/drm-uapi/amdgpu_drm.h | 123 ++++++++++++++++++++++++++++++++++
>  1 file changed, 123 insertions(+)
>
> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
> index efe5de6ce..d780e1f2a 100644
> --- a/include/drm-uapi/amdgpu_drm.h
> +++ b/include/drm-uapi/amdgpu_drm.h
> @@ -54,6 +54,7 @@ extern "C" {
>  #define DRM_AMDGPU_VM			0x13
>  #define DRM_AMDGPU_FENCE_TO_HANDLE	0x14
>  #define DRM_AMDGPU_SCHED		0x15
> +#define DRM_AMDGPU_USERQ		0x16
>  
>  #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>  #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
> @@ -71,6 +72,7 @@ extern "C" {
>  #define DRM_IOCTL_AMDGPU_VM		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
>  #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
>  #define DRM_IOCTL_AMDGPU_SCHED		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
> +#define DRM_IOCTL_AMDGPU_USERQ		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
>  
>  /**
>   * DOC: memory domains
> @@ -319,6 +321,127 @@ union drm_amdgpu_ctx {
>  	union drm_amdgpu_ctx_out out;
>  };
>  
> +/* user queue IOCTL operations */
> +#define AMDGPU_USERQ_OP_CREATE	1
> +#define AMDGPU_USERQ_OP_FREE	2
> +
> +/*
> + * This structure is a container to pass input configuration
> + * info for all supported userqueue related operations.
> + * For operation AMDGPU_USERQ_OP_CREATE: user is expected
> + *  to set all fields, excep the parameter 'queue_id'.
> + * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected
> + *  to be set is 'queue_id', eveything else is ignored.
> + */
> +struct drm_amdgpu_userq_in {
> +	/** AMDGPU_USERQ_OP_* */
> +	__u32	op;
> +	/** Queue id passed for operation USERQ_OP_FREE */
> +	__u32	queue_id;
> +	/** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */
> +	__u32   ip_type;
> +	/**
> +	 * @doorbell_handle: the handle of doorbell GEM object
> +	 * associated with this userqueue client.
> +	 */
> +	__u32   doorbell_handle;
> +	/**
> +	 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
> +	 * Kernel will generate absolute doorbell offset using doorbell_handle
> +	 * and doorbell_offset in the doorbell bo.
> +	 */
> +	__u32   doorbell_offset;
> +	__u32 _pad;
> +	/**
> +	 * @queue_va: Virtual address of the GPU memory which holds the queue
> +	 * object. The queue holds the workload packets.
> +	 */
> +	__u64   queue_va;
> +	/**
> +	 * @queue_size: Size of the queue in bytes, this needs to be 256-byte
> +	 * aligned.
> +	 */
> +	__u64   queue_size;
> +	/**
> +	 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR.
> +	 * This object must be at least 8 byte in size and aligned to 8-byte offset.
> +	 */
> +	__u64   rptr_va;
> +	/**
> +	 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR.
> +	 * This object must be at least 8 byte in size and aligned to 8-byte offset.
> +	 *
> +	 * Queue, RPTR and WPTR can come from the same object, as long as the size
> +	 * and alignment related requirements are met.
> +	 */
> +	__u64   wptr_va;
> +	/**
> +	 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow
> +	 * the GPU to uniquely define and identify a usermode queue.
> +	 *
> +	 * MQD data can be of different size for different GPU IP/engine and
> +	 * their respective versions/revisions, so this points to a __u64 *
> +	 * which holds IP specific MQD of this usermode queue.
> +	 */
> +	__u64 mqd;
> +	/**
> +	 * @size: size of MQD data in bytes, it must match the MQD structure
> +	 * size of the respective engine/revision defined in UAPI for ex, for
> +	 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).
> +	 */
> +	__u64 mqd_size;
> +};
> +
> +/* The structure to carry output of userqueue ops */
> +struct drm_amdgpu_userq_out {
> +	/**
> +	 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique
> +	 * queue ID to represent the newly created userqueue in the system, otherwise
> +	 * it should be ignored.
> +	 */
> +	__u32	queue_id;
> +	__u32 _pad;
> +};
> +
> +union drm_amdgpu_userq {
> +	struct drm_amdgpu_userq_in in;
> +	struct drm_amdgpu_userq_out out;
> +};
> +
> +/* GFX V11 IP specific MQD parameters */
> +struct drm_amdgpu_userq_mqd_gfx11 {
> +	/**
> +	 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.
> +	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
> +	 */
> +	__u64   shadow_va;
> +	/**
> +	 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
> +	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
> +	 */
> +	__u64   csa_va;
> +};
> +
> +/* GFX V11 SDMA IP specific MQD parameters */
> +struct drm_amdgpu_userq_mqd_sdma_gfx11 {
> +	/**
> +	 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
> +	 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
> +	 * to get the size.
> +	 */
> +	__u64   csa_va;
> +};
> +
> +/* GFX V11 Compute IP specific MQD parameters */
> +struct drm_amdgpu_userq_mqd_compute_gfx11 {
> +	/**
> +	 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer.
> +	 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
> +	 * to get the size.
> +	 */
> +	__u64   eop_va;
> +};
> +
>  /* vm ioctl */
>  #define AMDGPU_VM_OP_RESERVE_VMID	1
>  #define AMDGPU_VM_OP_UNRESERVE_VMID	2

Re: [PATCH v3 13/19] drm-uapi/amdgpu: sync with drm-next

[vitaly prosyak]

On 2025-04-01 12:06, Kamil Konieczny wrote:
> Hi Sunil,
> On 2025-03-28 at 13:54:10 +0530, Sunil Khatri wrote:
>> Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")
>>
> Hi Kamil,
>
> I removed this line
>

Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")

> as I believe it's internal information. If there are no objections, I'd like to merge without it.
>
> I just saw your reply, but I'll wait until tomorrow.
>
Thanks, Vitaly
> I could not find this commit in drm-next nor drm-tip,
> please add also subject to hash, like
>
> Align with kernel commit cd5bbb2532f2 ("drm/xe/uapi: Add a device query to
> get EU stall sampling information").
>
> One more point, you could also consider adding all in one patch
> unless they come from different trees, then please indicate from which
> ones they come.
>
> Regards,
> Kamil
>> Adds a new subquery (AMDGPU_INFO_UQ_FW_AREAS) in
>> AMDGPU_INFO_IOCTL to get the size and alignment of shadow
>> and csa objects from the FW setup. This information is
>> required for the userqueue consumers.
>>
>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>> ---
>>  include/drm-uapi/amdgpu_drm.h | 21 +++++++++++++++++++++
>>  1 file changed, 21 insertions(+)
>>
>> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
>> index fed39c9b4..8108c0c8a 100644
>> --- a/include/drm-uapi/amdgpu_drm.h
>> +++ b/include/drm-uapi/amdgpu_drm.h
>> @@ -1439,6 +1439,27 @@ struct drm_amdgpu_info_hw_ip {
>>  	__u32  ip_discovery_version;
>>  };
>>  
>> +/* GFX metadata BO sizes and alignment info (in bytes) */
>> +struct drm_amdgpu_info_uq_fw_areas_gfx {
>> +	/* shadow area size */
>> +	__u32 shadow_size;
>> +	/* shadow area base virtual mem alignment */
>> +	__u32 shadow_alignment;
>> +	/* context save area size */
>> +	__u32 csa_size;
>> +	/* context save area base virtual mem alignment */
>> +	__u32 csa_alignment;
>> +};
>> +
>> +/* IP specific metadata related information used in the
>> + * subquery AMDGPU_INFO_UQ_FW_AREAS
>> + */
>> +struct drm_amdgpu_info_uq_fw_areas {
>> +	union {
>> +		struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
>> +	};
>> +};
>> +
>>  struct drm_amdgpu_info_num_handles {
>>  	/** Max handles as supported by firmware for UVD */
>>  	__u32  uvd_max_handles;
>> -- 
>> 2.43.0
>>

Re: [PATCH v3 13/19] drm-uapi/amdgpu: sync with drm-next

[vitaly prosyak]

On 2025-04-01 12:06, Kamil Konieczny wrote:
> Hi Sunil,
> On 2025-03-28 at 13:54:10 +0530, Sunil Khatri wrote:
>> Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")
>>
> Thanks Kamil,
>
> I also spotted this strange line and removed it from the commit. While reading your email, I realized it's internal information.
>
> If there are no objections, I'd like to merge without it. I'll wait until tomorrow.
>
Thanks, Vitaly

> I could not find this commit in drm-next nor drm-tip,
> please add also subject to hash, like
>
> Align with kernel commit cd5bbb2532f2 ("drm/xe/uapi: Add a device query to
> get EU stall sampling information").
>
> One more point, you could also consider adding all in one patch
> unless they come from different trees, then please indicate from which
> ones they come.
>
> Regards,
> Kamil
>
>> Adds a new subquery (AMDGPU_INFO_UQ_FW_AREAS) in
>> AMDGPU_INFO_IOCTL to get the size and alignment of shadow
>> and csa objects from the FW setup. This information is
>> required for the userqueue consumers.
>>
>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>> ---
>>  include/drm-uapi/amdgpu_drm.h | 21 +++++++++++++++++++++
>>  1 file changed, 21 insertions(+)
>>
>> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
>> index fed39c9b4..8108c0c8a 100644
>> --- a/include/drm-uapi/amdgpu_drm.h
>> +++ b/include/drm-uapi/amdgpu_drm.h
>> @@ -1439,6 +1439,27 @@ struct drm_amdgpu_info_hw_ip {
>>  	__u32  ip_discovery_version;
>>  };
>>  
>> +/* GFX metadata BO sizes and alignment info (in bytes) */
>> +struct drm_amdgpu_info_uq_fw_areas_gfx {
>> +	/* shadow area size */
>> +	__u32 shadow_size;
>> +	/* shadow area base virtual mem alignment */
>> +	__u32 shadow_alignment;
>> +	/* context save area size */
>> +	__u32 csa_size;
>> +	/* context save area base virtual mem alignment */
>> +	__u32 csa_alignment;
>> +};
>> +
>> +/* IP specific metadata related information used in the
>> + * subquery AMDGPU_INFO_UQ_FW_AREAS
>> + */
>> +struct drm_amdgpu_info_uq_fw_areas {
>> +	union {
>> +		struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
>> +	};
>> +};
>> +
>>  struct drm_amdgpu_info_num_handles {
>>  	/** Max handles as supported by firmware for UVD */
>>  	__u32  uvd_max_handles;
>> -- 
>> 2.43.0
>>

Re: [PATCH v3 13/19] drm-uapi/amdgpu: sync with drm-next

[Kamil Konieczny]

Hi Vitaly,
On 2025-04-01 at 19:52:45 -0400, vitaly prosyak wrote:
> 
> On 2025-04-01 12:06, Kamil Konieczny wrote:
> > Hi Sunil,
> > On 2025-03-28 at 13:54:10 +0530, Sunil Khatri wrote:
> >> Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")
> >>
> Hi Kamil,
>
> I removed this line
>
> 
> Sync with drm-next commit ("866fc4f7e772c4a397f9459754ed1b1872b3a3c6")
> 
> as I believe it's internal information. If there are no objections, I'd like to merge without it.
>
> I just saw your reply, but I'll wait until tomorrow.
>
> Thanks, Vitaly

Yes looks reasonable, please give at least link(s) to lore.kernel.org for
drm-uapi changes you are introducing, in case they are still discussed
and do not get into drm-next nor drm-tip.
Also when giving link(s) add also a subject of patch with a change.

Regards,
Kamil

> > I could not find this commit in drm-next nor drm-tip,
> > please add also subject to hash, like
> >
> > Align with kernel commit cd5bbb2532f2 ("drm/xe/uapi: Add a device query to
> > get EU stall sampling information").
> >
> > One more point, you could also consider adding all in one patch
> > unless they come from different trees, then please indicate from which
> > ones they come.
> >
> > Regards,
> > Kamil
> >> Adds a new subquery (AMDGPU_INFO_UQ_FW_AREAS) in
> >> AMDGPU_INFO_IOCTL to get the size and alignment of shadow
> >> and csa objects from the FW setup. This information is
> >> required for the userqueue consumers.
> >>
> >> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> >> ---
> >>  include/drm-uapi/amdgpu_drm.h | 21 +++++++++++++++++++++
> >>  1 file changed, 21 insertions(+)
> >>
> >> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
> >> index fed39c9b4..8108c0c8a 100644
> >> --- a/include/drm-uapi/amdgpu_drm.h
> >> +++ b/include/drm-uapi/amdgpu_drm.h
> >> @@ -1439,6 +1439,27 @@ struct drm_amdgpu_info_hw_ip {
> >>  	__u32  ip_discovery_version;
> >>  };
> >>  
> >> +/* GFX metadata BO sizes and alignment info (in bytes) */
> >> +struct drm_amdgpu_info_uq_fw_areas_gfx {
> >> +	/* shadow area size */
> >> +	__u32 shadow_size;
> >> +	/* shadow area base virtual mem alignment */
> >> +	__u32 shadow_alignment;
> >> +	/* context save area size */
> >> +	__u32 csa_size;
> >> +	/* context save area base virtual mem alignment */
> >> +	__u32 csa_alignment;
> >> +};
> >> +
> >> +/* IP specific metadata related information used in the
> >> + * subquery AMDGPU_INFO_UQ_FW_AREAS
> >> + */
> >> +struct drm_amdgpu_info_uq_fw_areas {
> >> +	union {
> >> +		struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
> >> +	};
> >> +};
> >> +
> >>  struct drm_amdgpu_info_num_handles {
> >>  	/** Max handles as supported by firmware for UVD */
> >>  	__u32  uvd_max_handles;
> >> -- 
> >> 2.43.0
> >>

✗ Xe.CI.Full: failure for series starting with [v3,01/19] drm-uapi/amdgpu: sync with drm-next

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 140364 bytes --]

== Series Details ==

Series: series starting with [v3,01/19] drm-uapi/amdgpu: sync with drm-next
URL   : https://patchwork.freedesktop.org/series/146929/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8291_FULL -> XEIGTPW_12872_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_12872_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_12872_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_12872_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-lnl:          [PASS][1] -> ([INCOMPLETE][2], [PASS][3]) +1 other test ( 1 incomplete, 1 pass )
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-8/igt@kms_panel_fitting@atomic-fastset.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_panel_fitting@atomic-fastset.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-3/igt@kms_panel_fitting@atomic-fastset.html

  * igt@xe_pm@s4-vm-bind-prefetch:
    - shard-dg2-set2:     [PASS][4] -> ([INCOMPLETE][5], [PASS][6])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-466/igt@xe_pm@s4-vm-bind-prefetch.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@xe_pm@s4-vm-bind-prefetch.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@xe_pm@s4-vm-bind-prefetch.html

  
Known issues
------------

  Here are the changes found in XEIGTPW_12872_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-bmg:          [PASS][7] -> [FAIL][8] ([Intel XE#4665])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-1/igt@intel_hwmon@hwmon-write.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@intel_hwmon@hwmon-write.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-dp-4-4-rc-ccs-cc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#3767]) +7 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-dp-4-4-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear:
    - shard-lnl:          [PASS][10] -> ([PASS][11], [FAIL][12]) ([Intel XE#911]) +3 other tests ( 1 fail, 1 pass )
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2327]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> ([SKIP][14], [SKIP][15]) ([Intel XE#2327]) +1 other test ( 2 skip )
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_big_fb@linear-32bpp-rotate-270.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#316])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-0:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][17] ([Intel XE#4543]) +2 other tests dmesg-fail
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-270:
    - shard-bmg:          NOTRUN -> ([SKIP][18], [SKIP][19]) ([Intel XE#1124]) +6 other tests ( 2 skip )
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#607])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-lnl:          NOTRUN -> ([SKIP][21], [SKIP][22]) ([Intel XE#1124]) +1 other test ( 2 skip )
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#1124]) +8 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#1124]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][25], [SKIP][26]) ([Intel XE#1124])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-adlp:         NOTRUN -> [SKIP][27] ([Intel XE#1124]) +6 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-dg2-set2:     [PASS][28] -> ([SKIP][29], [PASS][30]) ([Intel XE#2191])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-436/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          [PASS][31] -> ([SKIP][32], [PASS][33]) ([Intel XE#2314] / [Intel XE#2894])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-bmg:          [PASS][34] -> ([SKIP][35], [SKIP][36]) ([Intel XE#2314] / [Intel XE#2894])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
    - shard-adlp:         NOTRUN -> [SKIP][37] ([Intel XE#2191])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2314] / [Intel XE#2894])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#367])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> ([SKIP][40], [SKIP][41]) ([Intel XE#367])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][42] ([Intel XE#367])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-4-displays-3840x2160p:
    - shard-lnl:          NOTRUN -> ([SKIP][43], [SKIP][44]) ([Intel XE#1512])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][45] ([Intel XE#455] / [Intel XE#787]) +13 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][46] ([Intel XE#787]) +20 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][47] ([Intel XE#787]) +155 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> ([SKIP][48], [SKIP][49]) ([Intel XE#2887]) +18 other tests ( 2 skip )
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_ccs@crc-primary-basic-y-tiled-ccs.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_ccs@crc-primary-basic-y-tiled-ccs.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][50] ([Intel XE#455] / [Intel XE#787]) +34 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2887]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][52] ([Intel XE#3442])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [PASS][53] -> ([INCOMPLETE][54], [PASS][55]) ([Intel XE#3862])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> ([PASS][56], [INCOMPLETE][57]) ([Intel XE#3862])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#3432])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> ([SKIP][59], [SKIP][60]) ([Intel XE#3432])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> ([SKIP][61], [SKIP][62]) ([Intel XE#2652] / [Intel XE#787]) +7 other tests ( 2 skip )
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][63], [SKIP][64]) ([Intel XE#787]) +54 other tests ( 2 skip )
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-c-dp-4.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-c-dp-4.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][65], [SKIP][66]) ([Intel XE#455] / [Intel XE#787]) +10 other tests ( 2 skip )
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][67] -> [INCOMPLETE][68] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> ([SKIP][69], [SKIP][70]) ([Intel XE#2887]) +3 other tests ( 2 skip )
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-3/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-2:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][71] ([Intel XE#3113])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-2.html

  * igt@kms_cdclk@mode-transition@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#4417]) +3 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][73] ([Intel XE#4416]) +3 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_cdclk@plane-scaling@pipe-b-dp-2.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-dg2-set2:     NOTRUN -> [SKIP][74] ([Intel XE#306])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@ctm-green-to-red:
    - shard-bmg:          NOTRUN -> ([SKIP][75], [SKIP][76]) ([Intel XE#2325]) +1 other test ( 2 skip )
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_chamelium_color@ctm-green-to-red.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_chamelium_color@ctm-green-to-red.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-adlp:         NOTRUN -> [SKIP][77] ([Intel XE#306])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_chamelium_color@ctm-max.html
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#2325])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> ([SKIP][79], [SKIP][80]) ([Intel XE#2252]) +6 other tests ( 2 skip )
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#2252]) +4 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][82], [SKIP][83]) ([Intel XE#373])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_chamelium_frames@dp-crc-single.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-adlp:         NOTRUN -> [SKIP][84] ([Intel XE#373]) +2 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@vga-hpd-after-hibernate:
    - shard-lnl:          NOTRUN -> ([SKIP][85], [SKIP][86]) ([Intel XE#373])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@kms_chamelium_hpd@vga-hpd-after-hibernate.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_chamelium_hpd@vga-hpd-after-hibernate.html

  * igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][87] ([Intel XE#373]) +5 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-bmg:          NOTRUN -> ([SKIP][88], [SKIP][89]) ([Intel XE#2390])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_content_protection@dp-mst-lic-type-1.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][90] ([Intel XE#3304])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html

  * igt@kms_content_protection@srm@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][91] ([Intel XE#1178]) +2 other tests fail
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_content_protection@srm@pipe-a-dp-4.html

  * igt@kms_content_protection@uevent@pipe-a-dp-2:
    - shard-dg2-set2:     NOTRUN -> [FAIL][92] ([Intel XE#1188])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_content_protection@uevent@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          NOTRUN -> ([SKIP][93], [SKIP][94]) ([Intel XE#2321])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_cursor_crc@cursor-offscreen-512x512.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-256x85:
    - shard-bmg:          NOTRUN -> ([SKIP][95], [SKIP][96]) ([Intel XE#2320]) +4 other tests ( 2 skip )
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_cursor_crc@cursor-random-256x85.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_cursor_crc@cursor-random-256x85.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][97], [SKIP][98]) ([Intel XE#308])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_cursor_crc@cursor-random-512x512.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-128x42:
    - shard-lnl:          NOTRUN -> ([SKIP][99], [SKIP][100]) ([Intel XE#1424])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-4/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html

  * igt@kms_cursor_crc@cursor-rapid-movement-256x85:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#2320])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-adlp:         NOTRUN -> [SKIP][102] ([Intel XE#308])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
    - shard-bmg:          NOTRUN -> [SKIP][103] ([Intel XE#2321])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
    - shard-adlp:         [PASS][104] -> [DMESG-WARN][105] ([Intel XE#4173]) +3 other tests dmesg-warn
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-4/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
    - shard-dg2-set2:     NOTRUN -> ([PASS][106], [SKIP][107]) ([Intel XE#309])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-bmg:          NOTRUN -> ([SKIP][108], [SKIP][109]) ([Intel XE#2286])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][110] -> ([SKIP][111], [PASS][112]) ([Intel XE#2291]) +6 other tests ( 1 pass, 1 skip )
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-bmg:          [PASS][113] -> [SKIP][114] ([Intel XE#2291]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-adlp:         NOTRUN -> [SKIP][115] ([Intel XE#309]) +1 other test skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-lnl:          NOTRUN -> ([SKIP][116], [SKIP][117]) ([Intel XE#309])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-3/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-dg2-set2:     [PASS][118] -> ([SKIP][119], [PASS][120]) ([Intel XE#309]) +1 other test ( 1 pass, 1 skip )
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-466/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-dg2-set2:     NOTRUN -> [SKIP][121] ([Intel XE#309])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
    - shard-dg2-set2:     [PASS][122] -> [SKIP][123] ([Intel XE#309])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][124] -> ([PASS][125], [FAIL][126]) ([Intel XE#4667])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2-set2:     NOTRUN -> [SKIP][127] ([Intel XE#323])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> ([SKIP][128], [SKIP][129]) ([Intel XE#4210])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-bmg:          [PASS][130] -> ([SKIP][131], [PASS][132]) ([Intel XE#4302])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_display_modes@extended-mode-basic.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> ([SKIP][133], [SKIP][134]) ([Intel XE#1340])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-adlp:         NOTRUN -> [SKIP][135] ([Intel XE#4354])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-bmg:          [PASS][136] -> ([PASS][137], [SKIP][138]) ([Intel XE#4354])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_dp_link_training@non-uhbr-sst.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-bmg:          NOTRUN -> ([SKIP][139], [SKIP][140]) ([Intel XE#4354]) +1 other test ( 2 skip )
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_dp_link_training@uhbr-sst.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-bmg:          NOTRUN -> ([SKIP][141], [SKIP][142]) ([Intel XE#4331])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-bmg:          NOTRUN -> [SKIP][143] ([Intel XE#2244])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-bmg:          NOTRUN -> [SKIP][144] ([Intel XE#4156])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-bmg:          NOTRUN -> ([SKIP][145], [SKIP][146]) ([Intel XE#4156])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_fbcon_fbt@fbc-suspend.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank:
    - shard-dg2-set2:     [PASS][147] -> [SKIP][148] ([Intel XE#310])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_flip@2x-blocking-absolute-wf_vblank.html

  * igt@kms_flip@2x-busy-flip:
    - shard-adlp:         NOTRUN -> [SKIP][149] ([Intel XE#310])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_flip@2x-busy-flip.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-dg2-set2:     [PASS][150] -> ([FAIL][151], [FAIL][152]) ([Intel XE#301])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-435/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3:
    - shard-bmg:          [PASS][153] -> [FAIL][154] ([Intel XE#3321])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][155] -> ([FAIL][156], [PASS][157]) ([Intel XE#301]) +3 other tests ( 1 fail, 1 pass )
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-435/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a6-dp4.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a6-dp4.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3:
    - shard-bmg:          [PASS][158] -> ([PASS][159], [FAIL][160]) ([Intel XE#3321]) +1 other test ( 1 fail, 1 pass )
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ad-dp2-hdmi-a3:
    - shard-bmg:          [PASS][161] -> ([FAIL][162], [FAIL][163]) ([Intel XE#3321])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ad-dp2-hdmi-a3.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank@ad-dp2-hdmi-a3.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ad-dp2-hdmi-a3.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-dg2-set2:     [PASS][164] -> ([PASS][165], [SKIP][166]) ([Intel XE#310]) +3 other tests ( 1 pass, 1 skip )
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@kms_flip@2x-nonexisting-fb.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_flip@2x-nonexisting-fb.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
    - shard-bmg:          [PASS][167] -> ([PASS][168], [SKIP][169]) ([Intel XE#2316]) +8 other tests ( 1 pass, 1 skip )
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [PASS][170] -> [SKIP][171] ([Intel XE#2316])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-dg2-set2:     NOTRUN -> [SKIP][172] ([Intel XE#310])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_flip@2x-wf_vblank-ts-check.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-bmg:          [PASS][173] -> [INCOMPLETE][174] ([Intel XE#2049])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-7/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@d-hdmi-a6:
    - shard-dg2-set2:     NOTRUN -> ([PASS][175], [INCOMPLETE][176]) ([Intel XE#2049]) +1 other test ( 1 incomplete, 1 pass )
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_flip@flip-vs-blocking-wf-vblank@d-hdmi-a6.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_flip@flip-vs-blocking-wf-vblank@d-hdmi-a6.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][177] -> ([PASS][178], [FAIL][179]) ([Intel XE#301]) +3 other tests ( 1 fail, 1 pass )
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-dp4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][180] ([Intel XE#301] / [Intel XE#3321]) +1 other test fail
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6:
    - shard-dg2-set2:     NOTRUN -> [FAIL][181] ([Intel XE#301]) +8 other tests fail
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg2-set2:     [PASS][182] -> ([PASS][183], [INCOMPLETE][184]) ([Intel XE#2049] / [Intel XE#2597])
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-466/igt@kms_flip@flip-vs-suspend.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_flip@flip-vs-suspend.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a3:
    - shard-bmg:          [PASS][185] -> ([INCOMPLETE][186], [PASS][187]) ([Intel XE#2049] / [Intel XE#2597])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a3.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a3.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a3.html

  * igt@kms_flip@flip-vs-suspend@d-dp2:
    - shard-dg2-set2:     NOTRUN -> ([PASS][188], [INCOMPLETE][189]) ([Intel XE#2049] / [Intel XE#2597])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_flip@flip-vs-suspend@d-dp2.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_flip@flip-vs-suspend@d-dp2.html

  * igt@kms_flip@flip-vs-suspend@d-hdmi-a3:
    - shard-bmg:          NOTRUN -> ([PASS][190], [INCOMPLETE][191]) ([Intel XE#2049] / [Intel XE#2597])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_flip@flip-vs-suspend@d-hdmi-a3.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_flip@flip-vs-suspend@d-hdmi-a3.html

  * igt@kms_flip@plain-flip-ts-check:
    - shard-bmg:          [PASS][192] -> ([PASS][193], [FAIL][194]) ([Intel XE#2882]) +1 other test ( 1 fail, 1 pass )
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-1/igt@kms_flip@plain-flip-ts-check.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_flip@plain-flip-ts-check.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_flip@plain-flip-ts-check.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-lnl:          [PASS][195] -> ([FAIL][196], [PASS][197]) ([Intel XE#886]) +1 other test ( 1 fail, 1 pass )
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-8/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-3/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
    - shard-adlp:         NOTRUN -> [SKIP][198] ([Intel XE#455]) +9 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][199] ([Intel XE#455]) +6 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-bmg:          NOTRUN -> ([SKIP][200], [SKIP][201]) ([Intel XE#2293] / [Intel XE#2380]) +3 other tests ( 2 skip )
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> ([SKIP][202], [SKIP][203]) ([Intel XE#2293]) +3 other tests ( 2 skip )
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][204] ([Intel XE#2293] / [Intel XE#2380])
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][205] ([Intel XE#2293])
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][206] ([Intel XE#1401]) +1 other test skip
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][207] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x:
    - shard-adlp:         [PASS][208] -> [DMESG-FAIL][209] ([Intel XE#4543])
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y:
    - shard-adlp:         [PASS][210] -> [FAIL][211] ([Intel XE#1874])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][212] ([Intel XE#656]) +16 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> ([SKIP][213], [SKIP][214]) ([Intel XE#2311] / [Intel XE#2312]) +3 other tests ( 2 skip )
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][215] ([Intel XE#651]) +7 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][216] ([Intel XE#2311]) +10 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][217], [SKIP][218]) ([Intel XE#651]) +6 other tests ( 2 skip )
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [PASS][219] -> ([SKIP][220], [PASS][221]) ([Intel XE#656]) +5 other tests ( 1 pass, 1 skip )
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> ([SKIP][222], [SKIP][223]) ([Intel XE#2312] / [Intel XE#4141]) +1 other test ( 2 skip )
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> ([SKIP][224], [SKIP][225]) ([Intel XE#4141]) +4 other tests ( 2 skip )
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][226] ([Intel XE#4141]) +2 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][227] ([Intel XE#651]) +3 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> ([SKIP][228], [SKIP][229]) ([Intel XE#2311]) +16 other tests ( 2 skip )
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> ([SKIP][230], [SKIP][231]) ([Intel XE#656]) +1 other test ( 2 skip )
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-blt.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt:
    - shard-lnl:          NOTRUN -> ([SKIP][232], [SKIP][233]) ([Intel XE#651]) +1 other test ( 2 skip )
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> ([SKIP][234], [SKIP][235]) ([Intel XE#2313]) +17 other tests ( 2 skip )
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-bmg:          NOTRUN -> ([SKIP][236], [SKIP][237]) ([Intel XE#2312] / [Intel XE#2313]) +3 other tests ( 2 skip )
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][238] ([Intel XE#2312]) +7 other tests skip
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][239] ([Intel XE#656]) +2 other tests skip
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][240] ([Intel XE#2313]) +10 other tests skip
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][241], [SKIP][242]) ([Intel XE#653]) +4 other tests ( 2 skip )
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][243] ([Intel XE#653]) +5 other tests skip
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-dg2-set2:     NOTRUN -> [SKIP][244] ([Intel XE#653]) +12 other tests skip
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-bmg:          NOTRUN -> ([SKIP][245], [SKIP][246]) ([Intel XE#2502])
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_getfb@getfb-reject-ccs.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_getfb@getfb2-accept-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][247] ([Intel XE#1339])
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_getfb@getfb2-accept-ccs.html
    - shard-bmg:          NOTRUN -> ([SKIP][248], [SKIP][249]) ([Intel XE#2340])
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_getfb@getfb2-accept-ccs.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_getfb@getfb2-accept-ccs.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-bmg:          NOTRUN -> [SKIP][250] ([Intel XE#1503])
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][251] ([Intel XE#2927])
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_joiner@basic-ultra-joiner.html
    - shard-bmg:          NOTRUN -> [SKIP][252] ([Intel XE#2927])
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][253] ([Intel XE#2925])
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
    - shard-dg2-set2:     [PASS][254] -> ([PASS][255], [FAIL][256]) ([Intel XE#616]) +1 other test ( 1 fail, 1 pass )
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-bmg:          NOTRUN -> ([SKIP][257], [SKIP][258]) ([Intel XE#2393])
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_plane_lowres@tiling-y.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-bmg:          [PASS][259] -> ([PASS][260], [SKIP][261]) ([Intel XE#4596]) +1 other test ( 1 pass, 1 skip )
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-x.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-x.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-adlp:         NOTRUN -> [SKIP][262] ([Intel XE#4596]) +1 other test skip
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_plane_multiple@2x-tiling-yf.html
    - shard-bmg:          NOTRUN -> ([SKIP][263], [SKIP][264]) ([Intel XE#2493] / [Intel XE#4596])
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-yf.html
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-bmg:          NOTRUN -> ([SKIP][265], [SKIP][266]) ([Intel XE#2493])
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_plane_multiple@tiling-yf.html
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d:
    - shard-bmg:          NOTRUN -> [SKIP][267] ([Intel XE#2763]) +4 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
    - shard-bmg:          NOTRUN -> ([SKIP][268], [SKIP][269]) ([Intel XE#2763]) +9 other tests ( 2 skip )
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-bmg:          NOTRUN -> ([SKIP][270], [SKIP][271]) ([Intel XE#870])
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_pm_backlight@bad-brightness.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-adlp:         NOTRUN -> [SKIP][272] ([Intel XE#2938])
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_pm_backlight@brightness-with-dpms.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][273] ([Intel XE#2938])
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][274] ([Intel XE#870]) +1 other test skip
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [PASS][275] -> ([FAIL][276], [PASS][277]) ([Intel XE#718])
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-8/igt@kms_pm_dc@dc5-dpms.html
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-1/igt@kms_pm_dc@dc5-dpms.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-3/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          NOTRUN -> ([SKIP][278], [SKIP][279]) ([Intel XE#2392])
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_pm_dc@dc6-psr.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_pm_dc@dc6-psr.html
    - shard-adlp:         NOTRUN -> [SKIP][280] ([Intel XE#1129])
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][281] ([Intel XE#908])
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg2-set2:     [PASS][282] -> [SKIP][283] ([Intel XE#836])
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-bmg:          NOTRUN -> ([SKIP][284], [SKIP][285]) ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836]) +1 other test ( 2 skip )
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_pm_rpm@modeset-lpsp.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-bmg:          NOTRUN -> [SKIP][286] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][287], [SKIP][288]) ([Intel XE#1489]) +1 other test ( 2 skip )
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][289] ([Intel XE#1489]) +2 other tests skip
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-adlp:         NOTRUN -> [SKIP][290] ([Intel XE#1489]) +2 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
    - shard-bmg:          NOTRUN -> ([SKIP][291], [SKIP][292]) ([Intel XE#1489]) +4 other tests ( 2 skip )
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-psr-cursor-blt:
    - shard-adlp:         NOTRUN -> [SKIP][293] ([Intel XE#2850] / [Intel XE#929]) +4 other tests skip
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_psr@fbc-psr-cursor-blt.html

  * igt@kms_psr@fbc-psr-sprite-blt:
    - shard-bmg:          NOTRUN -> ([SKIP][294], [SKIP][295]) ([Intel XE#2234] / [Intel XE#2850]) +14 other tests ( 2 skip )
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_psr@fbc-psr-sprite-blt.html
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_psr@fbc-psr-sprite-blt.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][296] ([Intel XE#2850] / [Intel XE#929]) +5 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@psr2-cursor-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][297] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_psr@psr2-cursor-plane-move.html

  * igt@kms_psr@psr2-cursor-render:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][298], [SKIP][299]) ([Intel XE#2850] / [Intel XE#929]) +3 other tests ( 2 skip )
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_psr@psr2-cursor-render.html
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_psr@psr2-cursor-render.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-adlp:         NOTRUN -> [SKIP][300] ([Intel XE#3414])
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_rotation_crc@bad-pixel-format.html
    - shard-bmg:          NOTRUN -> [SKIP][301] ([Intel XE#3414] / [Intel XE#3904])
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][302], [SKIP][303]) ([Intel XE#3414])
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][304] ([Intel XE#3414])
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-bmg:          NOTRUN -> ([SKIP][305], [SKIP][306]) ([Intel XE#3414] / [Intel XE#3904]) +2 other tests ( 2 skip )
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_setmode@basic:
    - shard-bmg:          [PASS][307] -> ([PASS][308], [FAIL][309]) ([Intel XE#2883]) +6 other tests ( 1 fail, 1 pass )
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_setmode@basic.html
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_setmode@basic.html
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_setmode@basic.html
    - shard-dg2-set2:     NOTRUN -> [FAIL][310] ([Intel XE#2883]) +1 other test fail
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_setmode@basic.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-dg2-set2:     [PASS][311] -> ([SKIP][312], [PASS][313]) ([Intel XE#455])
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-435/igt@kms_setmode@clone-exclusive-crtc.html
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_setmode@clone-exclusive-crtc.html
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-dg2-set2:     [PASS][314] -> ([SKIP][315], [SKIP][316]) ([Intel XE#455])
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_setmode@invalid-clone-single-crtc.html
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_setmode@invalid-clone-single-crtc.html
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing@pipe-a-hdmi-a-6-dp-4:
    - shard-dg2-set2:     [PASS][317] -> ([ABORT][318], [PASS][319]) ([Intel XE#4540]) +1 other test ( 1 abort, 1 pass )
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_setmode@invalid-clone-single-crtc-stealing@pipe-a-hdmi-a-6-dp-4.html
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_setmode@invalid-clone-single-crtc-stealing@pipe-a-hdmi-a-6-dp-4.html
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_setmode@invalid-clone-single-crtc-stealing@pipe-a-hdmi-a-6-dp-4.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing@pipe-b-hdmi-a-6-dp-4:
    - shard-dg2-set2:     [PASS][320] -> ([PASS][321], [DMESG-WARN][322]) ([Intel XE#4212])
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_setmode@invalid-clone-single-crtc-stealing@pipe-b-hdmi-a-6-dp-4.html
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_setmode@invalid-clone-single-crtc-stealing@pipe-b-hdmi-a-6-dp-4.html
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_setmode@invalid-clone-single-crtc-stealing@pipe-b-hdmi-a-6-dp-4.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
    - shard-lnl:          [PASS][323] -> ([FAIL][324], [FAIL][325]) ([Intel XE#771] / [Intel XE#899]) +1 other test ( 2 fail )
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-1/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][326] -> [FAIL][327] ([Intel XE#4459]) +1 other test fail
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-4/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-3/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@kms_vrr@flip-dpms:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][328], [SKIP][329]) ([Intel XE#455])
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_vrr@flip-dpms.html
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_vrr@flip-dpms.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          NOTRUN -> ([SKIP][330], [SKIP][331]) ([Intel XE#1499])
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_vrr@flip-suspend.html
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@max-min:
    - shard-bmg:          NOTRUN -> [SKIP][332] ([Intel XE#1499])
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_vrr@max-min.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][333], [SKIP][334]) ([Intel XE#756])
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_writeback@writeback-pixel-formats.html
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_writeback@writeback-pixel-formats.html
    - shard-adlp:         NOTRUN -> [SKIP][335] ([Intel XE#756])
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_writeback@writeback-pixel-formats.html

  * igt@xe_compute_preempt@compute-preempt-many:
    - shard-bmg:          [PASS][336] -> ([FAIL][337], [FAIL][338]) ([Intel XE#4278]) +1 other test ( 2 fail )
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@xe_compute_preempt@compute-preempt-many.html
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@xe_compute_preempt@compute-preempt-many.html
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@xe_compute_preempt@compute-preempt-many.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute:
    - shard-dg2-set2:     NOTRUN -> [SKIP][339] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html

  * igt@xe_create@create-big-vram:
    - shard-adlp:         NOTRUN -> [SKIP][340] ([Intel XE#1062])
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@xe_create@create-big-vram.html

  * igt@xe_eu_stall@blocking-read:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][341], [SKIP][342]) ([Intel XE#4497])
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@xe_eu_stall@blocking-read.html
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@xe_eu_stall@blocking-read.html

  * igt@xe_eudebug@basic-vm-bind-ufence:
    - shard-bmg:          NOTRUN -> ([SKIP][343], [SKIP][344]) ([Intel XE#2905]) +7 other tests ( 2 skip )
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@xe_eudebug@basic-vm-bind-ufence.html
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@xe_eudebug@basic-vm-bind-ufence.html

  * igt@xe_eudebug@basic-vm-bind-ufence-reconnect:
    - shard-dg2-set2:     NOTRUN -> [SKIP][345] ([Intel XE#2905] / [Intel XE#3889])
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@xe_eudebug@basic-vm-bind-ufence-reconnect.html

  * igt@xe_eudebug@basic-vm-bind-ufence-sigint-client:
    - shard-bmg:          NOTRUN -> ([SKIP][346], [SKIP][347]) ([Intel XE#2905] / [Intel XE#3889]) +1 other test ( 2 skip )
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@xe_eudebug@basic-vm-bind-ufence-sigint-client.html
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@xe_eudebug@basic-vm-bind-ufence-sigint-client.html

  * igt@xe_eudebug@basic-vm-bind-vm-destroy:
    - shard-bmg:          NOTRUN -> [SKIP][348] ([Intel XE#2905]) +1 other test skip
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@xe_eudebug@basic-vm-bind-vm-destroy.html

  * igt@xe_eudebug_online@resume-dss:
    - shard-dg2-set2:     NOTRUN -> [SKIP][349] ([Intel XE#2905]) +2 other tests skip
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@xe_eudebug_online@resume-dss.html

  * igt@xe_eudebug_online@set-breakpoint-sigint-debugger:
    - shard-dg2-set2:     NOTRUN -> [SKIP][350] ([Intel XE#4577])
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@xe_eudebug_online@set-breakpoint-sigint-debugger.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram:
    - shard-adlp:         NOTRUN -> [SKIP][351] ([Intel XE#2905]) +3 other tests skip
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram.html

  * igt@xe_evict@evict-beng-small:
    - shard-adlp:         NOTRUN -> [SKIP][352] ([Intel XE#261] / [Intel XE#688]) +1 other test skip
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@xe_evict@evict-beng-small.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][353] ([Intel XE#2322]) +1 other test skip
   [353]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-bind:
    - shard-dg2-set2:     [PASS][354] -> [SKIP][355] ([Intel XE#1392]) +2 other tests skip
   [354]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-466/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html
   [355]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html

  * igt@xe_exec_basic@multigpu-once-basic:
    - shard-adlp:         NOTRUN -> [SKIP][356] ([Intel XE#1392]) +2 other tests skip
   [356]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@xe_exec_basic@multigpu-once-basic.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-bind:
    - shard-bmg:          NOTRUN -> ([SKIP][357], [SKIP][358]) ([Intel XE#2322]) +8 other tests ( 2 skip )
   [357]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
   [358]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
    - shard-dg2-set2:     [PASS][359] -> ([SKIP][360], [PASS][361]) ([Intel XE#1392]) +2 other tests ( 1 pass, 1 skip )
   [359]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-466/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
   [360]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
   [361]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-prefetch:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][362], [SKIP][363]) ([Intel XE#288]) +3 other tests ( 2 skip )
   [362]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-prefetch.html
   [363]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-prefetch.html

  * igt@xe_exec_fault_mode@many-userptr-rebind-prefetch:
    - shard-adlp:         NOTRUN -> [SKIP][364] ([Intel XE#288]) +8 other tests skip
   [364]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@xe_exec_fault_mode@many-userptr-rebind-prefetch.html

  * igt@xe_exec_fault_mode@once-rebind-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][365] ([Intel XE#288]) +10 other tests skip
   [365]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@xe_exec_fault_mode@once-rebind-prefetch.html

  * igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit:
    - shard-dg2-set2:     NOTRUN -> [FAIL][366] ([Intel XE#1999]) +2 other tests fail
   [366]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html

  * igt@xe_oa@buffer-size@rcs-0-256k:
    - shard-lnl:          NOTRUN -> [FAIL][367] ([Intel XE#4541])
   [367]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-5/igt@xe_oa@buffer-size@rcs-0-256k.html

  * igt@xe_oa@closed-fd-and-unmapped-access:
    - shard-dg2-set2:     NOTRUN -> [SKIP][368] ([Intel XE#2541] / [Intel XE#3573]) +3 other tests skip
   [368]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@xe_oa@closed-fd-and-unmapped-access.html

  * igt@xe_oa@non-privileged-access-vaddr:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][369], [SKIP][370]) ([Intel XE#2541] / [Intel XE#3573])
   [369]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@xe_oa@non-privileged-access-vaddr.html
   [370]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@xe_oa@non-privileged-access-vaddr.html

  * igt@xe_oa@rc6-disable:
    - shard-adlp:         NOTRUN -> [SKIP][371] ([Intel XE#2541] / [Intel XE#3573]) +2 other tests skip
   [371]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@xe_oa@rc6-disable.html

  * igt@xe_oa@syncs-syncobj-cfg:
    - shard-dg2-set2:     NOTRUN -> [SKIP][372] ([Intel XE#2541] / [Intel XE#3573] / [Intel XE#4501])
   [372]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@xe_oa@syncs-syncobj-cfg.html

  * igt@xe_peer2peer@read:
    - shard-lnl:          NOTRUN -> ([SKIP][373], [SKIP][374]) ([Intel XE#1061])
   [373]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@xe_peer2peer@read.html
   [374]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@xe_peer2peer@read.html

  * igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
    - shard-dg2-set2:     NOTRUN -> [FAIL][375] ([Intel XE#1173]) +1 other test fail
   [375]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html

  * igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p:
    - shard-dg2-set2:     NOTRUN -> ([FAIL][376], [FAIL][377]) ([Intel XE#1173])
   [376]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html
   [377]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html

  * igt@xe_pm@d3cold-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][378] ([Intel XE#2284] / [Intel XE#366])
   [378]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@xe_pm@d3cold-basic.html

  * igt@xe_pm@d3hot-mmap-system:
    - shard-bmg:          NOTRUN -> [FAIL][379] ([Intel XE#3290])
   [379]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@xe_pm@d3hot-mmap-system.html

  * igt@xe_pm@d3hot-mmap-vram:
    - shard-adlp:         NOTRUN -> [SKIP][380] ([Intel XE#1948])
   [380]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@xe_pm@d3hot-mmap-vram.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-dg2-set2:     NOTRUN -> ([SKIP][381], [SKIP][382]) ([Intel XE#2284] / [Intel XE#366])
   [381]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@xe_pm@s2idle-d3cold-basic-exec.html
   [382]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pm@s4-basic:
    - shard-adlp:         [PASS][383] -> [ABORT][384] ([Intel XE#1794])
   [383]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-6/igt@xe_pm@s4-basic.html
   [384]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-9/igt@xe_pm@s4-basic.html

  * igt@xe_pm@s4-d3hot-basic-exec:
    - shard-lnl:          [PASS][385] -> [ABORT][386] ([Intel XE#1794])
   [385]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-4/igt@xe_pm@s4-d3hot-basic-exec.html
   [386]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-2/igt@xe_pm@s4-d3hot-basic-exec.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-lnl:          [PASS][387] -> ([ABORT][388], [PASS][389]) ([Intel XE#1794])
   [387]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-3/igt@xe_pm@s4-vm-bind-unbind-all.html
   [388]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html
   [389]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-4/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-bmg:          NOTRUN -> [SKIP][390] ([Intel XE#944])
   [390]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-dg2-set2:     NOTRUN -> [SKIP][391] ([Intel XE#944])
   [391]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-lnl:          NOTRUN -> [SKIP][392] ([Intel XE#944])
   [392]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@xe_query@multigpu-query-invalid-size.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-bmg:          NOTRUN -> ([SKIP][393], [SKIP][394]) ([Intel XE#944]) +1 other test ( 2 skip )
   [393]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@xe_query@multigpu-query-mem-usage.html
   [394]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@xe_query@multigpu-query-mem-usage.html
    - shard-adlp:         NOTRUN -> [SKIP][395] ([Intel XE#944])
   [395]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@xe_query@multigpu-query-mem-usage.html

  * igt@xe_sriov_auto_provisioning@exclusive-ranges:
    - shard-bmg:          NOTRUN -> ([SKIP][396], [SKIP][397]) ([Intel XE#4130]) +1 other test ( 2 skip )
   [396]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
   [397]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@xe_sriov_auto_provisioning@exclusive-ranges.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-bmg:          NOTRUN -> ([SKIP][398], [SKIP][399]) ([Intel XE#4273])
   [398]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@xe_sriov_flr@flr-vfs-parallel.html
   [399]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@xe_sriov_flr@flr-vfs-parallel.html

  
#### Possible fixes ####

  * igt@core_hotunplug@hotreplug:
    - shard-adlp:         [DMESG-WARN][400] ([Intel XE#4173]) -> [PASS][401] +11 other tests pass
   [400]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-4/igt@core_hotunplug@hotreplug.html
   [401]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@core_hotunplug@hotreplug.html

  * igt@kms_async_flips@invalid-async-flip-atomic@pipe-c-hdmi-a-1:
    - shard-adlp:         [DMESG-WARN][402] ([Intel XE#4543]) -> [PASS][403] +1 other test pass
   [402]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-8/igt@kms_async_flips@invalid-async-flip-atomic@pipe-c-hdmi-a-1.html
   [403]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-2/igt@kms_async_flips@invalid-async-flip-atomic@pipe-c-hdmi-a-1.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
    - shard-adlp:         [FAIL][404] ([Intel XE#3908]) -> [PASS][405] +1 other test pass
   [404]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-6/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
   [405]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-9/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-dg2-set2:     [SKIP][406] ([Intel XE#2191]) -> ([PASS][407], [PASS][408])
   [406]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [407]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [408]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [DMESG-WARN][409] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][410]
   [409]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
   [410]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][411] ([Intel XE#3124]) -> [PASS][412]
   [411]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html
   [412]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-bmg:          [SKIP][413] ([Intel XE#2291]) -> ([PASS][414], [PASS][415])
   [413]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
   [414]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
   [415]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-dg2-set2:     [SKIP][416] ([Intel XE#309]) -> ([PASS][417], [PASS][418]) +1 other test ( 2 pass )
   [416]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [417]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [418]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][419] ([Intel XE#2291]) -> [PASS][420]
   [419]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [420]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
    - shard-dg2-set2:     [INCOMPLETE][421] ([Intel XE#3226]) -> ([PASS][422], [PASS][423])
   [421]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
   [422]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
   [423]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-dg2-set2:     [SKIP][424] ([Intel XE#4354]) -> ([PASS][425], [PASS][426])
   [424]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_dp_link_training@non-uhbr-sst.html
   [425]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_dp_link_training@non-uhbr-sst.html
   [426]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible:
    - shard-dg2-set2:     [SKIP][427] ([Intel XE#310]) -> [PASS][428] +1 other test pass
   [427]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
   [428]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][429] ([Intel XE#3321]) -> [PASS][430] +1 other test pass
   [429]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-dp2-hdmi-a3.html
   [430]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-hdmi-a6-dp4:
    - shard-dg2-set2:     [FAIL][431] ([Intel XE#301] / [Intel XE#3321]) -> [PASS][432]
   [431]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-hdmi-a6-dp4.html
   [432]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4:
    - shard-dg2-set2:     [FAIL][433] ([Intel XE#301]) -> [PASS][434] +2 other tests pass
   [433]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html
   [434]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-bmg:          [SKIP][435] ([Intel XE#2316]) -> ([PASS][436], [PASS][437])
   [435]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [436]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [437]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-bmg:          [SKIP][438] ([Intel XE#2316]) -> [PASS][439] +1 other test pass
   [438]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_flip@2x-nonexisting-fb.html
   [439]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-dg2-set2:     [FAIL][440] ([Intel XE#886]) -> ([PASS][441], [PASS][442])
   [440]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
   [441]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
   [442]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a2-dp2:
    - shard-dg2-set2:     [FAIL][443] ([Intel XE#886]) -> [PASS][444]
   [443]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a2-dp2.html
   [444]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a2-dp2.html

  * igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a3:
    - shard-bmg:          [INCOMPLETE][445] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][446]
   [445]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a3.html
   [446]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a3.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a3:
    - shard-bmg:          [INCOMPLETE][447] ([Intel XE#2049] / [Intel XE#2597]) -> ([PASS][448], [PASS][449])
   [447]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-1/igt@kms_flip@flip-vs-suspend@b-hdmi-a3.html
   [448]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_flip@flip-vs-suspend@b-hdmi-a3.html
   [449]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_flip@flip-vs-suspend@b-hdmi-a3.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y:
    - shard-adlp:         [DMESG-FAIL][450] ([Intel XE#4543]) -> [PASS][451] +1 other test pass
   [450]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
   [451]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x:
    - shard-adlp:         [FAIL][452] ([Intel XE#1874]) -> [PASS][453]
   [452]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x.html
   [453]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][454] ([Intel XE#656]) -> [PASS][455]
   [454]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
   [455]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-dg2-set2:     [SKIP][456] ([Intel XE#656]) -> ([PASS][457], [PASS][458]) +2 other tests ( 2 pass )
   [456]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [457]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [458]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-dg2-set2:     [SKIP][459] ([Intel XE#836]) -> ([PASS][460], [PASS][461])
   [459]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [460]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [461]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race:
    - shard-dg2-set2:     [SKIP][462] ([Intel XE#1392]) -> ([PASS][463], [PASS][464]) +2 other tests ( 2 pass )
   [462]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
   [463]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
   [464]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
    - shard-dg2-set2:     [SKIP][465] ([Intel XE#1392]) -> [PASS][466] +1 other test pass
   [465]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
   [466]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html

  * igt@xe_pm@s4-basic-exec:
    - shard-adlp:         [ABORT][467] ([Intel XE#1794]) -> [PASS][468] +1 other test pass
   [467]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-9/igt@xe_pm@s4-basic-exec.html
   [468]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@xe_pm@s4-basic-exec.html

  * igt@xe_pm@s4-exec-after:
    - shard-lnl:          [ABORT][469] ([Intel XE#1794]) -> ([PASS][470], [PASS][471])
   [469]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-2/igt@xe_pm@s4-exec-after.html
   [470]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-8/igt@xe_pm@s4-exec-after.html
   [471]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@xe_pm@s4-exec-after.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-with-page-flip-events:
    - shard-adlp:         [DMESG-WARN][472] ([Intel XE#4173] / [Intel XE#4543]) -> [DMESG-WARN][473] ([Intel XE#4543])
   [472]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-2/igt@kms_async_flips@async-flip-with-page-flip-events.html
   [473]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@kms_async_flips@async-flip-with-page-flip-events.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-180:
    - shard-adlp:         [DMESG-FAIL][474] ([Intel XE#4173] / [Intel XE#4543]) -> [DMESG-FAIL][475] ([Intel XE#4543])
   [474]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-4/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
   [475]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-6/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][476] ([Intel XE#787]) -> ([SKIP][477], [SKIP][478]) ([Intel XE#455] / [Intel XE#787]) +2 other tests ( 2 skip )
   [476]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html
   [477]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html
   [478]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][479] ([Intel XE#787]) -> [SKIP][480] ([Intel XE#455] / [Intel XE#787]) +2 other tests skip
   [479]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html
   [480]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][481] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][482] ([Intel XE#787]) +4 other tests skip
   [481]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-6.html
   [482]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][483] ([Intel XE#455] / [Intel XE#787]) -> ([SKIP][484], [SKIP][485]) ([Intel XE#787]) +1 other test ( 2 skip )
   [483]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-6.html
   [484]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-6.html
   [485]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][486] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [INCOMPLETE][487] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [486]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [487]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][488] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124]) -> ([PASS][489], [INCOMPLETE][490]) ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345])
   [488]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [489]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [490]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][491] ([Intel XE#1727] / [Intel XE#3113]) -> ([PASS][492], [INCOMPLETE][493]) ([Intel XE#1727] / [Intel XE#3113]) +1 other test ( 1 incomplete, 1 pass )
   [491]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [492]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [493]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_content_protection@legacy:
    - shard-dg2-set2:     [FAIL][494] ([Intel XE#1178]) -> ([FAIL][495], [SKIP][496]) ([Intel XE#1178] / [Intel XE#455])
   [494]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_content_protection@legacy.html
   [495]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_content_protection@legacy.html
   [496]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@uevent:
    - shard-dg2-set2:     [FAIL][497] ([Intel XE#1188]) -> ([FAIL][498], [SKIP][499]) ([Intel XE#1188] / [Intel XE#455])
   [497]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-466/igt@kms_content_protection@uevent.html
   [498]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@kms_content_protection@uevent.html
   [499]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-dg2-set2:     [SKIP][500] ([Intel XE#309]) -> ([SKIP][501], [PASS][502]) ([Intel XE#309])
   [500]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [501]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [502]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-dg2-set2:     [SKIP][503] ([Intel XE#4302]) -> ([PASS][504], [SKIP][505]) ([Intel XE#4302])
   [503]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_display_modes@extended-mode-basic.html
   [504]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_display_modes@extended-mode-basic.html
   [505]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][506] ([Intel XE#3321]) -> ([FAIL][507], [PASS][508]) ([Intel XE#3321]) +1 other test ( 1 fail, 1 pass )
   [506]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
   [507]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
   [508]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [INCOMPLETE][509] ([Intel XE#2049] / [Intel XE#2597]) -> ([INCOMPLETE][510], [PASS][511]) ([Intel XE#2049] / [Intel XE#2597]) +1 other test ( 1 incomplete, 1 pass )
   [509]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_flip@flip-vs-suspend-interruptible.html
   [510]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [511]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-2/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate@a-edp1:
    - shard-lnl:          [FAIL][512] ([Intel XE#886]) -> ([FAIL][513], [PASS][514]) ([Intel XE#886]) +2 other tests ( 1 fail, 1 pass )
   [512]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-7/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
   [513]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
   [514]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-1/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling:
    - shard-adlp:         [DMESG-FAIL][515] ([Intel XE#4543]) -> [DMESG-FAIL][516] ([Intel XE#324] / [Intel XE#4543]) +3 other tests dmesg-fail
   [515]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-adlp-4/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html
   [516]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-adlp-1/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [SKIP][517] ([Intel XE#656]) -> [SKIP][518] ([Intel XE#651]) +3 other tests skip
   [517]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html
   [518]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-plflip-blt:
    - shard-bmg:          [SKIP][519] ([Intel XE#2312]) -> ([SKIP][520], [SKIP][521]) ([Intel XE#2311]) +4 other tests ( 2 skip )
   [519]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-plflip-blt.html
   [520]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-plflip-blt.html
   [521]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-rte:
    - shard-bmg:          [SKIP][522] ([Intel XE#2311]) -> ([SKIP][523], [SKIP][524]) ([Intel XE#2312])
   [522]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-rte.html
   [523]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-rte.html
   [524]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-rte.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][525] ([Intel XE#2311]) -> [SKIP][526] ([Intel XE#2312]) +3 other tests skip
   [525]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-render.html
   [526]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     [SKIP][527] ([Intel XE#651]) -> ([SKIP][528], [SKIP][529]) ([Intel XE#651] / [Intel XE#656]) +9 other tests ( 2 skip )
   [527]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html
   [528]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html
   [529]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][530] ([Intel XE#4141]) -> ([SKIP][531], [SKIP][532]) ([Intel XE#2312] / [Intel XE#4141]) +4 other tests ( 2 skip )
   [530]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [531]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [532]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move:
    - shard-bmg:          [SKIP][533] ([Intel XE#2312]) -> ([SKIP][534], [SKIP][535]) ([Intel XE#2312] / [Intel XE#4141])
   [533]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html
   [534]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html
   [535]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][536] ([Intel XE#2312]) -> ([SKIP][537], [SKIP][538]) ([Intel XE#4141]) +2 other tests ( 2 skip )
   [536]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [537]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [538]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
    - shard-bmg:          [SKIP][539] ([Intel XE#4141]) -> [SKIP][540] ([Intel XE#2312])
   [539]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
   [540]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][541] ([Intel XE#2312]) -> [SKIP][542] ([Intel XE#4141])
   [541]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html
   [542]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc:
    - shard-bmg:          [INCOMPLETE][543] ([Intel XE#2050]) -> [SKIP][544] ([Intel XE#4141])
   [543]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html
   [544]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt:
    - shard-dg2-set2:     [SKIP][545] ([Intel XE#656]) -> ([SKIP][546], [SKIP][547]) ([Intel XE#651] / [Intel XE#656]) +1 other test ( 2 skip )
   [545]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt.html
   [546]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt.html
   [547]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt:
    - shard-bmg:          [SKIP][548] ([Intel XE#2311]) -> ([SKIP][549], [SKIP][550]) ([Intel XE#2311] / [Intel XE#2312]) +14 other tests ( 2 skip )
   [548]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt.html
   [549]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt.html
   [550]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     [SKIP][551] ([Intel XE#651]) -> [SKIP][552] ([Intel XE#656])
   [551]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html
   [552]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     [SKIP][553] ([Intel XE#656]) -> ([SKIP][554], [SKIP][555]) ([Intel XE#651]) +4 other tests ( 2 skip )
   [553]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render.html
   [554]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render.html
   [555]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-bmg:          [SKIP][556] ([Intel XE#2313]) -> [SKIP][557] ([Intel XE#2312]) +3 other tests skip
   [556]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
   [557]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move:
    - shard-dg2-set2:     [SKIP][558] ([Intel XE#653]) -> [SKIP][559] ([Intel XE#656])
   [558]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html
   [559]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][560] ([Intel XE#653]) -> ([SKIP][561], [SKIP][562]) ([Intel XE#653] / [Intel XE#656]) +5 other tests ( 2 skip )
   [560]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
   [561]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
   [562]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][563] ([Intel XE#656]) -> ([SKIP][564], [SKIP][565]) ([Intel XE#653]) +2 other tests ( 2 skip )
   [563]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html
   [564]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html
   [565]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move:
    - shard-bmg:          [SKIP][566] ([Intel XE#2312]) -> ([SKIP][567], [SKIP][568]) ([Intel XE#2313]) +3 other tests ( 2 skip )
   [566]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move.html
   [567]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move.html
   [568]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][569] ([Intel XE#2313]) -> ([SKIP][570], [SKIP][571]) ([Intel XE#2312] / [Intel XE#2313]) +10 other tests ( 2 skip )
   [569]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [570]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [571]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][572] ([Intel XE#2313]) -> ([SKIP][573], [SKIP][574]) ([Intel XE#2312]) +2 other tests ( 2 skip )
   [572]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html
   [573]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html
   [574]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][575] ([Intel XE#656]) -> [SKIP][576] ([Intel XE#653]) +2 other tests skip
   [575]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html
   [576]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move:
    - shard-bmg:          [SKIP][577] ([Intel XE#2312]) -> [SKIP][578] ([Intel XE#2313]) +2 other tests skip
   [577]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move.html
   [578]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][579] ([Intel XE#653]) -> ([SKIP][580], [SKIP][581]) ([Intel XE#656]) +1 other test ( 2 skip )
   [579]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html
   [580]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html
   [581]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move:
    - shard-dg2-set2:     [SKIP][582] ([Intel XE#656]) -> ([SKIP][583], [SKIP][584]) ([Intel XE#653] / [Intel XE#656]) +2 other tests ( 2 skip )
   [582]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move.html
   [583]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move.html
   [584]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-dg2-set2:     [SKIP][585] ([Intel XE#455]) -> ([SKIP][586], [SKIP][587]) ([Intel XE#455] / [Intel XE#4596])
   [585]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@kms_plane_multiple@2x-tiling-y.html
   [586]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-466/igt@kms_plane_multiple@2x-tiling-y.html
   [587]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-dg2-set2:     [SKIP][588] ([Intel XE#4596]) -> [SKIP][589] ([Intel XE#455])
   [588]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-464/igt@kms_plane_multiple@2x-tiling-yf.html
   [589]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-433/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2-set2:     [ABORT][590] ([Intel XE#4540]) -> ([ABORT][591], [ABORT][592]) ([Intel XE#2705] / [Intel XE#4540])
   [590]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_plane_scaling@intel-max-src-size.html
   [591]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_plane_scaling@intel-max-src-size.html
   [592]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [ABORT][593] ([Intel XE#4540]) -> ([ABORT][594], [ABORT][595]) ([Intel XE#4502] / [Intel XE#4540])
   [593]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-463/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html
   [594]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-435/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html
   [595]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-lnl:          [FAIL][596] ([Intel XE#3924]) -> ([FAIL][597], [FAIL][598]) ([Intel XE#3924] / [Intel XE#4568]) +1 other test ( 2 fail )
   [596]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-8/igt@kms_psr@fbc-psr2-primary-render.html
   [597]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-6/igt@kms_psr@fbc-psr2-primary-render.html
   [598]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-2/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][599] ([Intel XE#2426]) -> ([SKIP][600], [SKIP][601]) ([Intel XE#2426] / [Intel XE#2509])
   [599]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [600]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [601]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-lnl:          [FAIL][602] ([Intel XE#771]) -> ([FAIL][603], [FAIL][604]) ([Intel XE#771] / [Intel XE#899]) +1 other test ( 2 fail )
   [602]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-4/igt@kms_universal_plane@cursor-fb-leak.html
   [603]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-4/igt@kms_universal_plane@cursor-fb-leak.html
   [604]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-1/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
    - shard-dg2-set2:     [SKIP][605] ([Intel XE#1392]) -> ([PASS][606], [SKIP][607]) ([Intel XE#1392]) +3 other tests ( 1 pass, 1 skip )
   [605]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
   [606]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-463/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
   [607]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html

  * igt@xe_oa@buffer-size:
    - shard-lnl:          [FAIL][608] ([Intel XE#4541]) -> ([PASS][609], [FAIL][610]) ([Intel XE#4541])
   [608]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-lnl-1/igt@xe_oa@buffer-size.html
   [609]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-7/igt@xe_oa@buffer-size.html
   [610]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-lnl-5/igt@xe_oa@buffer-size.html

  * igt@xe_peer2peer@write:
    - shard-dg2-set2:     [SKIP][611] ([Intel XE#1061]) -> ([FAIL][612], [FAIL][613]) ([Intel XE#1173])
   [611]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8291/shard-dg2-432/igt@xe_peer2peer@write.html
   [612]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-464/igt@xe_peer2peer@write.html
   [613]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/shard-dg2-436/igt@xe_peer2peer@write.html

  
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1062]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1062
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1339
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#1948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1948
  [Intel XE#1999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1999
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2050
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2340
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2493]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2493
  [Intel XE#2502]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2502
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
  [Intel XE#3290]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3290
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3767]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3767
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3889]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3889
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
  [Intel XE#3924]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3924
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4210]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4210
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4278
  [Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4497]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4497
  [Intel XE#4501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4501
  [Intel XE#4502]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4502
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4540
  [Intel XE#4541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4541
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4568]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4568
  [Intel XE#4577]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4577
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4665
  [Intel XE#4667]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4667
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/771
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8291 -> IGTPW_12872
  * Linux: xe-2863-274d97eed4e8376b7a66b8904066baed6a1ae874 -> xe-2868-c66e1b5495eda37a602bf54a9f4f34d476d2f3d7

  IGTPW_12872: 12872
  IGT_8291: a1809bc9d786d9b37a22e3e5e4810c6a0c84480b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-2863-274d97eed4e8376b7a66b8904066baed6a1ae874: 274d97eed4e8376b7a66b8904066baed6a1ae874
  xe-2868-c66e1b5495eda37a602bf54a9f4f34d476d2f3d7: c66e1b5495eda37a602bf54a9f4f34d476d2f3d7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12872/index.html

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