[PATCH i-g-t v3 00/10] tests/intel/xe_drm_fdinfo: Fix noise and improve

[PATCH i-g-t v3 00/10] tests/intel/xe_drm_fdinfo: Fix noise and improve

[Lucas De Marchi]

2 patch series together:
1) https://patchwork.freedesktop.org/series/137750/
2) https://patchwork.freedesktop.org/series/137742/

The first one was a single patch fixing a bug. It's the same fix here,
but now with a proper justification in the commit message.  I found a
(LNL) machine reproducing the failures every 2 or 3 runs and executed 50
times successfully with patch 1.

Patch 3 was a suggestion from Matt Roper, but for that to work we need
patch 2, as we don't have the relevant assert in igt. Patch 4 comes
as a bonus.

Other patches are the same as the second patch series.

With all patches applied I executed 100 times in that machine and
didn't have any failure.

v2: Remove bogus patch
v3: Fix the stricter == 0 check

Lucas De Marchi (10):
  tests/intel/xe_drm_fdinfo: Extend mercy to the upper end
  tests/intel/xe_drm_fdinfo: Print timestamp for debug
  lib/igt_core: Add igt_assert_lt_double()
  tests/intel/xe_drm_fdinfo: Use igt_assert_lt_double()
  tests/intel/xe_drm_fdinfo: Be strict on == 0 comparison
  tests/intel/xe_drm_fdinfo: Use usec for batch duration
  tests/intel/xe_drm_fdinfo: Half the execution time
  tests/intel/xe_drm_fdinfo: Remove unused flags
  tests/intel/xe_drm_fdinfo: Use enum with expected load
  tests/intel/xe_drm_fdinfo: Rename and reorder tests

 lib/igt_core.h              |  12 ++
 tests/intel/xe_drm_fdinfo.c | 260 +++++++++++++++++++-----------------
 2 files changed, 153 insertions(+), 119 deletions(-)

-- 
2.43.0

[PATCH i-g-t v3 01/10] tests/intel/xe_drm_fdinfo: Extend mercy to the upper end

[Lucas De Marchi]

When we are processing the fdinfo of each client, the gpu time is read
first, and then later all the exec queues are accumulated. It's thus
possible that the total gpu time is smaller than the time reported in
the exec queues. A preemption in the middle of second sample would
exaggerate the problem:
				  total_cycles	      cycles
	s1: read exec queues times			*
	s1: read gpu time		|		*
	.				|		*
	.				|		*
	.				|		*
	-> xe_spin_end()		|		*
	s2: read exec queues times	|
	s2: read gpu time		|

There's nothing guaranteeing and atomic read between the gpu time and
exec_queue time in either s1 or s2. Due to the call to xe_spin_end(),
in which exec_queue tick stops and gpu tick continues, it's much more
likely delta_total_cycles > cycles. However, if there was any additional
delay between the readout in s1, it could also go the other way.

In a more realistic situation, as reported in CI:

	(xe_drm_fdinfo:1072) DEBUG: rcs: sample 1: cycles 29223333, total_cycles 5801623069
	(xe_drm_fdinfo:1072) DEBUG: rcs: sample 2: cycles 38974256, total_cycles 5811276365
	(xe_drm_fdinfo:1072) DEBUG: rcs: percent: 101.000000

Extend the same mercy to the upper end as we did to the lower end.
This also matches the tolerance applied on the i915 side in
tests/intel/drm_fdinfo.c:__assert_within_epsilon().

v2: Fix the commit message since the problem is actually on sample1, not
    sample2

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 4696c6495..e3a99a2dc 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -484,7 +484,7 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
 	igt_debug("%s: percent: %f\n", engine_map[class], percent);
 
 	if (flags & TEST_BUSY)
-		igt_assert(percent >= 95 && percent <= 100);
+		igt_assert(percent >= 95 && percent <= 105);
 	else
 		igt_assert(!percent);
 }
-- 
2.43.0

Re: [PATCH i-g-t v3 01/10] tests/intel/xe_drm_fdinfo: Extend mercy to the upper end

[Nirmoy Das]

On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
> When we are processing the fdinfo of each client, the gpu time is read
> first, and then later all the exec queues are accumulated. It's thus
> possible that the total gpu time is smaller than the time reported in
> the exec queues. A preemption in the middle of second sample would
> exaggerate the problem:
> 				  total_cycles	      cycles
> 	s1: read exec queues times			*
> 	s1: read gpu time		|		*
> 	.				|		*
> 	.				|		*
> 	.				|		*
> 	-> xe_spin_end()		|		*
> 	s2: read exec queues times	|
> 	s2: read gpu time		|
>
> There's nothing guaranteeing and atomic read between the gpu time and
> exec_queue time in either s1 or s2. Due to the call to xe_spin_end(),
> in which exec_queue tick stops and gpu tick continues, it's much more
> likely delta_total_cycles > cycles. However, if there was any additional
> delay between the readout in s1, it could also go the other way.
>
> In a more realistic situation, as reported in CI:
>
> 	(xe_drm_fdinfo:1072) DEBUG: rcs: sample 1: cycles 29223333, total_cycles 5801623069
> 	(xe_drm_fdinfo:1072) DEBUG: rcs: sample 2: cycles 38974256, total_cycles 5811276365
> 	(xe_drm_fdinfo:1072) DEBUG: rcs: percent: 101.000000
>
> Extend the same mercy to the upper end as we did to the lower end.
> This also matches the tolerance applied on the i915 side in
> tests/intel/drm_fdinfo.c:__assert_within_epsilon().
>
> v2: Fix the commit message since the problem is actually on sample1, not
>      sample2
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

LGTM thanks for the detailed description.

Reviewed-by: Nirmoy.das@intel.com

> ---
>   tests/intel/xe_drm_fdinfo.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 4696c6495..e3a99a2dc 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -484,7 +484,7 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>   	igt_debug("%s: percent: %f\n", engine_map[class], percent);
>   
>   	if (flags & TEST_BUSY)
> -		igt_assert(percent >= 95 && percent <= 100);
> +		igt_assert(percent >= 95 && percent <= 105);
>   	else
>   		igt_assert(!percent);
>   }

Re: [PATCH i-g-t v3 01/10] tests/intel/xe_drm_fdinfo: Extend mercy to the upper end

[Nirmoy Das]

On 8/28/2024 4:44 PM, Nirmoy Das wrote:
>
> On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
>> When we are processing the fdinfo of each client, the gpu time is read
>> first, and then later all the exec queues are accumulated. It's thus
>> possible that the total gpu time is smaller than the time reported in
>> the exec queues. A preemption in the middle of second sample would
>> exaggerate the problem:
>>                   total_cycles          cycles
>>     s1: read exec queues times            *
>>     s1: read gpu time        |        *
>>     .                |        *
>>     .                |        *
>>     .                |        *
>>     -> xe_spin_end()        |        *
>>     s2: read exec queues times    |
>>     s2: read gpu time        |
>>
>> There's nothing guaranteeing and atomic read between the gpu time and
>> exec_queue time in either s1 or s2. Due to the call to xe_spin_end(),
>> in which exec_queue tick stops and gpu tick continues, it's much more
>> likely delta_total_cycles > cycles. However, if there was any additional
>> delay between the readout in s1, it could also go the other way.
>>
>> In a more realistic situation, as reported in CI:
>>
>>     (xe_drm_fdinfo:1072) DEBUG: rcs: sample 1: cycles 29223333, 
>> total_cycles 5801623069
>>     (xe_drm_fdinfo:1072) DEBUG: rcs: sample 2: cycles 38974256, 
>> total_cycles 5811276365
>>     (xe_drm_fdinfo:1072) DEBUG: rcs: percent: 101.000000
>>
>> Extend the same mercy to the upper end as we did to the lower end.
>> This also matches the tolerance applied on the i915 side in
>> tests/intel/drm_fdinfo.c:__assert_within_epsilon().
>>
>> v2: Fix the commit message since the problem is actually on sample1, not
>>      sample2
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> LGTM thanks for the detailed description.
>
> Reviewed-by: Nirmoy.das@intel.com

I was too quick.


Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
>
>> ---
>>   tests/intel/xe_drm_fdinfo.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
>> index 4696c6495..e3a99a2dc 100644
>> --- a/tests/intel/xe_drm_fdinfo.c
>> +++ b/tests/intel/xe_drm_fdinfo.c
>> @@ -484,7 +484,7 @@ check_results(struct pceu_cycles *s1, struct 
>> pceu_cycles *s2,
>>       igt_debug("%s: percent: %f\n", engine_map[class], percent);
>>         if (flags & TEST_BUSY)
>> -        igt_assert(percent >= 95 && percent <= 100);
>> +        igt_assert(percent >= 95 && percent <= 105);
>>       else
>>           igt_assert(!percent);
>>   }

[PATCH i-g-t v3 02/10] tests/intel/xe_drm_fdinfo: Print timestamp for debug

[Lucas De Marchi]

xe_spin is capable of writing the timestamp from the GPU side. This is a
good way to compare what we are reading from the fdinfo with what the
GPU is seeing. Example output:

(xe_drm_fdinfo:10404) DEBUG: rcs: spinner ended (timestamp=9817720)
(xe_drm_fdinfo:10404) DEBUG: bcs: spinner ended (timestamp=9755785)
(xe_drm_fdinfo:10404) DEBUG: vecs: spinner ended (timestamp=9653024)
(xe_drm_fdinfo:10404) DEBUG: ccs: spinner ended (timestamp=9722776)
(xe_drm_fdinfo:10404) DEBUG: rcs: sample 1: cycles 19513436, total_cycles 130596422980
(xe_drm_fdinfo:10404) DEBUG: rcs: sample 2: cycles 29331470, total_cycles 130606141449

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index e3a99a2dc..074a89711 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -416,6 +416,7 @@ spin_sync_start(int fd, struct spin_ctx *ctx)
 		return;
 
 	ctx->spin_opts.addr = ctx->addr;
+	ctx->spin_opts.write_timestamp = true;
 	ctx->spin_opts.preempt = true;
 	xe_spin_init(ctx->spin, &ctx->spin_opts);
 
@@ -448,7 +449,8 @@ spin_sync_end(int fd, struct spin_ctx *ctx)
 	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
 
 	ctx->ended = true;
-	igt_debug("%s: spinner ended\n", engine_map[ctx->class]);
+	igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
+		  ctx->spin->timestamp);
 }
 
 static void
-- 
2.43.0

Re: [PATCH i-g-t v3 02/10] tests/intel/xe_drm_fdinfo: Print timestamp for debug

[Nirmoy Das]

On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
> xe_spin is capable of writing the timestamp from the GPU side. This is a
> good way to compare what we are reading from the fdinfo with what the
> GPU is seeing. Example output:
>
> (xe_drm_fdinfo:10404) DEBUG: rcs: spinner ended (timestamp=9817720)
> (xe_drm_fdinfo:10404) DEBUG: bcs: spinner ended (timestamp=9755785)
> (xe_drm_fdinfo:10404) DEBUG: vecs: spinner ended (timestamp=9653024)
> (xe_drm_fdinfo:10404) DEBUG: ccs: spinner ended (timestamp=9722776)
> (xe_drm_fdinfo:10404) DEBUG: rcs: sample 1: cycles 19513436, total_cycles 130596422980
> (xe_drm_fdinfo:10404) DEBUG: rcs: sample 2: cycles 29331470, total_cycles 130606141449
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   tests/intel/xe_drm_fdinfo.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index e3a99a2dc..074a89711 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -416,6 +416,7 @@ spin_sync_start(int fd, struct spin_ctx *ctx)
>   		return;
>   
>   	ctx->spin_opts.addr = ctx->addr;
> +	ctx->spin_opts.write_timestamp = true;
>   	ctx->spin_opts.preempt = true;
>   	xe_spin_init(ctx->spin, &ctx->spin_opts);
>   
> @@ -448,7 +449,8 @@ spin_sync_end(int fd, struct spin_ctx *ctx)
>   	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>   
>   	ctx->ended = true;
> -	igt_debug("%s: spinner ended\n", engine_map[ctx->class]);
> +	igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
> +		  ctx->spin->timestamp);
>   }
>   
>   static void

[PATCH i-g-t v3 03/10] lib/igt_core: Add igt_assert_lt_double()

[Lucas De Marchi]

Like the for other types. Avoid the lte variant as it's not good
practice to compare a double for equality.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 lib/igt_core.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/lib/igt_core.h b/lib/igt_core.h
index 06c5314bf..84925767c 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -998,6 +998,18 @@ void igt_describe_f(const char *fmt, ...);
  */
 #define igt_assert_lt_s64(n1, n2) igt_assert_cmps64(n1, <, >=, n2)
 
+/**
+ * igt_assert_lt_double:
+ * @n1: first double
+ * @n2: second double
+ *
+ * Fails (sub-)test if the second double is smaller than or equal to the first.
+ *
+ * Like igt_assert(), but displays the values being compared on failure instead
+ * of simply printing the stringified expression.
+ */
+#define igt_assert_lt_double(n1, n2) igt_assert_cmpdouble(n1, <, >=, n2)
+
 /**
  * igt_assert_fd:
  * @fd: file descriptor
-- 
2.43.0

Re: [PATCH i-g-t v3 03/10] lib/igt_core: Add igt_assert_lt_double()

[Nirmoy Das]

On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
> Like the for other types. Avoid the lte variant as it's not good
> practice to compare a double for equality.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   lib/igt_core.h | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/lib/igt_core.h b/lib/igt_core.h
> index 06c5314bf..84925767c 100644
> --- a/lib/igt_core.h
> +++ b/lib/igt_core.h
> @@ -998,6 +998,18 @@ void igt_describe_f(const char *fmt, ...);
>    */
>   #define igt_assert_lt_s64(n1, n2) igt_assert_cmps64(n1, <, >=, n2)
>   
> +/**
> + * igt_assert_lt_double:
> + * @n1: first double
> + * @n2: second double
> + *
> + * Fails (sub-)test if the second double is smaller than or equal to the first.
> + *
> + * Like igt_assert(), but displays the values being compared on failure instead
> + * of simply printing the stringified expression.
> + */
> +#define igt_assert_lt_double(n1, n2) igt_assert_cmpdouble(n1, <, >=, n2)
> +
>   /**
>    * igt_assert_fd:
>    * @fd: file descriptor

[PATCH i-g-t v3 04/10] tests/intel/xe_drm_fdinfo: Use igt_assert_lt_double()

[Lucas De Marchi]

This also shows the value that is failing, which helps debugging.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 074a89711..1b5980752 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -485,10 +485,12 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
 
 	igt_debug("%s: percent: %f\n", engine_map[class], percent);
 
-	if (flags & TEST_BUSY)
-		igt_assert(percent >= 95 && percent <= 105);
-	else
+	if (flags & TEST_BUSY) {
+		igt_assert_lt_double(95.0, percent);
+		igt_assert_lt_double(percent, 105.0);
+	} else {
 		igt_assert(!percent);
+	}
 }
 
 static void
-- 
2.43.0

Re: [PATCH i-g-t v3 04/10] tests/intel/xe_drm_fdinfo: Use igt_assert_lt_double()

[Nirmoy Das]

On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
> This also shows the value that is failing, which helps debugging.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   tests/intel/xe_drm_fdinfo.c | 8 +++++---
>   1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 074a89711..1b5980752 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -485,10 +485,12 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>   
>   	igt_debug("%s: percent: %f\n", engine_map[class], percent);
>   
> -	if (flags & TEST_BUSY)
> -		igt_assert(percent >= 95 && percent <= 105);
> -	else
> +	if (flags & TEST_BUSY) {
> +		igt_assert_lt_double(95.0, percent);
> +		igt_assert_lt_double(percent, 105.0);
> +	} else {
>   		igt_assert(!percent);
> +	}
>   }
>   
>   static void

[PATCH i-g-t v3 05/10] tests/intel/xe_drm_fdinfo: Be strict on == 0 comparison

[Lucas De Marchi]

Do not compare the percent to 0, just make sure there's not a single
tick in those cycles.

v2: separate numerator and denominator calculation and check
    numerator. It's not guaranteed cycles start from 0.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 1b5980752..68c21925c 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -474,14 +474,16 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
 	      int class, unsigned int flags)
 {
 	double percent;
+	u64 den, num;
 
 	igt_debug("%s: sample 1: cycles %lu, total_cycles %lu\n",
 		  engine_map[class], s1[class].cycles, s1[class].total_cycles);
 	igt_debug("%s: sample 2: cycles %lu, total_cycles %lu\n",
 		  engine_map[class], s2[class].cycles, s2[class].total_cycles);
 
-	percent = ((s2[class].cycles - s1[class].cycles) * 100) /
-		  ((s2[class].total_cycles + 1) - s1[class].total_cycles);
+	num = s2[class].cycles - s1[class].cycles;
+	den = s2[class].total_cycles - s1[class].total_cycles;
+	percent = (num * 100.0) / (den + 1);
 
 	igt_debug("%s: percent: %f\n", engine_map[class], percent);
 
@@ -489,7 +491,7 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
 		igt_assert_lt_double(95.0, percent);
 		igt_assert_lt_double(percent, 105.0);
 	} else {
-		igt_assert(!percent);
+		igt_assert_eq(num, 0);
 	}
 }
 
-- 
2.43.0

Re: [PATCH i-g-t v3 05/10] tests/intel/xe_drm_fdinfo: Be strict on == 0 comparison

[Nirmoy Das]

On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
> Do not compare the percent to 0, just make sure there's not a single
> tick in those cycles.
>
> v2: separate numerator and denominator calculation and check
>      numerator. It's not guaranteed cycles start from 0.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   tests/intel/xe_drm_fdinfo.c | 8 +++++---
>   1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 1b5980752..68c21925c 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -474,14 +474,16 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>   	      int class, unsigned int flags)
>   {
>   	double percent;
> +	u64 den, num;
>   
>   	igt_debug("%s: sample 1: cycles %lu, total_cycles %lu\n",
>   		  engine_map[class], s1[class].cycles, s1[class].total_cycles);
>   	igt_debug("%s: sample 2: cycles %lu, total_cycles %lu\n",
>   		  engine_map[class], s2[class].cycles, s2[class].total_cycles);
>   
> -	percent = ((s2[class].cycles - s1[class].cycles) * 100) /
> -		  ((s2[class].total_cycles + 1) - s1[class].total_cycles);
> +	num = s2[class].cycles - s1[class].cycles;
> +	den = s2[class].total_cycles - s1[class].total_cycles;
> +	percent = (num * 100.0) / (den + 1);
>   
>   	igt_debug("%s: percent: %f\n", engine_map[class], percent);
>   
> @@ -489,7 +491,7 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>   		igt_assert_lt_double(95.0, percent);
>   		igt_assert_lt_double(percent, 105.0);
>   	} else {
> -		igt_assert(!percent);
> +		igt_assert_eq(num, 0);
>   	}
>   }
>   

[PATCH i-g-t v3 06/10] tests/intel/xe_drm_fdinfo: Use usec for batch duration

[Lucas De Marchi]

It's only used to control the time to usleep(), so use a better unit.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 68c21925c..9fb739fba 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -73,7 +73,7 @@ struct pceu_cycles {
 	uint64_t total_cycles;
 };
 
-const unsigned long batch_duration_ns = (1 * NSEC_PER_SEC) / 2;
+const unsigned long batch_duration_usec = (1 * USEC_PER_SEC) / 2;
 
 static const char *engine_map[] = {
 	"rcs",
@@ -517,7 +517,7 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
 	if (flags & TEST_ISOLATION)
 		read_engine_cycles(new_fd, pceu1[1]);
 
-	usleep(batch_duration_ns / 1000);
+	usleep(batch_duration_usec);
 	if (flags & TEST_TRAILING_IDLE)
 		spin_sync_end(fd, ctx);
 
@@ -553,7 +553,7 @@ busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int fl
 	}
 
 	read_engine_cycles(fd, pceu1);
-	usleep(batch_duration_ns / 1000);
+	usleep(batch_duration_usec);
 	if (flags & TEST_TRAILING_IDLE)
 		spin_sync_end(fd, ctx);
 	read_engine_cycles(fd, pceu2);
@@ -580,7 +580,7 @@ single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
 	spin_sync_start(fd, ctx);
 
 	read_engine_cycles(fd, pceu1);
-	usleep(batch_duration_ns / 1000);
+	usleep(batch_duration_usec);
 
 	/* destroy queue before sampling again */
 	spin_sync_end(fd, ctx);
@@ -619,7 +619,7 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe,
 	}
 
 	read_engine_cycles(fd, pceu1);
-	usleep(batch_duration_ns / 1000);
+	usleep(batch_duration_usec);
 	if (flags & TEST_TRAILING_IDLE)
 		xe_for_each_engine_class(class)
 			spin_sync_end(fd, ctx[class]);
@@ -663,7 +663,7 @@ all_busy_check_all(int fd, unsigned int flags)
 	}
 
 	read_engine_cycles(fd, pceu1);
-	usleep(batch_duration_ns / 1000);
+	usleep(batch_duration_usec);
 	if (flags & TEST_TRAILING_IDLE)
 		xe_for_each_engine_class(class)
 			spin_sync_end(fd, ctx[class]);
-- 
2.43.0

Re: [PATCH i-g-t v3 06/10] tests/intel/xe_drm_fdinfo: Use usec for batch duration

[Nirmoy Das]

On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
> It's only used to control the time to usleep(), so use a better unit.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   tests/intel/xe_drm_fdinfo.c | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 68c21925c..9fb739fba 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -73,7 +73,7 @@ struct pceu_cycles {
>   	uint64_t total_cycles;
>   };
>   
> -const unsigned long batch_duration_ns = (1 * NSEC_PER_SEC) / 2;
> +const unsigned long batch_duration_usec = (1 * USEC_PER_SEC) / 2;
>   
>   static const char *engine_map[] = {
>   	"rcs",
> @@ -517,7 +517,7 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
>   	if (flags & TEST_ISOLATION)
>   		read_engine_cycles(new_fd, pceu1[1]);
>   
> -	usleep(batch_duration_ns / 1000);
> +	usleep(batch_duration_usec);
>   	if (flags & TEST_TRAILING_IDLE)
>   		spin_sync_end(fd, ctx);
>   
> @@ -553,7 +553,7 @@ busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int fl
>   	}
>   
>   	read_engine_cycles(fd, pceu1);
> -	usleep(batch_duration_ns / 1000);
> +	usleep(batch_duration_usec);
>   	if (flags & TEST_TRAILING_IDLE)
>   		spin_sync_end(fd, ctx);
>   	read_engine_cycles(fd, pceu2);
> @@ -580,7 +580,7 @@ single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
>   	spin_sync_start(fd, ctx);
>   
>   	read_engine_cycles(fd, pceu1);
> -	usleep(batch_duration_ns / 1000);
> +	usleep(batch_duration_usec);
>   
>   	/* destroy queue before sampling again */
>   	spin_sync_end(fd, ctx);
> @@ -619,7 +619,7 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe,
>   	}
>   
>   	read_engine_cycles(fd, pceu1);
> -	usleep(batch_duration_ns / 1000);
> +	usleep(batch_duration_usec);
>   	if (flags & TEST_TRAILING_IDLE)
>   		xe_for_each_engine_class(class)
>   			spin_sync_end(fd, ctx[class]);
> @@ -663,7 +663,7 @@ all_busy_check_all(int fd, unsigned int flags)
>   	}
>   
>   	read_engine_cycles(fd, pceu1);
> -	usleep(batch_duration_ns / 1000);
> +	usleep(batch_duration_usec);
>   	if (flags & TEST_TRAILING_IDLE)
>   		xe_for_each_engine_class(class)
>   			spin_sync_end(fd, ctx[class]);

[PATCH i-g-t v3 07/10] tests/intel/xe_drm_fdinfo: Half the execution time

[Lucas De Marchi]

No need to do 500 msec per subtest. As we add more tests, the total
execution time of ~ 2.5 sec per subtest make it take too long. Sleep
half the time to lower the execution time.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 9fb739fba..46c96dbe0 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -73,7 +73,7 @@ struct pceu_cycles {
 	uint64_t total_cycles;
 };
 
-const unsigned long batch_duration_usec = (1 * USEC_PER_SEC) / 2;
+const unsigned long batch_duration_usec = (1 * USEC_PER_SEC) / 4;
 
 static const char *engine_map[] = {
 	"rcs",
-- 
2.43.0

Re: [PATCH i-g-t v3 07/10] tests/intel/xe_drm_fdinfo: Half the execution time

[Nirmoy Das]

On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
> No need to do 500 msec per subtest. As we add more tests, the total
> execution time of ~ 2.5 sec per subtest make it take too long. Sleep
> half the time to lower the execution time.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   tests/intel/xe_drm_fdinfo.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 9fb739fba..46c96dbe0 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -73,7 +73,7 @@ struct pceu_cycles {
>   	uint64_t total_cycles;
>   };
>   
> -const unsigned long batch_duration_usec = (1 * USEC_PER_SEC) / 2;
> +const unsigned long batch_duration_usec = (1 * USEC_PER_SEC) / 4;
>   
>   static const char *engine_map[] = {
>   	"rcs",

[PATCH i-g-t v3 08/10] tests/intel/xe_drm_fdinfo: Remove unused flags

[Lucas De Marchi]

single() is the only test function that is used by multiple kinds of
tests and controlled by flags. The others simply pass the same flags
every time. Simplify the tests by removing the bogus checks.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 81 +++++++++++++++++--------------------
 1 file changed, 38 insertions(+), 43 deletions(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 46c96dbe0..23edeea40 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -538,7 +538,7 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
 }
 
 static void
-busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
+busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
@@ -547,20 +547,20 @@ busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int fl
 	int class;
 
 	vm = xe_vm_create(fd, 0, 0);
-	if (flags & TEST_BUSY) {
-		ctx = spin_ctx_init(fd, hwe, vm);
-		spin_sync_start(fd, ctx);
-	}
+
+	ctx = spin_ctx_init(fd, hwe, vm);
+	spin_sync_start(fd, ctx);
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
-	if (flags & TEST_TRAILING_IDLE)
-		spin_sync_end(fd, ctx);
+	spin_sync_end(fd, ctx);
 	read_engine_cycles(fd, pceu2);
 
-	xe_for_each_engine_class(class)
-		check_results(pceu1, pceu2, class,
-			      hwe->engine_class == class ? flags : 0);
+	xe_for_each_engine_class(class) {
+		bool idle = hwe->engine_class != class;
+
+		check_results(pceu1, pceu2, class, idle ? 0 : TEST_BUSY);
+	}
 
 	spin_sync_end(fd, ctx);
 	spin_ctx_destroy(fd, ctx);
@@ -594,8 +594,7 @@ single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
 }
 
 static void
-most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe,
-		    unsigned int flags)
+most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
@@ -605,32 +604,31 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe,
 	int class;
 
 	vm = xe_vm_create(fd, 0, 0);
-	if (flags & TEST_BUSY) {
-		/* spin on one hwe per class except the target class hwes */
-		xe_for_each_engine(fd, _hwe) {
-			int _class = _hwe->engine_class;
 
-			if (_class == hwe->engine_class || ctx[_class])
-				continue;
+	/* spin on one hwe per class except the target class hwes */
+	xe_for_each_engine(fd, _hwe) {
+		int _class = _hwe->engine_class;
 
-			ctx[_class] = spin_ctx_init(fd, _hwe, vm);
-			spin_sync_start(fd, ctx[_class]);
-		}
+		if (_class == hwe->engine_class || ctx[_class])
+			continue;
+
+		ctx[_class] = spin_ctx_init(fd, _hwe, vm);
+		spin_sync_start(fd, ctx[_class]);
 	}
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
-	if (flags & TEST_TRAILING_IDLE)
-		xe_for_each_engine_class(class)
-			spin_sync_end(fd, ctx[class]);
+	xe_for_each_engine_class(class)
+		spin_sync_end(fd, ctx[class]);
 	read_engine_cycles(fd, pceu2);
 
 	xe_for_each_engine_class(class) {
+		bool idle = hwe->engine_class == class;
+
 		if (!ctx[class])
 			continue;
 
-		check_results(pceu1, pceu2, class,
-			      hwe->engine_class == class ? 0 : flags);
+		check_results(pceu1, pceu2, class, idle ? 0 : TEST_BUSY);
 		spin_sync_end(fd, ctx[class]);
 		spin_ctx_destroy(fd, ctx[class]);
 	}
@@ -639,7 +637,7 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe,
 }
 
 static void
-all_busy_check_all(int fd, unsigned int flags)
+all_busy_check_all(int fd)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
@@ -649,31 +647,28 @@ all_busy_check_all(int fd, unsigned int flags)
 	int class;
 
 	vm = xe_vm_create(fd, 0, 0);
-	if (flags & TEST_BUSY) {
-		/* spin on one hwe per class */
-		xe_for_each_engine(fd, hwe) {
-			class = hwe->engine_class;
 
-			if (ctx[class])
-				continue;
+	/* spin on one hwe per class */
+	xe_for_each_engine(fd, hwe) {
+		class = hwe->engine_class;
+		if (ctx[class])
+			continue;
 
-			ctx[class] = spin_ctx_init(fd, hwe, vm);
-			spin_sync_start(fd, ctx[class]);
-		}
+		ctx[class] = spin_ctx_init(fd, hwe, vm);
+		spin_sync_start(fd, ctx[class]);
 	}
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
-	if (flags & TEST_TRAILING_IDLE)
-		xe_for_each_engine_class(class)
-			spin_sync_end(fd, ctx[class]);
+	xe_for_each_engine_class(class)
+		spin_sync_end(fd, ctx[class]);
 	read_engine_cycles(fd, pceu2);
 
 	xe_for_each_engine_class(class) {
 		if (!ctx[class])
 			continue;
 
-		check_results(pceu1, pceu2, class, flags);
+		check_results(pceu1, pceu2, class, TEST_BUSY);
 		spin_sync_end(fd, ctx[class]);
 		spin_ctx_destroy(fd, ctx[class]);
 	}
@@ -715,14 +710,14 @@ igt_main
 
 	igt_subtest("drm-busy-idle-check-all")
 		xe_for_each_engine(xe, hwe)
-			busy_check_all(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE);
+			busy_check_all(xe, hwe);
 
 	igt_subtest("drm-most-busy-idle-check-all")
 		xe_for_each_engine(xe, hwe)
-			most_busy_check_all(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE);
+			most_busy_check_all(xe, hwe);
 
 	igt_subtest("drm-all-busy-idle-check-all")
-		all_busy_check_all(xe, TEST_BUSY | TEST_TRAILING_IDLE);
+		all_busy_check_all(xe);
 
 	igt_subtest("drm-busy-exec-queue-destroy-idle")
 		xe_for_each_engine(xe, hwe)
-- 
2.43.0

Re: [PATCH i-g-t v3 08/10] tests/intel/xe_drm_fdinfo: Remove unused flags

[Nirmoy Das]

On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
> single() is the only test function that is used by multiple kinds of
> tests and controlled by flags. The others simply pass the same flags
> every time. Simplify the tests by removing the bogus checks.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   tests/intel/xe_drm_fdinfo.c | 81 +++++++++++++++++--------------------
>   1 file changed, 38 insertions(+), 43 deletions(-)
>
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 46c96dbe0..23edeea40 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -538,7 +538,7 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
>   }
>   
>   static void
> -busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
> +busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
>   {
>   	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> @@ -547,20 +547,20 @@ busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int fl
>   	int class;
>   
>   	vm = xe_vm_create(fd, 0, 0);
> -	if (flags & TEST_BUSY) {
> -		ctx = spin_ctx_init(fd, hwe, vm);
> -		spin_sync_start(fd, ctx);
> -	}
> +
> +	ctx = spin_ctx_init(fd, hwe, vm);
> +	spin_sync_start(fd, ctx);
>   
>   	read_engine_cycles(fd, pceu1);
>   	usleep(batch_duration_usec);
> -	if (flags & TEST_TRAILING_IDLE)
> -		spin_sync_end(fd, ctx);
> +	spin_sync_end(fd, ctx);
>   	read_engine_cycles(fd, pceu2);
>   
> -	xe_for_each_engine_class(class)
> -		check_results(pceu1, pceu2, class,
> -			      hwe->engine_class == class ? flags : 0);
> +	xe_for_each_engine_class(class) {
> +		bool idle = hwe->engine_class != class;
> +
> +		check_results(pceu1, pceu2, class, idle ? 0 : TEST_BUSY);
> +	}
>   
>   	spin_sync_end(fd, ctx);
>   	spin_ctx_destroy(fd, ctx);
> @@ -594,8 +594,7 @@ single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
>   }
>   
>   static void
> -most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe,
> -		    unsigned int flags)
> +most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
>   {
>   	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> @@ -605,32 +604,31 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe,
>   	int class;
>   
>   	vm = xe_vm_create(fd, 0, 0);
> -	if (flags & TEST_BUSY) {
> -		/* spin on one hwe per class except the target class hwes */
> -		xe_for_each_engine(fd, _hwe) {
> -			int _class = _hwe->engine_class;
>   
> -			if (_class == hwe->engine_class || ctx[_class])
> -				continue;
> +	/* spin on one hwe per class except the target class hwes */
> +	xe_for_each_engine(fd, _hwe) {
> +		int _class = _hwe->engine_class;
>   
> -			ctx[_class] = spin_ctx_init(fd, _hwe, vm);
> -			spin_sync_start(fd, ctx[_class]);
> -		}
> +		if (_class == hwe->engine_class || ctx[_class])
> +			continue;
> +
> +		ctx[_class] = spin_ctx_init(fd, _hwe, vm);
> +		spin_sync_start(fd, ctx[_class]);
>   	}
>   
>   	read_engine_cycles(fd, pceu1);
>   	usleep(batch_duration_usec);
> -	if (flags & TEST_TRAILING_IDLE)
> -		xe_for_each_engine_class(class)
> -			spin_sync_end(fd, ctx[class]);
> +	xe_for_each_engine_class(class)
> +		spin_sync_end(fd, ctx[class]);
>   	read_engine_cycles(fd, pceu2);
>   
>   	xe_for_each_engine_class(class) {
> +		bool idle = hwe->engine_class == class;
> +
>   		if (!ctx[class])
>   			continue;
>   
> -		check_results(pceu1, pceu2, class,
> -			      hwe->engine_class == class ? 0 : flags);
> +		check_results(pceu1, pceu2, class, idle ? 0 : TEST_BUSY);
>   		spin_sync_end(fd, ctx[class]);
>   		spin_ctx_destroy(fd, ctx[class]);
>   	}
> @@ -639,7 +637,7 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe,
>   }
>   
>   static void
> -all_busy_check_all(int fd, unsigned int flags)
> +all_busy_check_all(int fd)
>   {
>   	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> @@ -649,31 +647,28 @@ all_busy_check_all(int fd, unsigned int flags)
>   	int class;
>   
>   	vm = xe_vm_create(fd, 0, 0);
> -	if (flags & TEST_BUSY) {
> -		/* spin on one hwe per class */
> -		xe_for_each_engine(fd, hwe) {
> -			class = hwe->engine_class;
>   
> -			if (ctx[class])
> -				continue;
> +	/* spin on one hwe per class */
> +	xe_for_each_engine(fd, hwe) {
> +		class = hwe->engine_class;
> +		if (ctx[class])
> +			continue;
>   
> -			ctx[class] = spin_ctx_init(fd, hwe, vm);
> -			spin_sync_start(fd, ctx[class]);
> -		}
> +		ctx[class] = spin_ctx_init(fd, hwe, vm);
> +		spin_sync_start(fd, ctx[class]);
>   	}
>   
>   	read_engine_cycles(fd, pceu1);
>   	usleep(batch_duration_usec);
> -	if (flags & TEST_TRAILING_IDLE)
> -		xe_for_each_engine_class(class)
> -			spin_sync_end(fd, ctx[class]);
> +	xe_for_each_engine_class(class)
> +		spin_sync_end(fd, ctx[class]);
>   	read_engine_cycles(fd, pceu2);
>   
>   	xe_for_each_engine_class(class) {
>   		if (!ctx[class])
>   			continue;
>   
> -		check_results(pceu1, pceu2, class, flags);
> +		check_results(pceu1, pceu2, class, TEST_BUSY);
>   		spin_sync_end(fd, ctx[class]);
>   		spin_ctx_destroy(fd, ctx[class]);
>   	}
> @@ -715,14 +710,14 @@ igt_main
>   
>   	igt_subtest("drm-busy-idle-check-all")
>   		xe_for_each_engine(xe, hwe)
> -			busy_check_all(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE);
> +			busy_check_all(xe, hwe);
>   
>   	igt_subtest("drm-most-busy-idle-check-all")
>   		xe_for_each_engine(xe, hwe)
> -			most_busy_check_all(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE);
> +			most_busy_check_all(xe, hwe);
>   
>   	igt_subtest("drm-all-busy-idle-check-all")
> -		all_busy_check_all(xe, TEST_BUSY | TEST_TRAILING_IDLE);
> +		all_busy_check_all(xe);
>   
>   	igt_subtest("drm-busy-exec-queue-destroy-idle")
>   		xe_for_each_engine(xe, hwe)

[PATCH i-g-t v3 09/10] tests/intel/xe_drm_fdinfo: Use enum with expected load

[Lucas De Marchi]

Do not let the execution flag dictate the result check, but rather be
explicit what's being checked: idle or full load.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 45 +++++++++++++++++++++++++++----------
 1 file changed, 33 insertions(+), 12 deletions(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 23edeea40..d45e45c6b 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -68,6 +68,11 @@ IGT_TEST_DESCRIPTION("Read and verify drm client memory consumption and engine u
 #define TEST_TRAILING_IDLE	(1 << 1)
 #define TEST_ISOLATION		(1 << 2)
 
+enum expected_load {
+	EXPECTED_LOAD_IDLE,
+	EXPECTED_LOAD_FULL,
+};
+
 struct pceu_cycles {
 	uint64_t cycles;
 	uint64_t total_cycles;
@@ -471,7 +476,7 @@ spin_ctx_destroy(int fd, struct spin_ctx *ctx)
 
 static void
 check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
-	      int class, unsigned int flags)
+	      int class, enum expected_load expected_load)
 {
 	double percent;
 	u64 den, num;
@@ -487,11 +492,18 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
 
 	igt_debug("%s: percent: %f\n", engine_map[class], percent);
 
-	if (flags & TEST_BUSY) {
+	switch (expected_load) {
+	case EXPECTED_LOAD_IDLE:
+		igt_assert_eq(num, 0);
+		break;
+	case EXPECTED_LOAD_FULL:
+		/*
+		 * We are still relying on CPU sleep time and there could be
+		 * some imprecision when calculating the load. Use a 5% margin.
+		 */
 		igt_assert_lt_double(95.0, percent);
 		igt_assert_lt_double(percent, 105.0);
-	} else {
-		igt_assert_eq(num, 0);
+		break;
 	}
 }
 
@@ -501,6 +513,7 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
 	struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct spin_ctx *ctx = NULL;
+	enum expected_load expected_load;
 	uint32_t vm;
 	int new_fd;
 
@@ -525,10 +538,16 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
 	if (flags & TEST_ISOLATION)
 		read_engine_cycles(new_fd, pceu2[1]);
 
-	check_results(pceu1[0], pceu2[0], hwe->engine_class, flags);
+	expected_load = flags & TEST_BUSY ?
+	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
+	check_results(pceu1[0], pceu2[0], hwe->engine_class, expected_load);
 
 	if (flags & TEST_ISOLATION) {
-		check_results(pceu1[1], pceu2[1], hwe->engine_class, 0);
+		/*
+		 * Load from one client shouldn't spill on another,
+		 * so check for idle
+		 */
+		check_results(pceu1[1], pceu2[1], hwe->engine_class, EXPECTED_LOAD_IDLE);
 		close(new_fd);
 	}
 
@@ -557,9 +576,10 @@ busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
 	read_engine_cycles(fd, pceu2);
 
 	xe_for_each_engine_class(class) {
-		bool idle = hwe->engine_class != class;
+		enum expected_load expected_load = hwe->engine_class != class ?
+			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
 
-		check_results(pceu1, pceu2, class, idle ? 0 : TEST_BUSY);
+		check_results(pceu1, pceu2, class, expected_load);
 	}
 
 	spin_sync_end(fd, ctx);
@@ -590,7 +610,7 @@ single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
 
 	xe_vm_destroy(fd, vm);
 
-	check_results(pceu1, pceu2, hwe->engine_class, TEST_BUSY);
+	check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
 }
 
 static void
@@ -623,12 +643,13 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
 	read_engine_cycles(fd, pceu2);
 
 	xe_for_each_engine_class(class) {
-		bool idle = hwe->engine_class == class;
+		enum expected_load expected_load = hwe->engine_class == class ?
+			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
 
 		if (!ctx[class])
 			continue;
 
-		check_results(pceu1, pceu2, class, idle ? 0 : TEST_BUSY);
+		check_results(pceu1, pceu2, class, expected_load);
 		spin_sync_end(fd, ctx[class]);
 		spin_ctx_destroy(fd, ctx[class]);
 	}
@@ -668,7 +689,7 @@ all_busy_check_all(int fd)
 		if (!ctx[class])
 			continue;
 
-		check_results(pceu1, pceu2, class, TEST_BUSY);
+		check_results(pceu1, pceu2, class, EXPECTED_LOAD_FULL);
 		spin_sync_end(fd, ctx[class]);
 		spin_ctx_destroy(fd, ctx[class]);
 	}
-- 
2.43.0

Re: [PATCH i-g-t v3 09/10] tests/intel/xe_drm_fdinfo: Use enum with expected load

[Nirmoy Das]

On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
> Do not let the execution flag dictate the result check, but rather be
> explicit what's being checked: idle or full load.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Nirmoy Das<nirmoy.das@intel.com>

> ---
>   tests/intel/xe_drm_fdinfo.c | 45 +++++++++++++++++++++++++++----------
>   1 file changed, 33 insertions(+), 12 deletions(-)
>
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 23edeea40..d45e45c6b 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -68,6 +68,11 @@ IGT_TEST_DESCRIPTION("Read and verify drm client memory consumption and engine u
>   #define TEST_TRAILING_IDLE	(1 << 1)
>   #define TEST_ISOLATION		(1 << 2)
>   
> +enum expected_load {
> +	EXPECTED_LOAD_IDLE,
> +	EXPECTED_LOAD_FULL,
> +};
> +
>   struct pceu_cycles {
>   	uint64_t cycles;
>   	uint64_t total_cycles;
> @@ -471,7 +476,7 @@ spin_ctx_destroy(int fd, struct spin_ctx *ctx)
>   
>   static void
>   check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> -	      int class, unsigned int flags)
> +	      int class, enum expected_load expected_load)
>   {
>   	double percent;
>   	u64 den, num;
> @@ -487,11 +492,18 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>   
>   	igt_debug("%s: percent: %f\n", engine_map[class], percent);
>   
> -	if (flags & TEST_BUSY) {
> +	switch (expected_load) {
> +	case EXPECTED_LOAD_IDLE:
> +		igt_assert_eq(num, 0);
> +		break;
> +	case EXPECTED_LOAD_FULL:
> +		/*
> +		 * We are still relying on CPU sleep time and there could be
> +		 * some imprecision when calculating the load. Use a 5% margin.
> +		 */
>   		igt_assert_lt_double(95.0, percent);
>   		igt_assert_lt_double(percent, 105.0);
> -	} else {
> -		igt_assert_eq(num, 0);
> +		break;
>   	}
>   }
>   
> @@ -501,6 +513,7 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
>   	struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct spin_ctx *ctx = NULL;
> +	enum expected_load expected_load;
>   	uint32_t vm;
>   	int new_fd;
>   
> @@ -525,10 +538,16 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
>   	if (flags & TEST_ISOLATION)
>   		read_engine_cycles(new_fd, pceu2[1]);
>   
> -	check_results(pceu1[0], pceu2[0], hwe->engine_class, flags);
> +	expected_load = flags & TEST_BUSY ?
> +	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
> +	check_results(pceu1[0], pceu2[0], hwe->engine_class, expected_load);
>   
>   	if (flags & TEST_ISOLATION) {
> -		check_results(pceu1[1], pceu2[1], hwe->engine_class, 0);
> +		/*
> +		 * Load from one client shouldn't spill on another,
> +		 * so check for idle
> +		 */
> +		check_results(pceu1[1], pceu2[1], hwe->engine_class, EXPECTED_LOAD_IDLE);
>   		close(new_fd);
>   	}
>   
> @@ -557,9 +576,10 @@ busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
>   	read_engine_cycles(fd, pceu2);
>   
>   	xe_for_each_engine_class(class) {
> -		bool idle = hwe->engine_class != class;
> +		enum expected_load expected_load = hwe->engine_class != class ?
> +			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
>   
> -		check_results(pceu1, pceu2, class, idle ? 0 : TEST_BUSY);
> +		check_results(pceu1, pceu2, class, expected_load);
>   	}
>   
>   	spin_sync_end(fd, ctx);
> @@ -590,7 +610,7 @@ single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
>   
>   	xe_vm_destroy(fd, vm);
>   
> -	check_results(pceu1, pceu2, hwe->engine_class, TEST_BUSY);
> +	check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
>   }
>   
>   static void
> @@ -623,12 +643,13 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
>   	read_engine_cycles(fd, pceu2);
>   
>   	xe_for_each_engine_class(class) {
> -		bool idle = hwe->engine_class == class;
> +		enum expected_load expected_load = hwe->engine_class == class ?
> +			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
>   
>   		if (!ctx[class])
>   			continue;
>   
> -		check_results(pceu1, pceu2, class, idle ? 0 : TEST_BUSY);
> +		check_results(pceu1, pceu2, class, expected_load);
>   		spin_sync_end(fd, ctx[class]);
>   		spin_ctx_destroy(fd, ctx[class]);
>   	}
> @@ -668,7 +689,7 @@ all_busy_check_all(int fd)
>   		if (!ctx[class])
>   			continue;
>   
> -		check_results(pceu1, pceu2, class, TEST_BUSY);
> +		check_results(pceu1, pceu2, class, EXPECTED_LOAD_FULL);
>   		spin_sync_end(fd, ctx[class]);
>   		spin_ctx_destroy(fd, ctx[class]);
>   	}

[PATCH i-g-t v3 10/10] tests/intel/xe_drm_fdinfo: Rename and reorder tests

[Lucas De Marchi]

There are 2 main categories of tests in xe_drm_fdinfo:
mem and utilization. Group and name tests accordingly.

For utilization, create subgroups: "single", "others" and "all",
with variants on each of them.

No change in behavior on each tests, it's just rename and reorder.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 148 ++++++++++++++++++------------------
 1 file changed, 74 insertions(+), 74 deletions(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index d45e45c6b..d1ed0fcaa 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -22,41 +22,41 @@
  * Feature: SMI, core
  * Test category: SysMan
  *
- * SUBTEST: basic-memory
+ * SUBTEST: basic-mem
  * Description: Check if basic fdinfo content is present for memory
  *
- * SUBTEST: basic-engine-utilization
+ * SUBTEST: basic-utilization
  * Description: Check if basic fdinfo content is present for engine utilization
  *
- * SUBTEST: drm-idle
- * Description: Check that engines show no load when idle
+ * SUBTEST: mem-total-resident
+ * Description: Create and compare total and resident memory consumption by client
  *
- * SUBTEST: drm-busy-idle
- * Description: Check that engines show load when idle after busy
+ * SUBTEST: mem-shared
+ * Description: Create and compare shared memory consumption by client
  *
- * SUBTEST: drm-busy-idle-isolation
- * Description: Check that engine load does not spill over to other drm clients
+ * SUBTEST: mem-active
+ * Description: Create and compare active memory consumption by client
  *
- * SUBTEST: drm-busy-idle-check-all
- * Description: Check that only the target engine shows load when idle after busy
+ * SUBTEST: utilization-single-idle
+ * Description: Check that each engine shows no load
  *
- * SUBTEST: drm-most-busy-idle-check-all
- * Description: Check that only the target engine shows idle and all others are busy
+ * SUBTEST: utilization-single-full-load
+ * Description: Check that each engine shows full load
  *
- * SUBTEST: drm-all-busy-idle-check-all
- * Description: Check that all engines show busy when all are loaded
+ * SUBTEST: utilization-single-full-load-isolation
+ * Description: Check that each engine load does not spill over to other drm clients
  *
- * SUBTEST: drm-busy-exec-queue-destroy-idle
+ * SUBTEST: utilization-single-full-load-destroy-queue
  * Description: Destroy exec queue before idle and ensure load is accurate
  *
- * SUBTEST: drm-total-resident
- * Description: Create and compare total and resident memory consumption by client
+ * SUBTEST: utilization-others-idle
+ * Description: Check that only the target engine shows load
  *
- * SUBTEST: drm-shared
- * Description: Create and compare shared memory consumption by client
+ * SUBTEST: utilization-others-full-load
+ * Description: Check that only the target engine shows idle and all others are busy
  *
- * SUBTEST: drm-active
- * Description: Create and compare active memory consumption by client
+ * SUBTEST: utilization-all-full-load
+ * Description: Check that all engines show busy when all are loaded
  */
 
 IGT_TEST_DESCRIPTION("Read and verify drm client memory consumption and engine utilization using fdinfo");
@@ -104,7 +104,7 @@ static void read_engine_cycles(int xe, struct pceu_cycles *pceu)
 }
 
 /* Subtests */
-static void test_active(int fd, struct drm_xe_engine *engine)
+static void mem_active(int fd, struct drm_xe_engine *engine)
 {
 	struct drm_xe_mem_region *memregion;
 	uint64_t memreg = all_memory_regions(fd), region;
@@ -230,7 +230,7 @@ static void test_active(int fd, struct drm_xe_engine *engine)
 	xe_vm_destroy(fd, vm);
 }
 
-static void test_shared(int xe)
+static void mem_shared(int xe)
 {
 	struct drm_xe_mem_region *memregion;
 	uint64_t memreg = all_memory_regions(xe), region;
@@ -275,7 +275,7 @@ static void test_shared(int xe)
 	}
 }
 
-static void test_total_resident(int xe)
+static void mem_total_resident(int xe)
 {
 	struct drm_xe_mem_region *memregion;
 	uint64_t memreg = all_memory_regions(xe), region;
@@ -508,7 +508,7 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
 }
 
 static void
-single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
+utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
 {
 	struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
@@ -557,64 +557,64 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
 }
 
 static void
-busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
+utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct spin_ctx *ctx = NULL;
 	uint32_t vm;
-	int class;
 
 	vm = xe_vm_create(fd, 0, 0);
-
 	ctx = spin_ctx_init(fd, hwe, vm);
 	spin_sync_start(fd, ctx);
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
-	spin_sync_end(fd, ctx);
-	read_engine_cycles(fd, pceu2);
-
-	xe_for_each_engine_class(class) {
-		enum expected_load expected_load = hwe->engine_class != class ?
-			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
-
-		check_results(pceu1, pceu2, class, expected_load);
-	}
 
+	/* destroy queue before sampling again */
 	spin_sync_end(fd, ctx);
 	spin_ctx_destroy(fd, ctx);
+
+	read_engine_cycles(fd, pceu2);
+
 	xe_vm_destroy(fd, vm);
+
+	check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
 }
 
 static void
-single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
+utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct spin_ctx *ctx = NULL;
 	uint32_t vm;
+	int class;
 
 	vm = xe_vm_create(fd, 0, 0);
+
 	ctx = spin_ctx_init(fd, hwe, vm);
 	spin_sync_start(fd, ctx);
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
-
-	/* destroy queue before sampling again */
 	spin_sync_end(fd, ctx);
-	spin_ctx_destroy(fd, ctx);
-
 	read_engine_cycles(fd, pceu2);
 
-	xe_vm_destroy(fd, vm);
+	xe_for_each_engine_class(class) {
+		enum expected_load expected_load = hwe->engine_class != class ?
+			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
 
-	check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
+		check_results(pceu1, pceu2, class, expected_load);
+	}
+
+	spin_sync_end(fd, ctx);
+	spin_ctx_destroy(fd, ctx);
+	xe_vm_destroy(fd, vm);
 }
 
 static void
-most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
+utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
@@ -658,7 +658,7 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
 }
 
 static void
-all_busy_check_all(int fd)
+utilization_all_full_load(int fd)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
@@ -710,51 +710,51 @@ igt_main
 	}
 
 	igt_describe("Check if basic fdinfo content is present for memory");
-	igt_subtest("basic-memory")
+	igt_subtest("basic-mem")
 		basic_memory(xe);
 
 	igt_describe("Check if basic fdinfo content is present for engine utilization");
-	igt_subtest("basic-engine-utilization")
+	igt_subtest("basic-utilization")
 		basic_engine_utilization(xe);
 
-	igt_subtest("drm-idle")
-		xe_for_each_engine(xe, hwe)
-			single(xe, hwe, 0);
+	igt_describe("Create and compare total and resident memory consumption by client");
+	igt_subtest("mem-total-resident")
+		mem_total_resident(xe);
 
-	igt_subtest("drm-busy-idle")
-		xe_for_each_engine(xe, hwe)
-			single(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE);
+	igt_describe("Create and compare shared memory consumption by client");
+	igt_subtest("mem-shared")
+		mem_shared(xe);
 
-	igt_subtest("drm-busy-idle-isolation")
-		xe_for_each_engine(xe, hwe)
-			single(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE | TEST_ISOLATION);
+	igt_describe("Create and compare active memory consumption by client");
+	igt_subtest("mem-active")
+		mem_active(xe, xe_engine(xe, 0));
 
-	igt_subtest("drm-busy-idle-check-all")
+	igt_subtest("utilization-single-idle")
 		xe_for_each_engine(xe, hwe)
-			busy_check_all(xe, hwe);
+			utilization_single(xe, hwe, 0);
 
-	igt_subtest("drm-most-busy-idle-check-all")
+	igt_subtest("utilization-single-full-load")
 		xe_for_each_engine(xe, hwe)
-			most_busy_check_all(xe, hwe);
+			utilization_single(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE);
 
-	igt_subtest("drm-all-busy-idle-check-all")
-		all_busy_check_all(xe);
+	igt_subtest("utilization-single-full-load-isolation")
+		xe_for_each_engine(xe, hwe)
+			utilization_single(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE | TEST_ISOLATION);
 
-	igt_subtest("drm-busy-exec-queue-destroy-idle")
+	igt_subtest("utilization-single-full-load-destroy-queue")
 		xe_for_each_engine(xe, hwe)
-			single_destroy_queue(xe, hwe);
+			utilization_single_destroy_queue(xe, hwe);
 
-	igt_describe("Create and compare total and resident memory consumption by client");
-	igt_subtest("drm-total-resident")
-		test_total_resident(xe);
+	igt_subtest("utilization-others-idle")
+		xe_for_each_engine(xe, hwe)
+			utilization_others_idle(xe, hwe);
 
-	igt_describe("Create and compare shared memory consumption by client");
-	igt_subtest("drm-shared")
-		test_shared(xe);
+	igt_subtest("utilization-others-full-load")
+		xe_for_each_engine(xe, hwe)
+			utilization_others_full_load(xe, hwe);
 
-	igt_describe("Create and compare active memory consumption by client");
-	igt_subtest("drm-active")
-		test_active(xe, xe_engine(xe, 0));
+	igt_subtest("utilization-all-full-load")
+		utilization_all_full_load(xe);
 
 	igt_fixture {
 		drm_close_driver(xe);
-- 
2.43.0

Re: [PATCH i-g-t v3 10/10] tests/intel/xe_drm_fdinfo: Rename and reorder tests

[Nirmoy Das]

On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
> There are 2 main categories of tests in xe_drm_fdinfo:
> mem and utilization. Group and name tests accordingly.
>
> For utilization, create subgroups: "single", "others" and "all",
> with variants on each of them.
>
> No change in behavior on each tests, it's just rename and reorder.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   tests/intel/xe_drm_fdinfo.c | 148 ++++++++++++++++++------------------
>   1 file changed, 74 insertions(+), 74 deletions(-)
>
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index d45e45c6b..d1ed0fcaa 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -22,41 +22,41 @@
>    * Feature: SMI, core
>    * Test category: SysMan
>    *
> - * SUBTEST: basic-memory
> + * SUBTEST: basic-mem
>    * Description: Check if basic fdinfo content is present for memory
>    *
> - * SUBTEST: basic-engine-utilization
> + * SUBTEST: basic-utilization
>    * Description: Check if basic fdinfo content is present for engine utilization
>    *
> - * SUBTEST: drm-idle
> - * Description: Check that engines show no load when idle
> + * SUBTEST: mem-total-resident
> + * Description: Create and compare total and resident memory consumption by client
>    *
> - * SUBTEST: drm-busy-idle
> - * Description: Check that engines show load when idle after busy
> + * SUBTEST: mem-shared
> + * Description: Create and compare shared memory consumption by client
>    *
> - * SUBTEST: drm-busy-idle-isolation
> - * Description: Check that engine load does not spill over to other drm clients
> + * SUBTEST: mem-active
> + * Description: Create and compare active memory consumption by client
>    *
> - * SUBTEST: drm-busy-idle-check-all
> - * Description: Check that only the target engine shows load when idle after busy
> + * SUBTEST: utilization-single-idle
> + * Description: Check that each engine shows no load
>    *
> - * SUBTEST: drm-most-busy-idle-check-all
> - * Description: Check that only the target engine shows idle and all others are busy
> + * SUBTEST: utilization-single-full-load
> + * Description: Check that each engine shows full load
>    *
> - * SUBTEST: drm-all-busy-idle-check-all
> - * Description: Check that all engines show busy when all are loaded
> + * SUBTEST: utilization-single-full-load-isolation
> + * Description: Check that each engine load does not spill over to other drm clients
>    *
> - * SUBTEST: drm-busy-exec-queue-destroy-idle
> + * SUBTEST: utilization-single-full-load-destroy-queue
>    * Description: Destroy exec queue before idle and ensure load is accurate
>    *
> - * SUBTEST: drm-total-resident
> - * Description: Create and compare total and resident memory consumption by client
> + * SUBTEST: utilization-others-idle
> + * Description: Check that only the target engine shows load
>    *
> - * SUBTEST: drm-shared
> - * Description: Create and compare shared memory consumption by client
> + * SUBTEST: utilization-others-full-load
> + * Description: Check that only the target engine shows idle and all others are busy
>    *
> - * SUBTEST: drm-active
> - * Description: Create and compare active memory consumption by client
> + * SUBTEST: utilization-all-full-load
> + * Description: Check that all engines show busy when all are loaded
>    */
>   
>   IGT_TEST_DESCRIPTION("Read and verify drm client memory consumption and engine utilization using fdinfo");
> @@ -104,7 +104,7 @@ static void read_engine_cycles(int xe, struct pceu_cycles *pceu)
>   }
>   
>   /* Subtests */
> -static void test_active(int fd, struct drm_xe_engine *engine)
> +static void mem_active(int fd, struct drm_xe_engine *engine)
>   {
>   	struct drm_xe_mem_region *memregion;
>   	uint64_t memreg = all_memory_regions(fd), region;
> @@ -230,7 +230,7 @@ static void test_active(int fd, struct drm_xe_engine *engine)
>   	xe_vm_destroy(fd, vm);
>   }
>   
> -static void test_shared(int xe)
> +static void mem_shared(int xe)
>   {
>   	struct drm_xe_mem_region *memregion;
>   	uint64_t memreg = all_memory_regions(xe), region;
> @@ -275,7 +275,7 @@ static void test_shared(int xe)
>   	}
>   }
>   
> -static void test_total_resident(int xe)
> +static void mem_total_resident(int xe)
>   {
>   	struct drm_xe_mem_region *memregion;
>   	uint64_t memreg = all_memory_regions(xe), region;
> @@ -508,7 +508,7 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>   }
>   
>   static void
> -single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
> +utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
>   {
>   	struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> @@ -557,64 +557,64 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags)
>   }
>   
>   static void
> -busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
> +utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
>   {
>   	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct spin_ctx *ctx = NULL;
>   	uint32_t vm;
> -	int class;
>   
>   	vm = xe_vm_create(fd, 0, 0);
> -
>   	ctx = spin_ctx_init(fd, hwe, vm);
>   	spin_sync_start(fd, ctx);
>   
>   	read_engine_cycles(fd, pceu1);
>   	usleep(batch_duration_usec);
> -	spin_sync_end(fd, ctx);
> -	read_engine_cycles(fd, pceu2);
> -
> -	xe_for_each_engine_class(class) {
> -		enum expected_load expected_load = hwe->engine_class != class ?
> -			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
> -
> -		check_results(pceu1, pceu2, class, expected_load);
> -	}
>   
> +	/* destroy queue before sampling again */


Wouldn't this change the behavior ?


Regards,

Nirmoy

>   	spin_sync_end(fd, ctx);
>   	spin_ctx_destroy(fd, ctx);
> +
> +	read_engine_cycles(fd, pceu2);
> +
>   	xe_vm_destroy(fd, vm);
> +
> +	check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
>   }
>   
>   static void
> -single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
> +utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>   {
>   	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct spin_ctx *ctx = NULL;
>   	uint32_t vm;
> +	int class;
>   
>   	vm = xe_vm_create(fd, 0, 0);
> +
>   	ctx = spin_ctx_init(fd, hwe, vm);
>   	spin_sync_start(fd, ctx);
>   
>   	read_engine_cycles(fd, pceu1);
>   	usleep(batch_duration_usec);
> -
> -	/* destroy queue before sampling again */
>   	spin_sync_end(fd, ctx);
> -	spin_ctx_destroy(fd, ctx);
> -
>   	read_engine_cycles(fd, pceu2);
>   
> -	xe_vm_destroy(fd, vm);
> +	xe_for_each_engine_class(class) {
> +		enum expected_load expected_load = hwe->engine_class != class ?
> +			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
>   
> -	check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
> +		check_results(pceu1, pceu2, class, expected_load);
> +	}
> +
> +	spin_sync_end(fd, ctx);
> +	spin_ctx_destroy(fd, ctx);
> +	xe_vm_destroy(fd, vm);
>   }
>   
>   static void
> -most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
> +utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>   {
>   	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> @@ -658,7 +658,7 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
>   }
>   
>   static void
> -all_busy_check_all(int fd)
> +utilization_all_full_load(int fd)
>   {
>   	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>   	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> @@ -710,51 +710,51 @@ igt_main
>   	}
>   
>   	igt_describe("Check if basic fdinfo content is present for memory");
> -	igt_subtest("basic-memory")
> +	igt_subtest("basic-mem")
>   		basic_memory(xe);
>   
>   	igt_describe("Check if basic fdinfo content is present for engine utilization");
> -	igt_subtest("basic-engine-utilization")
> +	igt_subtest("basic-utilization")
>   		basic_engine_utilization(xe);
>   
> -	igt_subtest("drm-idle")
> -		xe_for_each_engine(xe, hwe)
> -			single(xe, hwe, 0);
> +	igt_describe("Create and compare total and resident memory consumption by client");
> +	igt_subtest("mem-total-resident")
> +		mem_total_resident(xe);
>   
> -	igt_subtest("drm-busy-idle")
> -		xe_for_each_engine(xe, hwe)
> -			single(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE);
> +	igt_describe("Create and compare shared memory consumption by client");
> +	igt_subtest("mem-shared")
> +		mem_shared(xe);
>   
> -	igt_subtest("drm-busy-idle-isolation")
> -		xe_for_each_engine(xe, hwe)
> -			single(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE | TEST_ISOLATION);
> +	igt_describe("Create and compare active memory consumption by client");
> +	igt_subtest("mem-active")
> +		mem_active(xe, xe_engine(xe, 0));
>   
> -	igt_subtest("drm-busy-idle-check-all")
> +	igt_subtest("utilization-single-idle")
>   		xe_for_each_engine(xe, hwe)
> -			busy_check_all(xe, hwe);
> +			utilization_single(xe, hwe, 0);
>   
> -	igt_subtest("drm-most-busy-idle-check-all")
> +	igt_subtest("utilization-single-full-load")
>   		xe_for_each_engine(xe, hwe)
> -			most_busy_check_all(xe, hwe);
> +			utilization_single(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE);
>   
> -	igt_subtest("drm-all-busy-idle-check-all")
> -		all_busy_check_all(xe);
> +	igt_subtest("utilization-single-full-load-isolation")
> +		xe_for_each_engine(xe, hwe)
> +			utilization_single(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE | TEST_ISOLATION);
>   
> -	igt_subtest("drm-busy-exec-queue-destroy-idle")
> +	igt_subtest("utilization-single-full-load-destroy-queue")
>   		xe_for_each_engine(xe, hwe)
> -			single_destroy_queue(xe, hwe);
> +			utilization_single_destroy_queue(xe, hwe);
>   
> -	igt_describe("Create and compare total and resident memory consumption by client");
> -	igt_subtest("drm-total-resident")
> -		test_total_resident(xe);
> +	igt_subtest("utilization-others-idle")
> +		xe_for_each_engine(xe, hwe)
> +			utilization_others_idle(xe, hwe);
>   
> -	igt_describe("Create and compare shared memory consumption by client");
> -	igt_subtest("drm-shared")
> -		test_shared(xe);
> +	igt_subtest("utilization-others-full-load")
> +		xe_for_each_engine(xe, hwe)
> +			utilization_others_full_load(xe, hwe);
>   
> -	igt_describe("Create and compare active memory consumption by client");
> -	igt_subtest("drm-active")
> -		test_active(xe, xe_engine(xe, 0));
> +	igt_subtest("utilization-all-full-load")
> +		utilization_all_full_load(xe);
>   
>   	igt_fixture {
>   		drm_close_driver(xe);

Re: [PATCH i-g-t v3 10/10] tests/intel/xe_drm_fdinfo: Rename and reorder tests

[Nirmoy Das]

On 8/28/2024 5:08 PM, Nirmoy Das wrote:
>
> On 8/27/2024 6:54 PM, Lucas De Marchi wrote:
>> There are 2 main categories of tests in xe_drm_fdinfo:
>> mem and utilization. Group and name tests accordingly.
>>
>> For utilization, create subgroups: "single", "others" and "all",
>> with variants on each of them.
>>
>> No change in behavior on each tests, it's just rename and reorder.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>   tests/intel/xe_drm_fdinfo.c | 148 ++++++++++++++++++------------------
>>   1 file changed, 74 insertions(+), 74 deletions(-)
>>
>> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
>> index d45e45c6b..d1ed0fcaa 100644
>> --- a/tests/intel/xe_drm_fdinfo.c
>> +++ b/tests/intel/xe_drm_fdinfo.c
>> @@ -22,41 +22,41 @@
>>    * Feature: SMI, core
>>    * Test category: SysMan
>>    *
>> - * SUBTEST: basic-memory
>> + * SUBTEST: basic-mem
>>    * Description: Check if basic fdinfo content is present for memory
>>    *
>> - * SUBTEST: basic-engine-utilization
>> + * SUBTEST: basic-utilization
>>    * Description: Check if basic fdinfo content is present for engine 
>> utilization
>>    *
>> - * SUBTEST: drm-idle
>> - * Description: Check that engines show no load when idle
>> + * SUBTEST: mem-total-resident
>> + * Description: Create and compare total and resident memory 
>> consumption by client
>>    *
>> - * SUBTEST: drm-busy-idle
>> - * Description: Check that engines show load when idle after busy
>> + * SUBTEST: mem-shared
>> + * Description: Create and compare shared memory consumption by client
>>    *
>> - * SUBTEST: drm-busy-idle-isolation
>> - * Description: Check that engine load does not spill over to other 
>> drm clients
>> + * SUBTEST: mem-active
>> + * Description: Create and compare active memory consumption by client
>>    *
>> - * SUBTEST: drm-busy-idle-check-all
>> - * Description: Check that only the target engine shows load when 
>> idle after busy
>> + * SUBTEST: utilization-single-idle
>> + * Description: Check that each engine shows no load
>>    *
>> - * SUBTEST: drm-most-busy-idle-check-all
>> - * Description: Check that only the target engine shows idle and all 
>> others are busy
>> + * SUBTEST: utilization-single-full-load
>> + * Description: Check that each engine shows full load
>>    *
>> - * SUBTEST: drm-all-busy-idle-check-all
>> - * Description: Check that all engines show busy when all are loaded
>> + * SUBTEST: utilization-single-full-load-isolation
>> + * Description: Check that each engine load does not spill over to 
>> other drm clients
>>    *
>> - * SUBTEST: drm-busy-exec-queue-destroy-idle
>> + * SUBTEST: utilization-single-full-load-destroy-queue
>>    * Description: Destroy exec queue before idle and ensure load is 
>> accurate
>>    *
>> - * SUBTEST: drm-total-resident
>> - * Description: Create and compare total and resident memory 
>> consumption by client
>> + * SUBTEST: utilization-others-idle
>> + * Description: Check that only the target engine shows load
>>    *
>> - * SUBTEST: drm-shared
>> - * Description: Create and compare shared memory consumption by client
>> + * SUBTEST: utilization-others-full-load
>> + * Description: Check that only the target engine shows idle and all 
>> others are busy
>>    *
>> - * SUBTEST: drm-active
>> - * Description: Create and compare active memory consumption by client
>> + * SUBTEST: utilization-all-full-load
>> + * Description: Check that all engines show busy when all are loaded
>>    */
>>     IGT_TEST_DESCRIPTION("Read and verify drm client memory 
>> consumption and engine utilization using fdinfo");
>> @@ -104,7 +104,7 @@ static void read_engine_cycles(int xe, struct 
>> pceu_cycles *pceu)
>>   }
>>     /* Subtests */
>> -static void test_active(int fd, struct drm_xe_engine *engine)
>> +static void mem_active(int fd, struct drm_xe_engine *engine)
>>   {
>>       struct drm_xe_mem_region *memregion;
>>       uint64_t memreg = all_memory_regions(fd), region;
>> @@ -230,7 +230,7 @@ static void test_active(int fd, struct 
>> drm_xe_engine *engine)
>>       xe_vm_destroy(fd, vm);
>>   }
>>   -static void test_shared(int xe)
>> +static void mem_shared(int xe)
>>   {
>>       struct drm_xe_mem_region *memregion;
>>       uint64_t memreg = all_memory_regions(xe), region;
>> @@ -275,7 +275,7 @@ static void test_shared(int xe)
>>       }
>>   }
>>   -static void test_total_resident(int xe)
>> +static void mem_total_resident(int xe)
>>   {
>>       struct drm_xe_mem_region *memregion;
>>       uint64_t memreg = all_memory_regions(xe), region;
>> @@ -508,7 +508,7 @@ check_results(struct pceu_cycles *s1, struct 
>> pceu_cycles *s2,
>>   }
>>     static void
>> -single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned 
>> int flags)
>> +utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, 
>> unsigned int flags)
>>   {
>>       struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>       struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> @@ -557,64 +557,64 @@ single(int fd, struct 
>> drm_xe_engine_class_instance *hwe, unsigned int flags)
>>   }
>>     static void
>> -busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
>> +utilization_single_destroy_queue(int fd, struct 
>> drm_xe_engine_class_instance *hwe)
>>   {
>>       struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>       struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>       struct spin_ctx *ctx = NULL;
>>       uint32_t vm;
>> -    int class;
>>         vm = xe_vm_create(fd, 0, 0);
>> -
>>       ctx = spin_ctx_init(fd, hwe, vm);
>>       spin_sync_start(fd, ctx);
>>         read_engine_cycles(fd, pceu1);
>>       usleep(batch_duration_usec);
>> -    spin_sync_end(fd, ctx);
>> -    read_engine_cycles(fd, pceu2);
>> -
>> -    xe_for_each_engine_class(class) {
>> -        enum expected_load expected_load = hwe->engine_class != class ?
>> -            EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
>> -
>> -        check_results(pceu1, pceu2, class, expected_load);
>> -    }
>>   +    /* destroy queue before sampling again */
>
>
> Wouldn't this change the behavior ?


ah never mind. This was moved from single_destroy_queue()

Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>

>
>
> Regards,
>
> Nirmoy
>
>>       spin_sync_end(fd, ctx);
>>       spin_ctx_destroy(fd, ctx);
>> +
>> +    read_engine_cycles(fd, pceu2);
>> +
>>       xe_vm_destroy(fd, vm);
>> +
>> +    check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
>>   }
>>     static void
>> -single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe)
>> +utilization_others_idle(int fd, struct drm_xe_engine_class_instance 
>> *hwe)
>>   {
>>       struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>       struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>       struct spin_ctx *ctx = NULL;
>>       uint32_t vm;
>> +    int class;
>>         vm = xe_vm_create(fd, 0, 0);
>> +
>>       ctx = spin_ctx_init(fd, hwe, vm);
>>       spin_sync_start(fd, ctx);
>>         read_engine_cycles(fd, pceu1);
>>       usleep(batch_duration_usec);
>> -
>> -    /* destroy queue before sampling again */
>>       spin_sync_end(fd, ctx);
>> -    spin_ctx_destroy(fd, ctx);
>> -
>>       read_engine_cycles(fd, pceu2);
>>   -    xe_vm_destroy(fd, vm);
>> +    xe_for_each_engine_class(class) {
>> +        enum expected_load expected_load = hwe->engine_class != class ?
>> +            EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
>>   -    check_results(pceu1, pceu2, hwe->engine_class, 
>> EXPECTED_LOAD_FULL);
>> +        check_results(pceu1, pceu2, class, expected_load);
>> +    }
>> +
>> +    spin_sync_end(fd, ctx);
>> +    spin_ctx_destroy(fd, ctx);
>> +    xe_vm_destroy(fd, vm);
>>   }
>>     static void
>> -most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe)
>> +utilization_others_full_load(int fd, struct 
>> drm_xe_engine_class_instance *hwe)
>>   {
>>       struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>       struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> @@ -658,7 +658,7 @@ most_busy_check_all(int fd, struct 
>> drm_xe_engine_class_instance *hwe)
>>   }
>>     static void
>> -all_busy_check_all(int fd)
>> +utilization_all_full_load(int fd)
>>   {
>>       struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>       struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> @@ -710,51 +710,51 @@ igt_main
>>       }
>>         igt_describe("Check if basic fdinfo content is present for 
>> memory");
>> -    igt_subtest("basic-memory")
>> +    igt_subtest("basic-mem")
>>           basic_memory(xe);
>>         igt_describe("Check if basic fdinfo content is present for 
>> engine utilization");
>> -    igt_subtest("basic-engine-utilization")
>> +    igt_subtest("basic-utilization")
>>           basic_engine_utilization(xe);
>>   -    igt_subtest("drm-idle")
>> -        xe_for_each_engine(xe, hwe)
>> -            single(xe, hwe, 0);
>> +    igt_describe("Create and compare total and resident memory 
>> consumption by client");
>> +    igt_subtest("mem-total-resident")
>> +        mem_total_resident(xe);
>>   -    igt_subtest("drm-busy-idle")
>> -        xe_for_each_engine(xe, hwe)
>> -            single(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE);
>> +    igt_describe("Create and compare shared memory consumption by 
>> client");
>> +    igt_subtest("mem-shared")
>> +        mem_shared(xe);
>>   -    igt_subtest("drm-busy-idle-isolation")
>> -        xe_for_each_engine(xe, hwe)
>> -            single(xe, hwe, TEST_BUSY | TEST_TRAILING_IDLE | 
>> TEST_ISOLATION);
>> +    igt_describe("Create and compare active memory consumption by 
>> client");
>> +    igt_subtest("mem-active")
>> +        mem_active(xe, xe_engine(xe, 0));
>>   -    igt_subtest("drm-busy-idle-check-all")
>> +    igt_subtest("utilization-single-idle")
>>           xe_for_each_engine(xe, hwe)
>> -            busy_check_all(xe, hwe);
>> +            utilization_single(xe, hwe, 0);
>>   -    igt_subtest("drm-most-busy-idle-check-all")
>> +    igt_subtest("utilization-single-full-load")
>>           xe_for_each_engine(xe, hwe)
>> -            most_busy_check_all(xe, hwe);
>> +            utilization_single(xe, hwe, TEST_BUSY | 
>> TEST_TRAILING_IDLE);
>>   -    igt_subtest("drm-all-busy-idle-check-all")
>> -        all_busy_check_all(xe);
>> +    igt_subtest("utilization-single-full-load-isolation")
>> +        xe_for_each_engine(xe, hwe)
>> +            utilization_single(xe, hwe, TEST_BUSY | 
>> TEST_TRAILING_IDLE | TEST_ISOLATION);
>>   -    igt_subtest("drm-busy-exec-queue-destroy-idle")
>> +    igt_subtest("utilization-single-full-load-destroy-queue")
>>           xe_for_each_engine(xe, hwe)
>> -            single_destroy_queue(xe, hwe);
>> +            utilization_single_destroy_queue(xe, hwe);
>>   -    igt_describe("Create and compare total and resident memory 
>> consumption by client");
>> -    igt_subtest("drm-total-resident")
>> -        test_total_resident(xe);
>> +    igt_subtest("utilization-others-idle")
>> +        xe_for_each_engine(xe, hwe)
>> +            utilization_others_idle(xe, hwe);
>>   -    igt_describe("Create and compare shared memory consumption by 
>> client");
>> -    igt_subtest("drm-shared")
>> -        test_shared(xe);
>> +    igt_subtest("utilization-others-full-load")
>> +        xe_for_each_engine(xe, hwe)
>> +            utilization_others_full_load(xe, hwe);
>>   -    igt_describe("Create and compare active memory consumption by 
>> client");
>> -    igt_subtest("drm-active")
>> -        test_active(xe, xe_engine(xe, 0));
>> +    igt_subtest("utilization-all-full-load")
>> +        utilization_all_full_load(xe);
>>         igt_fixture {
>>           drm_close_driver(xe);

✓ CI.xeBAT: success for tests/intel/xe_drm_fdinfo: Fix noise and improve (rev2)

[Patchwork]

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== Series Details ==

Series: tests/intel/xe_drm_fdinfo: Fix noise and improve (rev2)
URL   : https://patchwork.freedesktop.org/series/137824/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7993_BAT -> XEIGTPW_11647_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_11647_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_hdmi_inject@inject-audio:
    - bat-adlp-7:         [DMESG-WARN][1] ([Intel XE#324]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/bat-adlp-7/igt@kms_hdmi_inject@inject-audio.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/bat-adlp-7/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
    - bat-adlp-7:         [DMESG-WARN][3] -> [PASS][4] +1 other test pass
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/bat-adlp-7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/bat-adlp-7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html

  
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324


Build changes
-------------

  * IGT: IGT_7993 -> IGTPW_11647
  * Linux: xe-1832-0f7dbe16a23882ef9c928d9650ea0613925e710b -> xe-1837-2c3fbd94c8b2eda2275211dfa8ead639a4e3e161

  IGTPW_11647: 11647
  IGT_7993: 3b6b2d238e864ff1af9e33159d3bbf4b7f01d86d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1832-0f7dbe16a23882ef9c928d9650ea0613925e710b: 0f7dbe16a23882ef9c928d9650ea0613925e710b
  xe-1837-2c3fbd94c8b2eda2275211dfa8ead639a4e3e161: 2c3fbd94c8b2eda2275211dfa8ead639a4e3e161

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/index.html

[-- Attachment #2: Type: text/html, Size: 2610 bytes --]

✗ Fi.CI.BAT: failure for tests/intel/xe_drm_fdinfo: Fix noise and improve (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4819 bytes --]

== Series Details ==

Series: tests/intel/xe_drm_fdinfo: Fix noise and improve (rev2)
URL   : https://patchwork.freedesktop.org/series/137824/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_15302 -> IGTPW_11647
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_11647 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_11647, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/index.html

Participating hosts (38 -> 39)
------------------------------

  Additional (3): bat-kbl-2 fi-elk-e7500 fi-pnv-d510 
  Missing    (2): fi-snb-2520m fi-kbl-8809g 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_11647:

### IGT changes ###

#### Possible regressions ####

  * igt@fbdev@eof:
    - bat-arls-1:         [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15302/bat-arls-1/igt@fbdev@eof.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/bat-arls-1/igt@fbdev@eof.html

  
Known issues
------------

  Here are the changes found in IGTPW_11647 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@info:
    - bat-kbl-2:          NOTRUN -> [SKIP][3] ([i915#1849])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/bat-kbl-2/igt@fbdev@info.html

  * igt@gem_lmem_swapping@basic:
    - fi-pnv-d510:        NOTRUN -> [SKIP][4] +32 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/fi-pnv-d510/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-kbl-2:          NOTRUN -> [SKIP][5] +39 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_selftest@live@hangcheck:
    - bat-mtlp-6:         [PASS][6] -> [DMESG-WARN][7] ([i915#11349])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15302/bat-mtlp-6/igt@i915_selftest@live@hangcheck.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/bat-mtlp-6/igt@i915_selftest@live@hangcheck.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - fi-elk-e7500:       NOTRUN -> [SKIP][8] +24 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/fi-elk-e7500/igt@kms_pm_rpm@basic-pci-d3-state.html

  
#### Possible fixes ####

  * igt@fbdev@read:
    - bat-arls-1:         [DMESG-FAIL][9] ([i915#9157]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15302/bat-arls-1/igt@fbdev@read.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/bat-arls-1/igt@fbdev@read.html

  * igt@i915_selftest@live@gem:
    - bat-arlh-2:         [INCOMPLETE][11] -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15302/bat-arlh-2/igt@i915_selftest@live@gem.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/bat-arlh-2/igt@i915_selftest@live@gem.html

  * igt@i915_selftest@live@hangcheck:
    - bat-arls-2:         [DMESG-WARN][13] ([i915#11349]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15302/bat-arls-2/igt@i915_selftest@live@hangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/bat-arls-2/igt@i915_selftest@live@hangcheck.html

  
#### Warnings ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-apl-1:          [DMESG-WARN][15] ([i915#180] / [i915#1982]) -> [DMESG-WARN][16] ([i915#180])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15302/bat-apl-1/igt@core_hotunplug@unbind-rebind.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/bat-apl-1/igt@core_hotunplug@unbind-rebind.html

  
  [i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
  [i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#9157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9157


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7993 -> IGTPW_11647

  CI-20190529: 20190529
  CI_DRM_15302: 2c3fbd94c8b2eda2275211dfa8ead639a4e3e161 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_11647: 11647
  IGT_7993: 3b6b2d238e864ff1af9e33159d3bbf4b7f01d86d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11647/index.html

[-- Attachment #2: Type: text/html, Size: 5837 bytes --]

✗ CI.xeFULL: failure for tests/intel/xe_drm_fdinfo: Fix noise and improve (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 100477 bytes --]

== Series Details ==

Series: tests/intel/xe_drm_fdinfo: Fix noise and improve (rev2)
URL   : https://patchwork.freedesktop.org/series/137824/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_7993_full -> XEIGTPW_11647_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_11647_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_11647_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_11647_full:

### IGT changes ###

#### Possible regressions ####

  * igt@core_setmaster@master-drop-set-user:
    - shard-dg2-set2:     [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@core_setmaster@master-drop-set-user.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@core_setmaster@master-drop-set-user.html

  * {igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue} (NEW):
    - shard-lnl:          NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-3/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - {shard-bmg}:        [FAIL][4] ([Intel XE#2436]) -> [INCOMPLETE][5] +1 other test incomplete
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-bmg-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_pm_rpm@legacy-planes-dpms@plane-68:
    - {shard-bmg}:        [PASS][6] -> [DMESG-WARN][7] +1 other test dmesg-warn
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-bmg-6/igt@kms_pm_rpm@legacy-planes-dpms@plane-68.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-bmg-5/igt@kms_pm_rpm@legacy-planes-dpms@plane-68.html

  * igt@xe_evict@evict-beng-mixed-threads-large:
    - {shard-bmg}:        [PASS][8] -> [FAIL][9]
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-bmg-3/igt@xe_evict@evict-beng-mixed-threads-large.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-bmg-5/igt@xe_evict@evict-beng-mixed-threads-large.html

  
New tests
---------

  New tests have been introduced between XEIGT_7993_full and XEIGTPW_11647_full:

### New IGT tests (12) ###

  * igt@xe_drm_fdinfo@basic-mem:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@xe_drm_fdinfo@basic-utilization:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@xe_drm_fdinfo@mem-active:
    - Statuses : 2 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_drm_fdinfo@mem-shared:
    - Statuses : 3 pass(s)
    - Exec time: [0.00] s

  * igt@xe_drm_fdinfo@mem-total-resident:
    - Statuses : 2 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_drm_fdinfo@utilization-all-full-load:
    - Statuses : 3 pass(s)
    - Exec time: [0.26, 0.27] s

  * igt@xe_drm_fdinfo@utilization-others-full-load:
    - Statuses : 2 pass(s)
    - Exec time: [1.83] s

  * igt@xe_drm_fdinfo@utilization-others-idle:
    - Statuses : 3 pass(s)
    - Exec time: [1.28, 1.79] s

  * igt@xe_drm_fdinfo@utilization-single-full-load:
    - Statuses : 2 pass(s) 1 skip(s)
    - Exec time: [0.0, 1.79] s

  * igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue:
    - Statuses : 1 fail(s) 2 pass(s)
    - Exec time: [1.30, 1.80] s

  * igt@xe_drm_fdinfo@utilization-single-full-load-isolation:
    - Statuses : 2 pass(s)
    - Exec time: [1.27, 1.79] s

  * igt@xe_drm_fdinfo@utilization-single-idle:
    - Statuses : 3 pass(s)
    - Exec time: [1.26, 1.77] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_11647_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_getversion@basic:
    - shard-dg2-set2:     NOTRUN -> [FAIL][10] ([Intel XE#2452])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@core_getversion@basic.html

  * igt@core_hotunplug@hotrebind:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#1201] / [Intel XE#1885])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@core_hotunplug@hotrebind.html

  * igt@core_hotunplug@hotunbind-rebind:
    - shard-dg2-set2:     [PASS][12] -> [SKIP][13] ([Intel XE#1201] / [Intel XE#1885])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@core_hotunplug@hotunbind-rebind.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@core_hotunplug@hotunbind-rebind.html

  * igt@core_setmaster_vs_auth:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#1201] / [Intel XE#2423])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@core_setmaster_vs_auth.html

  * igt@fbdev@write:
    - shard-dg2-set2:     [PASS][15] -> [SKIP][16] ([Intel XE#1201] / [Intel XE#2134]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@fbdev@write.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@fbdev@write.html

  * igt@kms_addfb_basic@addfb25-modifier-no-flag:
    - shard-dg2-set2:     [PASS][17] -> [SKIP][18] ([Intel XE#1201] / [i915#6077])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@kms_addfb_basic@addfb25-modifier-no-flag.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_addfb_basic@addfb25-modifier-no-flag.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-dg2-set2:     NOTRUN -> [FAIL][19] ([Intel XE#827]) +1 other test fail
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
    - shard-dg2-set2:     [PASS][20] -> [SKIP][21] ([Intel XE#1201]) +53 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html

  * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +6 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#1124])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-7/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#1124] / [Intel XE#1201]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#1201] / [Intel XE#2191])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-463/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#1201] / [Intel XE#787]) +27 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-463/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-434/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#1399]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-7/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#373]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-8/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#1424])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-8/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-dg2-set2:     NOTRUN -> [SKIP][31] ([Intel XE#1201] / [Intel XE#455]) +4 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#776])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2-set2:     NOTRUN -> [SKIP][33] ([Intel XE#1201] / [Intel XE#701])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1:
    - shard-lnl:          [PASS][34] -> [FAIL][35] ([Intel XE#886]) +2 other tests fail
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-4/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-3/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][36] ([Intel XE#455]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#651]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][38] ([Intel XE#1201] / [Intel XE#651]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-dg2-set2:     [PASS][39] -> [SKIP][40] ([Intel XE#1201] / [Intel XE#783])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     [PASS][41] -> [SKIP][42] ([Intel XE#1201] / [Intel XE#2351]) +16 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#1201] / [Intel XE#2351]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][44] ([Intel XE#653])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][45] ([Intel XE#1201] / [Intel XE#653]) +9 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_getfb@getfb2-accept-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#2340])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-3/igt@kms_getfb@getfb2-accept-ccs.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12:
    - shard-dg2-set2:     [PASS][47] -> [SKIP][48] ([Intel XE#1201] / [Intel XE#829]) +4 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12.html

  * igt@kms_plane@plane-position-covered:
    - shard-lnl:          [PASS][49] -> [DMESG-FAIL][50] ([Intel XE#324]) +1 other test dmesg-fail
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-1/igt@kms_plane@plane-position-covered.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-6/igt@kms_plane@plane-position-covered.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers:
    - shard-dg2-set2:     [PASS][51] -> [SKIP][52] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +133 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
    - shard-dg2-set2:     NOTRUN -> [SKIP][53] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#1201] / [Intel XE#2318]) +2 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#1201]) +14 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_plane_scaling@planes-upscale-factor-0-25.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [PASS][56] -> [FAIL][57] ([Intel XE#718])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-2/igt@kms_pm_dc@dc5-psr.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-1/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [PASS][58] -> [FAIL][59] ([Intel XE#1430])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-3/igt@kms_pm_dc@dc6-psr.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-5/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_rpm@legacy-planes-dpms:
    - shard-lnl:          [PASS][60] -> [INCOMPLETE][61] ([Intel XE#1620])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-7/igt@kms_pm_rpm@legacy-planes-dpms.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-1/igt@kms_pm_rpm@legacy-planes-dpms.html

  * igt@kms_pm_rpm@legacy-planes-dpms@plane-41:
    - shard-lnl:          [PASS][62] -> [DMESG-FAIL][63] ([Intel XE#1620])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-7/igt@kms_pm_rpm@legacy-planes-dpms@plane-41.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-1/igt@kms_pm_rpm@legacy-planes-dpms@plane-41.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-dg2-set2:     [PASS][64] -> [SKIP][65] ([Intel XE#1201] / [Intel XE#2446]) +6 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_pm_rpm@modeset-non-lpsp.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][66] ([Intel XE#1201] / [Intel XE#1489])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@psr2-primary-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#1201] / [Intel XE#929]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-463/igt@kms_psr@psr2-primary-render.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#756])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-8/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#944]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-3/igt@xe_create@multigpu-create-massive-size.html

  * {igt@xe_drm_fdinfo@mem-total-resident} (NEW):
    - shard-dg2-set2:     NOTRUN -> [SKIP][70] ([Intel XE#1130] / [Intel XE#1201]) +11 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_drm_fdinfo@mem-total-resident.html

  * igt@xe_evict@evict-beng-mixed-threads-large:
    - shard-dg2-set2:     [PASS][71] -> [FAIL][72] ([Intel XE#1000])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@xe_evict@evict-beng-mixed-threads-large.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@xe_evict@evict-beng-mixed-threads-large.html

  * igt@xe_evict@evict-beng-small-cm:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#688])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-4/igt@xe_evict@evict-beng-small-cm.html

  * igt@xe_evict@evict-large-multi-vm-cm:
    - shard-dg2-set2:     [PASS][74] -> [FAIL][75] ([Intel XE#1600])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@xe_evict@evict-large-multi-vm-cm.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-463/igt@xe_evict@evict-large-multi-vm-cm.html

  * igt@xe_evict@evict-threads-large:
    - shard-dg2-set2:     [PASS][76] -> [TIMEOUT][77] ([Intel XE#1473])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@xe_evict@evict-threads-large.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@xe_evict@evict-threads-large.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#1392])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-6/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#288])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@xe_exec_fault_mode@many-basic.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][80] ([Intel XE#1201] / [Intel XE#288]) +3 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@xe_exec_fault_mode@twice-userptr-invalidate-race.html

  * igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
    - shard-dg2-set2:     NOTRUN -> [SKIP][81] ([Intel XE#1201] / [Intel XE#2360])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html

  * igt@xe_live_ktest@xe_bo:
    - shard-dg2-set2:     [PASS][82] -> [SKIP][83] ([Intel XE#1201] / [Intel XE#2229] / [Intel XE#455]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@xe_live_ktest@xe_bo.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_live_ktest@xe_bo.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-dg2-set2:     [PASS][84] -> [SKIP][85] ([Intel XE#1201] / [Intel XE#2229])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_module_load@reload-no-display:
    - shard-dg2-set2:     [PASS][86] -> [FAIL][87] ([Intel XE#1204] / [Intel XE#2136])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@xe_module_load@reload-no-display.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@xe_module_load@reload-no-display.html

  * igt@xe_pm@d3cold-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][88] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-463/igt@xe_pm@d3cold-basic.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-lnl:          [PASS][89] -> [ABORT][90] ([Intel XE#1794])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-6/igt@xe_pm@s4-vm-bind-unbind-all.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_pm_residency@toggle-gt-c6:
    - shard-lnl:          [PASS][91] -> [FAIL][92] ([Intel XE#958])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-1/igt@xe_pm_residency@toggle-gt-c6.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-3/igt@xe_pm_residency@toggle-gt-c6.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-dg2-set2:     NOTRUN -> [SKIP][93] ([Intel XE#1201] / [Intel XE#944])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-434/igt@xe_query@multigpu-query-mem-usage.html

  * igt@xe_vm@munmap-style-unbind-many-either-side-partial:
    - shard-dg2-set2:     [PASS][94] -> [SKIP][95] ([Intel XE#1130] / [Intel XE#1201]) +242 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@xe_vm@munmap-style-unbind-many-either-side-partial.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_vm@munmap-style-unbind-many-either-side-partial.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear:
    - shard-lnl:          [FAIL][96] ([Intel XE#911]) -> [PASS][97] +3 other tests pass
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1:
    - shard-lnl:          [FAIL][98] ([Intel XE#1426]) -> [PASS][99] +3 other tests pass
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          [FAIL][100] ([Intel XE#1659]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-dp-2:
    - {shard-bmg}:        [FAIL][102] -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-bmg-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-dp-2.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-sliding-64x64:
    - shard-dg2-set2:     [INCOMPLETE][104] ([Intel XE#1195]) -> [PASS][105] +1 other test pass
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_cursor_crc@cursor-sliding-64x64.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@kms_cursor_crc@cursor-sliding-64x64.html

  * igt@kms_flip@2x-flip-vs-suspend@bc-dp2-hdmi-a3:
    - {shard-bmg}:        [INCOMPLETE][106] -> [PASS][107] +2 other tests pass
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-bmg-6/igt@kms_flip@2x-flip-vs-suspend@bc-dp2-hdmi-a3.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-bmg-7/igt@kms_flip@2x-flip-vs-suspend@bc-dp2-hdmi-a3.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-lnl:          [FAIL][108] ([Intel XE#886]) -> [PASS][109] +3 other tests pass
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-2/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-8/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - {shard-bmg}:        [INCOMPLETE][110] ([Intel XE#2597]) -> [PASS][111] +2 other tests pass
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-bmg-5/igt@kms_flip@flip-vs-suspend.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-bmg-3/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [FAIL][112] ([Intel XE#718]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-3/igt@kms_pm_dc@dc5-dpms.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-6/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_psr@fbc-psr2-dpms:
    - shard-lnl:          [FAIL][114] ([Intel XE#1649]) -> [PASS][115] +1 other test pass
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-7/igt@kms_psr@fbc-psr2-dpms.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-7/igt@kms_psr@fbc-psr2-dpms.html

  * igt@kms_vrr@flip-basic:
    - shard-lnl:          [FAIL][116] ([Intel XE#2443]) -> [PASS][117] +1 other test pass
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-3/igt@kms_vrr@flip-basic.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-5/igt@kms_vrr@flip-basic.html

  * igt@xe_evict@evict-large-multi-vm-cm:
    - {shard-bmg}:        [FAIL][118] ([Intel XE#2364]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-bmg-1/igt@xe_evict@evict-large-multi-vm-cm.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-bmg-7/igt@xe_evict@evict-large-multi-vm-cm.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-dg2-set2:     [TIMEOUT][120] ([Intel XE#1473]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@xe_evict@evict-mixed-many-threads-small.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-dg2-set2:     [TIMEOUT][122] ([Intel XE#2105]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@xe_exec_reset@parallel-gt-reset.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_exec_threads@threads-bal-mixed-fd-basic:
    - {shard-bmg}:        [DMESG-WARN][124] ([Intel XE#877]) -> [PASS][125] +5 other tests pass
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-bmg-1/igt@xe_exec_threads@threads-bal-mixed-fd-basic.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-bmg-3/igt@xe_exec_threads@threads-bal-mixed-fd-basic.html

  * igt@xe_oa@mmio-triggered-reports:
    - {shard-bmg}:        [FAIL][126] ([Intel XE#2249]) -> [PASS][127] +1 other test pass
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-bmg-3/igt@xe_oa@mmio-triggered-reports.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-bmg-3/igt@xe_oa@mmio-triggered-reports.html
    - shard-lnl:          [FAIL][128] ([Intel XE#2249]) -> [PASS][129] +1 other test pass
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-2/igt@xe_oa@mmio-triggered-reports.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-5/igt@xe_oa@mmio-triggered-reports.html

  * igt@xe_pm@s4-basic:
    - shard-lnl:          [ABORT][130] ([Intel XE#1358] / [Intel XE#1607]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-lnl-2/igt@xe_pm@s4-basic.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-lnl-6/igt@xe_pm@s4-basic.html

  
#### Warnings ####

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-dg2-set2:     [SKIP][132] ([Intel XE#623]) -> [SKIP][133] ([Intel XE#1201] / [Intel XE#623])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-dg2-set2:     [FAIL][134] ([Intel XE#1426]) -> [SKIP][135] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_atomic_transition@plane-all-modeset-transition.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][136] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][137] ([Intel XE#1201] / [Intel XE#2351]) +3 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][138] ([Intel XE#316]) -> [SKIP][139] ([Intel XE#1201] / [Intel XE#316]) +2 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][140] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][141] ([Intel XE#316]) +3 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_big_fb@linear-16bpp-rotate-270.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][142] ([Intel XE#316]) -> [SKIP][143] ([Intel XE#1201] / [Intel XE#2351])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_big_fb@linear-64bpp-rotate-270.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][144] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][145] ([Intel XE#1201]) +4 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-dg2-set2:     [SKIP][146] ([Intel XE#1124]) -> [SKIP][147] ([Intel XE#1124] / [Intel XE#1201]) +3 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     [SKIP][148] ([Intel XE#1201] / [Intel XE#607]) -> [SKIP][149] ([Intel XE#1201] / [Intel XE#829])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg2-set2:     [SKIP][150] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][151] ([Intel XE#1201] / [Intel XE#2351]) +7 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-dg2-set2:     [SKIP][152] ([Intel XE#1124]) -> [SKIP][153] ([Intel XE#1201]) +2 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2-set2:     [SKIP][154] ([Intel XE#1201] / [Intel XE#619]) -> [SKIP][155] ([Intel XE#1201] / [Intel XE#2351])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_big_fb@yf-tiled-addfb.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-dg2-set2:     [SKIP][156] ([Intel XE#1201] / [Intel XE#610]) -> [SKIP][157] ([Intel XE#610])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-dg2-set2:     [SKIP][158] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][159] ([Intel XE#1201]) +8 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-dg2-set2:     [SKIP][160] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][161] ([Intel XE#1201] / [Intel XE#829]) +1 other test skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg2-set2:     [SKIP][162] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][163] ([Intel XE#1124]) +4 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-dg2-set2:     [SKIP][164] ([Intel XE#1201] / [Intel XE#346]) -> [SKIP][165] ([Intel XE#1201] / [Intel XE#2351])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_big_joiner@invalid-modeset.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][166] ([Intel XE#367]) -> [SKIP][167] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +1 other test skip
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][168] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][169] ([Intel XE#367]) +1 other test skip
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][170] ([Intel XE#1201] / [Intel XE#2191]) -> [SKIP][171] ([Intel XE#2191])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
    - shard-dg2-set2:     [SKIP][172] ([Intel XE#1201] / [Intel XE#2191]) -> [SKIP][173] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-2560x1440p:
    - shard-dg2-set2:     [SKIP][174] ([Intel XE#367]) -> [SKIP][175] ([Intel XE#1201] / [Intel XE#367]) +1 other test skip
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-434/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][176] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][177] ([Intel XE#1201]) +1 other test skip
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-3840x2160p:
    - shard-dg2-set2:     [SKIP][178] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][179] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +3 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
    - shard-dg2-set2:     [SKIP][180] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][181] ([Intel XE#1201] / [Intel XE#2351])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     [SKIP][182] ([Intel XE#787]) -> [SKIP][183] ([Intel XE#1201] / [Intel XE#787]) +34 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-dp-4.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-dp-4.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-dg2-set2:     [SKIP][184] ([Intel XE#1252]) -> [SKIP][185] ([Intel XE#1201])
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs:
    - shard-dg2-set2:     [SKIP][186] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][187] ([Intel XE#1201] / [Intel XE#829])
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs:
    - shard-dg2-set2:     [SKIP][188] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][189] ([Intel XE#1201]) +1 other test skip
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4:
    - shard-dg2-set2:     [SKIP][190] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][191] ([Intel XE#455] / [Intel XE#787]) +17 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-dg2-set2:     [SKIP][192] ([Intel XE#1252]) -> [SKIP][193] ([Intel XE#1201] / [Intel XE#1252]) +1 other test skip
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
    - shard-dg2-set2:     [SKIP][194] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][195] ([Intel XE#1201]) +10 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-dg2-set2:     [SKIP][196] ([Intel XE#1201] / [Intel XE#1252]) -> [SKIP][197] ([Intel XE#1201] / [Intel XE#829])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][198] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][199] ([Intel XE#787]) +62 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs:
    - shard-dg2-set2:     [SKIP][200] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][201] ([Intel XE#1201] / [Intel XE#2351]) +1 other test skip
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg2-set2:     [SKIP][202] ([Intel XE#1201] / [Intel XE#1252]) -> [SKIP][203] ([Intel XE#1201]) +2 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-ccs:
    - shard-dg2-set2:     [SKIP][204] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][205] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +9 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-463/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs:
    - shard-dg2-set2:     [SKIP][206] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][207] ([Intel XE#1201] / [Intel XE#829])
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs.html

  * igt@kms_cdclk@mode-transition@pipe-d-dp-4:
    - shard-dg2-set2:     [SKIP][208] ([Intel XE#1201] / [Intel XE#314]) -> [SKIP][209] ([Intel XE#314]) +3 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-dg2-set2:     [SKIP][210] ([Intel XE#306]) -> [SKIP][211] ([Intel XE#1201] / [Intel XE#306])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_chamelium_color@ctm-0-25.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-dg2-set2:     [SKIP][212] ([Intel XE#1201] / [Intel XE#306]) -> [SKIP][213] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +2 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_chamelium_color@ctm-0-50.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-dg2-set2:     [SKIP][214] ([Intel XE#1201] / [Intel XE#306]) -> [SKIP][215] ([Intel XE#306])
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_chamelium_color@ctm-0-75.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-dg2-set2:     [SKIP][216] ([Intel XE#306]) -> [SKIP][217] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +1 other test skip
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_chamelium_color@ctm-red-to-blue.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-dg2-set2:     [SKIP][218] ([Intel XE#373]) -> [SKIP][219] ([Intel XE#1201] / [Intel XE#373]) +4 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_chamelium_frames@hdmi-crc-multiple:
    - shard-dg2-set2:     [SKIP][220] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][221] ([Intel XE#1201])
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_chamelium_frames@hdmi-crc-multiple.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_chamelium_frames@hdmi-crc-multiple.html

  * igt@kms_chamelium_hpd@dp-hpd-fast:
    - shard-dg2-set2:     [SKIP][222] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][223] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +14 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_chamelium_hpd@dp-hpd-fast.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_chamelium_hpd@dp-hpd-fast.html

  * igt@kms_chamelium_hpd@vga-hpd:
    - shard-dg2-set2:     [SKIP][224] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][225] ([Intel XE#373]) +4 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_chamelium_hpd@vga-hpd.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_chamelium_hpd@vga-hpd.html

  * igt@kms_color@ctm-0-25:
    - shard-dg2-set2:     [INCOMPLETE][226] -> [SKIP][227] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_color@ctm-0-25.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_color@ctm-0-25.html

  * igt@kms_content_protection@atomic:
    - shard-dg2-set2:     [FAIL][228] ([Intel XE#1178]) -> [SKIP][229] ([Intel XE#1201])
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_content_protection@atomic.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2-set2:     [SKIP][230] ([Intel XE#1201] / [Intel XE#307]) -> [SKIP][231] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_content_protection@dp-mst-lic-type-0.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-dg2-set2:     [SKIP][232] ([Intel XE#1201] / [Intel XE#307]) -> [SKIP][233] ([Intel XE#307]) +2 other tests skip
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@kms_content_protection@dp-mst-type-1.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@srm:
    - shard-dg2-set2:     [FAIL][234] ([Intel XE#1178]) -> [SKIP][235] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_content_protection@srm.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-dg2-set2:     [SKIP][236] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][237] ([Intel XE#308]) +1 other test skip
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_cursor_crc@cursor-onscreen-512x512.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-dg2-set2:     [SKIP][238] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][239] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +11 other tests skip
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@kms_cursor_crc@cursor-random-max-size.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-dg2-set2:     [SKIP][240] ([Intel XE#308]) -> [SKIP][241] ([Intel XE#1201] / [Intel XE#308]) +1 other test skip
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-463/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-dg2-set2:     [SKIP][242] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][243] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_cursor_crc@cursor-sliding-512x170.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg2-set2:     [SKIP][244] ([Intel XE#323]) -> [SKIP][245] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-dg2-set2:     [SKIP][246] ([Intel XE#1201] / [Intel XE#323]) -> [SKIP][247] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     [SKIP][248] ([Intel XE#1201] / [Intel XE#323]) -> [SKIP][249] ([Intel XE#323])
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-dg2-set2:     [SKIP][250] ([Intel XE#307]) -> [SKIP][251] ([Intel XE#1201] / [Intel XE#307])
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_display_modes@mst-extended-mode-negative.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-dg2-set2:     [SKIP][252] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][253] ([Intel XE#1201] / [Intel XE#2351])
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-dg2-set2:     [SKIP][254] ([Intel XE#455]) -> [SKIP][255] ([Intel XE#1201] / [Intel XE#2351])
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_dsc@dsc-with-formats.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2-set2:     [SKIP][256] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][257] ([Intel XE#1201]) +6 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2-set2:     [SKIP][258] ([Intel XE#703]) -> [SKIP][259] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_feature_discovery@display-3x.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-dg2-set2:     [SKIP][260] ([Intel XE#1138] / [Intel XE#1201]) -> [SKIP][261] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_feature_discovery@display-4x.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@psr1:
    - shard-dg2-set2:     [SKIP][262] ([Intel XE#1135] / [Intel XE#1201]) -> [SKIP][263] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@kms_feature_discovery@psr1.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-dg2-set2:     [SKIP][264] ([Intel XE#455]) -> [SKIP][265] ([Intel XE#1201])
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-dg2-set2:     [SKIP][266] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][267] ([Intel XE#455]) +6 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [SKIP][268] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][269] ([Intel XE#1201]) +26 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move:
    - shard-dg2-set2:     [SKIP][270] ([Intel XE#651]) -> [SKIP][271] ([Intel XE#1201]) +8 other tests skip
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     [SKIP][272] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][273] ([Intel XE#1201] / [Intel XE#2351]) +12 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@drrs-slowdraw:
    - shard-dg2-set2:     [SKIP][274] ([Intel XE#651]) -> [SKIP][275] ([Intel XE#1201] / [Intel XE#2351]) +2 other tests skip
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-slowdraw.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-slowdraw.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2-set2:     [SKIP][276] ([Intel XE#1201] / [Intel XE#658]) -> [SKIP][277] ([Intel XE#658])
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
    - shard-dg2-set2:     [SKIP][278] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][279] ([Intel XE#651]) +15 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw:
    - shard-dg2-set2:     [SKIP][280] ([Intel XE#651]) -> [SKIP][281] ([Intel XE#1201] / [Intel XE#651]) +12 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][282] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][283] ([Intel XE#1201]) +37 other tests skip
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][284] ([Intel XE#653]) -> [SKIP][285] ([Intel XE#1201]) +4 other tests skip
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][286] ([Intel XE#653]) -> [SKIP][287] ([Intel XE#1201] / [Intel XE#653]) +13 other tests skip
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][288] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][289] ([Intel XE#1201] / [Intel XE#2351]) +12 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-dg2-set2:     [SKIP][290] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][291] ([Intel XE#653]) +14 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-slowdraw.html
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     [SKIP][292] ([Intel XE#455]) -> [SKIP][293] ([Intel XE#1201] / [Intel XE#455]) +4 other tests skip
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_hdr@invalid-hdr.html
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-433/igt@kms_hdr@invalid-hdr.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-dg2-set2:     [SKIP][294] ([Intel XE#1201] / [Intel XE#356]) -> [SKIP][295] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane_cursor@primary:
    - shard-dg2-set2:     [FAIL][296] ([Intel XE#616]) -> [SKIP][297] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_plane_cursor@primary.html
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_plane_cursor@primary.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-dg2-set2:     [SKIP][298] ([Intel XE#455]) -> [SKIP][299] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +3 other tests skip
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_plane_lowres@tiling-y.html
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
    - shard-dg2-set2:     [SKIP][300] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#498]) -> [SKIP][301] ([Intel XE#1201])
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling:
    - shard-dg2-set2:     [SKIP][302] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) -> [SKIP][303] ([Intel XE#2318] / [Intel XE#455]) +1 other test skip
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][304] ([Intel XE#1201] / [Intel XE#2318]) -> [SKIP][305] ([Intel XE#2318]) +2 other tests skip
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-6.html
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20:
    - shard-dg2-set2:     [SKIP][306] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) -> [SKIP][307] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +1 other test skip
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20.html
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-dg2-set2:     [SKIP][308] ([Intel XE#1201] / [Intel XE#870]) -> [SKIP][309] ([Intel XE#1201]) +1 other test skip
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@kms_pm_backlight@bad-brightness.html
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-dg2-set2:     [SKIP][310] ([Intel XE#870]) -> [SKIP][311] ([Intel XE#1201] / [Intel XE#870])
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_pm_backlight@fade-with-dpms.html
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-dg2-set2:     [SKIP][312] ([Intel XE#1129] / [Intel XE#1201]) -> [SKIP][313] ([Intel XE#1129])
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@kms_pm_dc@dc6-psr.html
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf:
    - shard-dg2-set2:     [SKIP][314] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][315] ([Intel XE#1489])
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf.html
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-overlay-primary-update-sf-dmg-area:
    - shard-dg2-set2:     [SKIP][316] ([Intel XE#1489]) -> [SKIP][317] ([Intel XE#1201] / [Intel XE#1489])
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_psr2_sf@fbc-overlay-primary-update-sf-dmg-area.html
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@kms_psr2_sf@fbc-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-dg2-set2:     [SKIP][318] ([Intel XE#1489]) -> [SKIP][319] ([Intel XE#1201])
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area:
    - shard-dg2-set2:     [SKIP][320] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][321] ([Intel XE#1201] / [Intel XE#2351])
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_psr2_sf@plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
    - shard-dg2-set2:     [SKIP][322] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][323] ([Intel XE#1201]) +6 other tests skip
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg2-set2:     [SKIP][324] ([Intel XE#1122]) -> [SKIP][325] ([Intel XE#1201])
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_psr2_su@frontbuffer-xrgb8888.html
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2-set2:     [SKIP][326] ([Intel XE#1122]) -> [SKIP][327] ([Intel XE#1122] / [Intel XE#1201])
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_psr2_su@page_flip-p010.html
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr-sprite-render:
    - shard-dg2-set2:     [SKIP][328] ([Intel XE#929]) -> [SKIP][329] ([Intel XE#1201] / [Intel XE#929]) +7 other tests skip
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_psr@fbc-psr-sprite-render.html
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-434/igt@kms_psr@fbc-psr-sprite-render.html

  * igt@kms_psr@fbc-psr2-cursor-blt:
    - shard-dg2-set2:     [SKIP][330] ([Intel XE#929]) -> [SKIP][331] ([Intel XE#1201])
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_psr@fbc-psr2-cursor-blt.html
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@kms_psr@fbc-psr2-cursor-blt.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-dg2-set2:     [SKIP][332] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][333] ([Intel XE#1201]) +15 other tests skip
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_psr@fbc-psr2-primary-render.html
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-dg2-set2:     [SKIP][334] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][335] ([Intel XE#929]) +9 other tests skip
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_psr@fbc-psr2-sprite-plane-move.html
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@pr-dpms:
    - shard-dg2-set2:     [SKIP][336] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][337] ([Intel XE#1201] / [Intel XE#2351]) +7 other tests skip
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@kms_psr@pr-dpms.html
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_psr@pr-dpms.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-dg2-set2:     [SKIP][338] ([Intel XE#1149]) -> [SKIP][339] ([Intel XE#1149] / [Intel XE#1201])
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-434/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-dg2-set2:     [SKIP][340] ([Intel XE#1149]) -> [SKIP][341] ([Intel XE#1201])
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2-set2:     [SKIP][342] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][343] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) +2 other tests skip
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_rotation_crc@bad-tiling.html
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-dg2-set2:     [SKIP][344] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][345] ([Intel XE#327]) +1 other test skip
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_rotation_crc@primary-rotation-90.html
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-dg2-set2:     [SKIP][346] ([Intel XE#1127] / [Intel XE#1201]) -> [SKIP][347] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-dg2-set2:     [SKIP][348] ([Intel XE#1127]) -> [SKIP][349] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2-set2:     [FAIL][350] ([Intel XE#1729]) -> [SKIP][351] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_tiled_display@basic-test-pattern.html
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-dg2-set2:     [SKIP][352] ([Intel XE#1201] / [Intel XE#330]) -> [SKIP][353] ([Intel XE#330])
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_tv_load_detect@load-detect.html
   [353]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@lobf:
    - shard-dg2-set2:     [SKIP][354] ([Intel XE#1201] / [Intel XE#2168]) -> [SKIP][355] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [354]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@kms_vrr@lobf.html
   [355]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_vrr@lobf.html

  * igt@kms_writeback@writeback-check-output:
    - shard-dg2-set2:     [SKIP][356] ([Intel XE#1201] / [Intel XE#756]) -> [SKIP][357] ([Intel XE#756])
   [356]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@kms_writeback@writeback-check-output.html
   [357]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-dg2-set2:     [SKIP][358] ([Intel XE#1201] / [Intel XE#756]) -> [SKIP][359] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575])
   [358]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@kms_writeback@writeback-pixel-formats.html
   [359]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@kms_writeback@writeback-pixel-formats.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-dg2-set2:     [SKIP][360] ([Intel XE#1091] / [Intel XE#1201]) -> [SKIP][361] ([Intel XE#1091])
   [360]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
   [361]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@xe_compute_preempt@compute-preempt:
    - shard-dg2-set2:     [SKIP][362] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][363] ([Intel XE#1201] / [Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [362]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_compute_preempt@compute-preempt.html
   [363]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-463/igt@xe_compute_preempt@compute-preempt.html

  * igt@xe_copy_basic@mem-copy-linear-0xfd:
    - shard-dg2-set2:     [SKIP][364] ([Intel XE#1123]) -> [SKIP][365] ([Intel XE#1130] / [Intel XE#1201])
   [364]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_copy_basic@mem-copy-linear-0xfd.html
   [365]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_copy_basic@mem-copy-linear-0xfd.html

  * igt@xe_copy_basic@mem-copy-linear-0xfffe:
    - shard-dg2-set2:     [SKIP][366] ([Intel XE#1123] / [Intel XE#1201]) -> [SKIP][367] ([Intel XE#1130] / [Intel XE#1201])
   [366]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@xe_copy_basic@mem-copy-linear-0xfffe.html
   [367]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_copy_basic@mem-copy-linear-0xfffe.html

  * igt@xe_copy_basic@mem-set-linear-0xfffe:
    - shard-dg2-set2:     [SKIP][368] ([Intel XE#1126] / [Intel XE#1201]) -> [SKIP][369] ([Intel XE#1130] / [Intel XE#1201])
   [368]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0xfffe.html
   [369]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_copy_basic@mem-set-linear-0xfffe.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate:
    - shard-dg2-set2:     [SKIP][370] ([Intel XE#288]) -> [SKIP][371] ([Intel XE#1130] / [Intel XE#1201]) +5 other tests skip
   [370]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate.html
   [371]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-imm:
    - shard-dg2-set2:     [SKIP][372] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][373] ([Intel XE#288]) +14 other tests skip
   [372]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@xe_exec_fault_mode@once-bindexecqueue-imm.html
   [373]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@xe_exec_fault_mode@once-bindexecqueue-imm.html

  * igt@xe_exec_fault_mode@once-invalid-userptr-fault:
    - shard-dg2-set2:     [SKIP][374] ([Intel XE#288]) -> [SKIP][375] ([Intel XE#1201] / [Intel XE#288]) +14 other tests skip
   [374]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html
   [375]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch:
    - shard-dg2-set2:     [SKIP][376] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][377] ([Intel XE#1130] / [Intel XE#1201]) +37 other tests skip
   [376]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html
   [377]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence:
    - shard-dg2-set2:     [SKIP][378] ([Intel XE#2360]) -> [SKIP][379] ([Intel XE#1130] / [Intel XE#1201])
   [378]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html
   [379]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html

  * igt@xe_exec_mix_modes@exec-spinner-interrupted-lr:
    - shard-dg2-set2:     [SKIP][380] ([Intel XE#1201] / [Intel XE#2360]) -> [SKIP][381] ([Intel XE#2360])
   [380]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@xe_exec_mix_modes@exec-spinner-interrupted-lr.html
   [381]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@xe_exec_mix_modes@exec-spinner-interrupted-lr.html

  * igt@xe_oa@buffer-fill:
    - shard-dg2-set2:     [SKIP][382] ([Intel XE#2541]) -> [SKIP][383] ([Intel XE#1130] / [Intel XE#1201])
   [382]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_oa@buffer-fill.html
   [383]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_oa@buffer-fill.html

  * igt@xe_oa@mi-rpc:
    - shard-dg2-set2:     [SKIP][384] ([Intel XE#2541]) -> [SKIP][385] ([Intel XE#1201] / [Intel XE#2541]) +3 other tests skip
   [384]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_oa@mi-rpc.html
   [385]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-434/igt@xe_oa@mi-rpc.html

  * igt@xe_oa@non-sampling-read-error:
    - shard-dg2-set2:     [SKIP][386] ([Intel XE#1201] / [Intel XE#2541]) -> [SKIP][387] ([Intel XE#2541]) +2 other tests skip
   [386]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@xe_oa@non-sampling-read-error.html
   [387]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@xe_oa@non-sampling-read-error.html

  * igt@xe_oa@polling-small-buf:
    - shard-dg2-set2:     [SKIP][388] ([Intel XE#1201] / [Intel XE#2541]) -> [SKIP][389] ([Intel XE#1130] / [Intel XE#1201]) +8 other tests skip
   [388]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-463/igt@xe_oa@polling-small-buf.html
   [389]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_oa@polling-small-buf.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-dg2-set2:     [SKIP][390] ([Intel XE#1337]) -> [SKIP][391] ([Intel XE#1201] / [Intel XE#1337])
   [390]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_pat@display-vs-wb-transient.html
   [391]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-466/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-dg2-set2:     [SKIP][392] ([Intel XE#979]) -> [SKIP][393] ([Intel XE#1201] / [Intel XE#979])
   [392]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_pat@pat-index-xehpc.html
   [393]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-435/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_peer2peer@read:
    - shard-dg2-set2:     [FAIL][394] ([Intel XE#1173]) -> [SKIP][395] ([Intel XE#1061] / [Intel XE#1201])
   [394]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-436/igt@xe_peer2peer@read.html
   [395]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_peer2peer@read.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-dg2-set2:     [SKIP][396] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) -> [SKIP][397] ([Intel XE#1130] / [Intel XE#1201])
   [396]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-434/igt@xe_pm@d3cold-mmap-vram.html
   [397]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@d3cold-mocs:
    - shard-dg2-set2:     [SKIP][398] ([Intel XE#1201] / [Intel XE#2284]) -> [SKIP][399] ([Intel XE#1130] / [Intel XE#1201])
   [398]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@xe_pm@d3cold-mocs.html
   [399]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-dg2-set2:     [SKIP][400] ([Intel XE#1201] / [Intel XE#579]) -> [SKIP][401] ([Intel XE#1130] / [Intel XE#1201])
   [400]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-435/igt@xe_pm@vram-d3cold-threshold.html
   [401]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_query@multigpu-query-config:
    - shard-dg2-set2:     [SKIP][402] ([Intel XE#944]) -> [SKIP][403] ([Intel XE#1130] / [Intel XE#1201]) +1 other test skip
   [402]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_query@multigpu-query-config.html
   [403]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_query@multigpu-query-config.html

  * igt@xe_query@multigpu-query-engines:
    - shard-dg2-set2:     [SKIP][404] ([Intel XE#1201] / [Intel XE#944]) -> [SKIP][405] ([Intel XE#944]) +2 other tests skip
   [404]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-433/igt@xe_query@multigpu-query-engines.html
   [405]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-432/igt@xe_query@multigpu-query-engines.html

  * igt@xe_query@multigpu-query-topology:
    - shard-dg2-set2:     [SKIP][406] ([Intel XE#1201] / [Intel XE#944]) -> [SKIP][407] ([Intel XE#1130] / [Intel XE#1201]) +1 other test skip
   [406]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-466/igt@xe_query@multigpu-query-topology.html
   [407]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-436/igt@xe_query@multigpu-query-topology.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-dg2-set2:     [SKIP][408] ([Intel XE#944]) -> [SKIP][409] ([Intel XE#1201] / [Intel XE#944]) +2 other tests skip
   [408]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7993/shard-dg2-432/igt@xe_query@multigpu-query-uc-fw-version-huc.html
   [409]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/shard-dg2-434/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1000]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1000
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
  [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1149
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
  [Intel XE#1204]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1204
  [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
  [Intel XE#1430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1430
  [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
  [Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
  [Intel XE#1620]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1620
  [Intel XE#1649]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1649
  [Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1885]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1885
  [Intel XE#2105]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2105
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2249
  [Intel XE#2251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2251
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2318
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
  [Intel XE#2340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2340
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2364
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2436]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2436
  [Intel XE#2443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2443
  [Intel XE#2446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2446
  [Intel XE#2452]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2452
  [Intel XE#2472]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2472
  [Intel XE#2493]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2493
  [Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
  [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#623]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/623
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#783]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/783
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#827]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/827
  [Intel XE#829]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/829
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/958
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
  [i915#6077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6077


Build changes
-------------

  * IGT: IGT_7993 -> IGTPW_11647
  * Linux: xe-1832-0f7dbe16a23882ef9c928d9650ea0613925e710b -> xe-1837-2c3fbd94c8b2eda2275211dfa8ead639a4e3e161

  IGTPW_11647: 11647
  IGT_7993: 3b6b2d238e864ff1af9e33159d3bbf4b7f01d86d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1832-0f7dbe16a23882ef9c928d9650ea0613925e710b: 0f7dbe16a23882ef9c928d9650ea0613925e710b
  xe-1837-2c3fbd94c8b2eda2275211dfa8ead639a4e3e161: 2c3fbd94c8b2eda2275211dfa8ead639a4e3e161

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11647/index.html

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