[PATCH 00/25] Haswell fixes

[Eugeni Dodonov <eugeni.dodonov@intel.com>]

Hi,

Essentially those are the same patches as in the previous round, rebased on
yesterday's drm-intel-next-queued, and with the following comments and
suggestions from Daniel and Jesse addressed:

 - Added all the new DIP controls, and a switch into hsw_write_infoframe to
   properly write frame contents for each type (asked by Jesse, Daniel).
 - Rebased the interrupts handling code on top of drm-intel-next-queued (asked
   by Jesse).
 - Show an error message when we are trying to use FDI over HSW+PPT combination
   (this was not tested yet, so probably won't work anyway) (asked by Jesse,
   Daniel).
 - DDI module split clean-up to simplify patches reviewing (asked by Daniel).
 - Added a new intel_update_linetime_watermarks callback, to setup line time
   watermarks that are dependant on the mode clock settings; add a note about
   IPS watermarks which are not yet there (asked by Jesse).
 - Reworked iCLKIP clock setting to use algorithm for mode calculation instead
   of table, added checks for invalid values from Ben (thanks!!). WR PLL table
   is still there, but with an explicit comment saying that it is temporary and
   will go away at some point (asked pretty much everyone :))
 - Adapted to the latest HDMI infoframes changes in drm-intel-next.
 - Misc cleanups all around.

The CRT and higher level function separations for the LPT paths are not there.
There is only 1 way to use VGA output on Haswell, and only 1 DDI can work in
FDI mode for that, so I don't think it makes much sense adding specific
functions for that considering that the LPT-specific chunks are quite small. We
could simplify it later in the intel_display refactoring if the need arises.

Please review and comment, unless someone has any major concerns or issues with
those I'd like to have them merged to drm-intel-next, for wider testing and
availability!

Thanks,

Eugeni Dodonov (25):
  drm/i915: add new Haswell DIP controls registers
  drm/i915: reuse Ivy Bridge interrupts code for Haswell
  drm/i915: add support for SBI ops
  drm/i915: calculate watermarks for devices that have 3 pipes
  drm/i915: properly check for pipe count
  drm/i915: show unknown sdvox registers on hdmi init
  drm/i915: do not use fdi_normal_train on Haswell
  drm/i915: detect PCH encoders on Haswell
  drm/i915: enable power wells on Haswell init
  drm/i915: add LPT PCH checks
  drm/i915: handle DDI-related assertions
  drm/i915: account for only one PCH receiver on Haswell
  drm/i915: initialize DDI buffer translations
  drm/i915: support DDI training in FDI mode
  drm/i915: use ironlake eld write routine for Haswell
  drm/i915: define Haswell watermarks and clock gating
  drm/i915: program WM_LINETIME on Haswell
  drm/i915: disable pipe DDI function when disabling pipe
  drm/i915: program iCLKIP on Lynx Point
  drm/i915: detect digital outputs on Haswell
  drm/i915: add support for DDI-controlled digital outputs
  drm/i915: add WR PLL programming table
  drm/i915: move HDMI structs to shared location
  drm/i915: prepare HDMI link for Haswell
  drm/i915: hook Haswell devices in place

 drivers/char/agp/intel-agp.c         |    4 +
 drivers/gpu/drm/i915/Makefile        |    1 +
 drivers/gpu/drm/i915/i915_drv.c      |    7 +
 drivers/gpu/drm/i915/i915_drv.h      |    2 +
 drivers/gpu/drm/i915/i915_irq.c      |   11 +-
 drivers/gpu/drm/i915/i915_reg.h      |   36 ++
 drivers/gpu/drm/i915/intel_crt.c     |    6 +-
 drivers/gpu/drm/i915/intel_ddi.c     |  755 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  306 ++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h     |   29 +-
 drivers/gpu/drm/i915/intel_hdmi.c    |  107 ++++-
 drivers/gpu/drm/i915/intel_pm.c      |   87 +++-
 12 files changed, 1299 insertions(+), 52 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_ddi.c

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1.7.10