From: Eugeni Dodonov <eugeni.dodonov@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Eugeni Dodonov <eugeni.dodonov@intel.com>
Subject: [PATCH 24/25] drm/i915: prepare HDMI link for Haswell
Date: Wed, 9 May 2012 15:37:31 -0300 [thread overview]
Message-ID: <1336588652-702-25-git-send-email-eugeni.dodonov@intel.com> (raw)
In-Reply-To: <1336588652-702-1-git-send-email-eugeni.dodonov@intel.com>
On Haswell, we need to properly train the DDI buffers prior to enabling
HDMI, and enable the required clocks with correct dividers for the desired
frequency.
Also, we cannot simple reuse HDMI routines from previous generations of
GPU, as most of HDMI-specific stuff is being done via the DDI port
programming instead of HDMI-specific registers.
This commit take advantage of the WR PLL clock table which is in a
separate (previous) commit to select the right divisors for each mode.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 116 +++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 5 ++
drivers/gpu/drm/i915/intel_hdmi.c | 13 ++++-
3 files changed, 133 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d4b268e..46d1e88 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -637,3 +637,119 @@ static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
{297000, 2, 22, 20},
{298000, 2, 21, 19},
};
+
+void intel_ddi_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc = encoder->crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+ int port = intel_hdmi->ddi_port;
+ int pipe = intel_crtc->pipe;
+ int p, n2, r2, valid=0;
+ u32 temp, i;
+
+ /* On Haswell, we need to enable the clocks and prepare DDI function to
+ * work in HDMI mode for this pipe.
+ */
+ DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c, pipe %c\n", port_name(port), pipe_name(pipe));
+
+ for (i=0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++) {
+ if (crtc->mode.clock == wrpll_tmds_clock_table[i].clock) {
+ p = wrpll_tmds_clock_table[i].p;
+ n2 = wrpll_tmds_clock_table[i].n2;
+ r2 = wrpll_tmds_clock_table[i].r2;
+
+ DRM_DEBUG_KMS("WR PLL clock: found settings for %dKHz refresh rate: p=%d, n2=%d, r2=%d\n",
+ crtc->mode.clock,
+ p, n2, r2);
+
+ valid = 1;
+ break;
+ }
+ }
+
+ if (!valid) {
+ DRM_ERROR("Unable to find WR PLL clock settings for %dKHz refresh rate\n",
+ crtc->mode.clock);
+ return;
+ }
+
+ /* Enable LCPLL if disabled */
+ temp = I915_READ(LCPLL_CTL);
+ if (temp & LCPLL_PLL_DISABLE)
+ I915_WRITE(LCPLL_CTL,
+ temp & ~LCPLL_PLL_DISABLE);
+
+ /* Configure WR PLL 1, program the correct divider values for
+ * the desired frequency and wait for warmup */
+ I915_WRITE(WRPLL_CTL1,
+ WRPLL_PLL_ENABLE |
+ WRPLL_PLL_SELECT_LCPLL_2700 |
+ WRPLL_DIVIDER_REFERENCE(r2) |
+ WRPLL_DIVIDER_FEEDBACK(n2) |
+ WRPLL_DIVIDER_POST(p));
+
+ udelay(20);
+
+ /* Use WRPLL1 clock to drive the output to the port, and tell the pipe to use
+ * this port for connection.
+ */
+ I915_WRITE(PORT_CLK_SEL(port),
+ PORT_CLK_SEL_WRPLL1);
+ I915_WRITE(PIPE_CLK_SEL(pipe),
+ PIPE_CLK_SEL_PORT(port));
+
+ udelay(20);
+
+ if (intel_hdmi->has_audio) {
+ /* Proper support for digital audio needs a new logic and a new set
+ * of registers, so we leave it for future patch bombing.
+ */
+ DRM_DEBUG_DRIVER("HDMI audio on pipe %c not yet supported on DDI\n",
+ pipe_name(intel_crtc->pipe));
+ }
+
+ /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
+ temp = I915_READ(DDI_FUNC_CTL(pipe));
+ temp &= ~PIPE_DDI_PORT_MASK;
+ temp &= ~PIPE_DDI_BPC_12;
+ temp |= PIPE_DDI_SELECT_PORT(port) |
+ PIPE_DDI_MODE_SELECT_HDMI |
+ ((intel_crtc->bpp > 24) ?
+ PIPE_DDI_BPC_12 :
+ PIPE_DDI_BPC_8) |
+ PIPE_DDI_FUNC_ENABLE;
+
+ I915_WRITE(DDI_FUNC_CTL(pipe), temp);
+
+ intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
+ intel_hdmi_set_spd_infoframe(encoder);
+}
+
+void intel_ddi_dpms(struct drm_encoder *encoder, int mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+ int port = intel_hdmi->ddi_port;
+ u32 temp;
+
+ temp = I915_READ(DDI_BUF_CTL(port));
+
+ if (mode != DRM_MODE_DPMS_ON) {
+ temp &= ~DDI_BUF_CTL_ENABLE;
+ } else {
+ temp |= DDI_BUF_CTL_ENABLE;
+ }
+
+ /* Enable DDI_BUF_CTL. In HDMI/DVI mode, the port width,
+ * and swing/emphasis values are ignored so nothing special needs
+ * to be done besides enabling the port.
+ */
+ I915_WRITE(DDI_BUF_CTL(port),
+ temp);
+}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index afdd74f..d51f27f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -497,4 +497,9 @@ extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
extern void gen6_disable_rps(struct drm_device *dev);
extern void intel_init_emon(struct drm_device *dev);
+extern void intel_ddi_dpms(struct drm_encoder *encoder, int mode);
+extern void intel_ddi_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode);
+
#endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 77c92fb..8a7ca7d 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -612,6 +612,14 @@ static void intel_hdmi_destroy(struct drm_connector *connector)
kfree(connector);
}
+static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
+ .dpms = intel_ddi_dpms,
+ .mode_fixup = intel_hdmi_mode_fixup,
+ .prepare = intel_encoder_prepare,
+ .mode_set = intel_ddi_mode_set,
+ .commit = intel_encoder_commit,
+};
+
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
.dpms = intel_hdmi_dpms,
.mode_fixup = intel_hdmi_mode_fixup,
@@ -751,7 +759,10 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
I915_WRITE(TVIDEO_DIP_CTL(i), 0);
}
- drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
+ if (IS_HASWELL(dev))
+ drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
+ else
+ drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
intel_hdmi_add_properties(intel_hdmi, connector);
--
1.7.10
next prev parent reply other threads:[~2012-05-09 18:41 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-09 18:37 [PATCH 00/25] Haswell fixes Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 01/25] drm/i915: add new Haswell DIP controls registers Eugeni Dodonov
2012-05-10 0:34 ` Paulo Zanoni
2012-05-10 1:02 ` Eugeni Dodonov
2012-05-10 3:03 ` Paulo Zanoni
2012-05-10 8:32 ` Daniel Vetter
2012-05-10 13:18 ` Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 02/25] drm/i915: reuse Ivy Bridge interrupts code for Haswell Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 03/25] drm/i915: add support for SBI ops Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 04/25] drm/i915: calculate watermarks for devices that have 3 pipes Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 05/25] drm/i915: properly check for pipe count Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 06/25] drm/i915: show unknown sdvox registers on hdmi init Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 07/25] drm/i915: do not use fdi_normal_train on Haswell Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 08/25] drm/i915: detect PCH encoders " Eugeni Dodonov
2012-05-09 21:46 ` Daniel Vetter
2012-05-09 23:30 ` Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 09/25] drm/i915: enable power wells on Haswell init Eugeni Dodonov
2012-05-09 21:42 ` Daniel Vetter
2012-05-09 23:29 ` Eugeni Dodonov
2012-05-10 14:48 ` Daniel Vetter
2012-05-10 15:08 ` Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 10/25] drm/i915: add LPT PCH checks Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 11/25] drm/i915: handle DDI-related assertions Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 12/25] drm/i915: account for only one PCH receiver on Haswell Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 13/25] drm/i915: initialize DDI buffer translations Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 14/25] drm/i915: support DDI training in FDI mode Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 15/25] drm/i915: use ironlake eld write routine for Haswell Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 16/25] drm/i915: define Haswell watermarks and clock gating Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 17/25] drm/i915: program WM_LINETIME on Haswell Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 18/25] drm/i915: disable pipe DDI function when disabling pipe Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 19/25] drm/i915: program iCLKIP on Lynx Point Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 20/25] drm/i915: detect digital outputs on Haswell Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 21/25] drm/i915: add support for DDI-controlled digital outputs Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 22/25] drm/i915: add WR PLL programming table Eugeni Dodonov
2012-05-09 18:37 ` [PATCH 23/25] drm/i915: move HDMI structs to shared location Eugeni Dodonov
2012-05-09 22:05 ` Daniel Vetter
2012-05-09 18:37 ` Eugeni Dodonov [this message]
2012-05-09 18:37 ` [PATCH 25/25] drm/i915: hook Haswell devices in place Eugeni Dodonov
2012-05-10 15:56 ` Daniel Vetter
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