* [PATCH 01/14] drm/i915: add TRANSCODER_EDP
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 22:00 ` Daniel Vetter
2012-10-18 21:21 ` [PATCH 02/14] drm/i915: convert PIPE_CLK_SEL to transcoder Paulo Zanoni
` (12 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Before Haswell we used to have the CPU pipes and the PCH transcoders.
We had the same amount of pipes and transcoders, and there was a 1:1
mapping between them. After Haswell what we used to call CPU pipe was
split into CPU pipe and CPU transcoder. So now we have 3 CPU pipes (A,
B and C), 4 CPU transcoders (A, B, C and EDP) and 1 PCH transcoder
(only used for VGA).
For all the outputs except for EDP we have an 1:1 mapping on the CPU
pipes and CPU transcoders, so if you're using CPU pipe A you have to
use CPU transcoder A. When have an eDP output you have to use
transcoder EDP and you can attach this CPU transcoder to any of the 3
CPU pipes. When using VGA you need to select a pair of matching CPU
pipes/transcoders (A/A, B/B, C/C) and you also need to enable/use the
PCH transcoder.
For now we're just creating the cpu_transcoder definitions and setting
cpu_transcoder to TRANSCODER_EDP on DDI eDP code, but none of the
registers was ported to use transcoder instead of pipe. The goal is to
keep the code backwards-compatible since on all cases except when
using eDP we must have pipe == cpu_transcoder.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
4 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4728d30..922ab8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -58,6 +58,14 @@ enum pipe {
};
#define pipe_name(p) ((p) + 'A')
+enum transcoder {
+ TRANSCODER_A = 0,
+ TRANSCODER_B,
+ TRANSCODER_C,
+ TRANSCODER_EDP = 0xF,
+};
+#define transcoder_name(t) ((t) + 'A')
+
enum plane {
PLANE_A = 0,
PLANE_B,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c31ee5b..c3fd536 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
#define _I915_REG_H_
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c2c219b..6bf5ea8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -927,6 +927,15 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
return true;
}
+enum transcoder pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ return intel_crtc->cpu_transcoder;
+}
+
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3336,6 +3345,9 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
static void haswell_crtc_off(struct drm_crtc *crtc)
{
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ intel_crtc->cpu_transcoder = intel_crtc->pipe;
intel_ddi_put_crtc_pll(crtc);
}
@@ -5212,6 +5224,11 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
num_connectors++;
}
+ if (is_cpu_edp)
+ intel_crtc->cpu_transcoder = TRANSCODER_EDP;
+ else
+ intel_crtc->cpu_transcoder = pipe;
+
/* We are not sure yet this won't happen. */
WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
INTEL_PCH_TYPE(dev));
@@ -7770,6 +7787,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
/* Swap pipes & planes for FBC on pre-965 */
intel_crtc->pipe = pipe;
intel_crtc->plane = pipe;
+ intel_crtc->cpu_transcoder = pipe;
if (IS_MOBILE(dev) && IS_GEN3(dev)) {
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
intel_crtc->plane = !pipe;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 95cbd67..8f6eee5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -185,6 +185,7 @@ struct intel_crtc {
struct drm_crtc base;
enum pipe pipe;
enum plane plane;
+ enum transcoder cpu_transcoder;
u8 lut_r[256], lut_g[256], lut_b[256];
/*
* Whether the crtc and the connected output pipeline is active. Implies
@@ -491,6 +492,8 @@ extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
struct drm_crtc *crtc);
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+extern enum transcoder pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
+ enum pipe pipe);
extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 01/14] drm/i915: add TRANSCODER_EDP
2012-10-18 21:21 ` [PATCH 01/14] drm/i915: add TRANSCODER_EDP Paulo Zanoni
@ 2012-10-18 22:00 ` Daniel Vetter
0 siblings, 0 replies; 22+ messages in thread
From: Daniel Vetter @ 2012-10-18 22:00 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Thu, Oct 18, 2012 at 06:21:31PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Before Haswell we used to have the CPU pipes and the PCH transcoders.
> We had the same amount of pipes and transcoders, and there was a 1:1
> mapping between them. After Haswell what we used to call CPU pipe was
> split into CPU pipe and CPU transcoder. So now we have 3 CPU pipes (A,
> B and C), 4 CPU transcoders (A, B, C and EDP) and 1 PCH transcoder
> (only used for VGA).
>
> For all the outputs except for EDP we have an 1:1 mapping on the CPU
> pipes and CPU transcoders, so if you're using CPU pipe A you have to
> use CPU transcoder A. When have an eDP output you have to use
> transcoder EDP and you can attach this CPU transcoder to any of the 3
> CPU pipes. When using VGA you need to select a pair of matching CPU
> pipes/transcoders (A/A, B/B, C/C) and you also need to enable/use the
> PCH transcoder.
>
> For now we're just creating the cpu_transcoder definitions and setting
> cpu_transcoder to TRANSCODER_EDP on DDI eDP code, but none of the
> registers was ported to use transcoder instead of pipe. The goal is to
> keep the code backwards-compatible since on all cases except when
> using eDP we must have pipe == cpu_transcoder.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> 4 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4728d30..922ab8d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -58,6 +58,14 @@ enum pipe {
> };
> #define pipe_name(p) ((p) + 'A')
>
> +enum transcoder {
> + TRANSCODER_A = 0,
> + TRANSCODER_B,
> + TRANSCODER_C,
> + TRANSCODER_EDP = 0xF,
> +};
> +#define transcoder_name(t) ((t) + 'A')
> +
> enum plane {
> PLANE_A = 0,
> PLANE_B,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c31ee5b..c3fd536 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -26,6 +26,7 @@
> #define _I915_REG_H_
>
> #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
> +#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
>
> #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c2c219b..6bf5ea8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -927,6 +927,15 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
> return true;
> }
>
> +enum transcoder pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> + enum pipe pipe)
> +{
> + struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + return intel_crtc->cpu_transcoder;
> +}
We need int intel_ prefix on this to avoid polluting the global namespace.
-Daniel
> +
> static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3336,6 +3345,9 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
>
> static void haswell_crtc_off(struct drm_crtc *crtc)
> {
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + intel_crtc->cpu_transcoder = intel_crtc->pipe;
> intel_ddi_put_crtc_pll(crtc);
> }
>
> @@ -5212,6 +5224,11 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
> num_connectors++;
> }
>
> + if (is_cpu_edp)
> + intel_crtc->cpu_transcoder = TRANSCODER_EDP;
> + else
> + intel_crtc->cpu_transcoder = pipe;
> +
> /* We are not sure yet this won't happen. */
> WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
> INTEL_PCH_TYPE(dev));
> @@ -7770,6 +7787,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
> /* Swap pipes & planes for FBC on pre-965 */
> intel_crtc->pipe = pipe;
> intel_crtc->plane = pipe;
> + intel_crtc->cpu_transcoder = pipe;
> if (IS_MOBILE(dev) && IS_GEN3(dev)) {
> DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
> intel_crtc->plane = !pipe;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 95cbd67..8f6eee5 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -185,6 +185,7 @@ struct intel_crtc {
> struct drm_crtc base;
> enum pipe pipe;
> enum plane plane;
> + enum transcoder cpu_transcoder;
> u8 lut_r[256], lut_g[256], lut_b[256];
> /*
> * Whether the crtc and the connected output pipeline is active. Implies
> @@ -491,6 +492,8 @@ extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
> struct drm_crtc *crtc);
> int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
> struct drm_file *file_priv);
> +extern enum transcoder pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> + enum pipe pipe);
> extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
> extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
>
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 02/14] drm/i915: convert PIPE_CLK_SEL to transcoder
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
2012-10-18 21:21 ` [PATCH 01/14] drm/i915: add TRANSCODER_EDP Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 21:21 ` [PATCH 03/14] drm/i915: convert DDI_FUNC_CTL " Paulo Zanoni
` (11 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
This register appeared in Haswell. It does not have an EDP version
because the EDP transcoder is always tied to the DDIA clock. Notice
that if we call PIPE_CLK_SEL(pipe) when pipe is PIPE_A and transcoder
is TRANSCODER_EDP we might introduce a bug, that's why this is a
transcoder register even though it does not have an EDP version.
Even though Haswell names this register PIPE_CLK_SEL, it will be
renamed to TRANS_CLK_SEL in the future, so let's just start using the
real name that makes more sense and avoids misusage.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
drivers/gpu/drm/i915/intel_ddi.c | 10 ++++++++--
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3fd536..32cad88 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4539,13 +4539,13 @@
#define PORT_CLK_SEL_WRPLL2 (5<<29)
#define PORT_CLK_SEL_NONE (7<<29)
-/* Pipe clock selection */
-#define PIPE_CLK_SEL_A 0x46140
-#define PIPE_CLK_SEL_B 0x46144
-#define PIPE_CLK_SEL(pipe) _PIPE(pipe, PIPE_CLK_SEL_A, PIPE_CLK_SEL_B)
-/* For each pipe, we need to select the corresponding port clock */
-#define PIPE_CLK_SEL_DISABLED (0x0<<29)
-#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
+/* Transcoder clock selection */
+#define TRANS_CLK_SEL_A 0x46140
+#define TRANS_CLK_SEL_B 0x46144
+#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
+/* For each transcoder, we need to select the corresponding port clock */
+#define TRANS_CLK_SEL_DISABLED (0x0<<29)
+#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
#define _PIPEA_MSA_MISC 0x60410
#define _PIPEB_MSA_MISC 0x61410
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 81cca48..f568862 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1095,15 +1095,21 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
- I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_PORT(port));
+ if (cpu_transcoder != TRANSCODER_EDP)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_PORT(port));
}
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
- I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_DISABLED);
+ if (cpu_transcoder != TRANSCODER_EDP)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_DISABLED);
}
void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 03/14] drm/i915: convert DDI_FUNC_CTL to transcoder
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
2012-10-18 21:21 ` [PATCH 01/14] drm/i915: add TRANSCODER_EDP Paulo Zanoni
2012-10-18 21:21 ` [PATCH 02/14] drm/i915: convert PIPE_CLK_SEL to transcoder Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 21:21 ` [PATCH 04/14] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state Paulo Zanoni
` (10 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Because there's one instance of the register per CPU transcoder and
not per CPU pipe. This is another register that appeared for the first
time on Haswell, and even though its Haswell name is
PIPE_DDI_FUNC_CTL, it will be renamed to TRANS_DDI_FUNC_CTL, so let's
just use the new naming scheme before it confuses more people.
Notice that there's a big improvement on intel_ddi_get_hw_state due to
the new TRANSCODER_EDP.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 59 +++++++++++----------
drivers/gpu/drm/i915/intel_ddi.c | 100 ++++++++++++++++++++++-------------
drivers/gpu/drm/i915/intel_display.c | 8 +--
drivers/gpu/drm/i915/intel_drv.h | 4 +-
4 files changed, 102 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 32cad88..72a61b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4395,34 +4395,39 @@
#define HSW_PWR_WELL_CTL6 0x45414
/* Per-pipe DDI Function Control */
-#define PIPE_DDI_FUNC_CTL_A 0x60400
-#define PIPE_DDI_FUNC_CTL_B 0x61400
-#define PIPE_DDI_FUNC_CTL_C 0x62400
-#define PIPE_DDI_FUNC_CTL_EDP 0x6F400
-#define DDI_FUNC_CTL(pipe) _PIPE(pipe, PIPE_DDI_FUNC_CTL_A, \
- PIPE_DDI_FUNC_CTL_B)
-#define PIPE_DDI_FUNC_ENABLE (1<<31)
+#define TRANS_DDI_FUNC_CTL_A 0x60400
+#define TRANS_DDI_FUNC_CTL_B 0x61400
+#define TRANS_DDI_FUNC_CTL_C 0x62400
+#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
+#define DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
+ TRANS_DDI_FUNC_CTL_B)
+#define TRANS_DDI_FUNC_ENABLE (1<<31)
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
-#define PIPE_DDI_PORT_MASK (7<<28)
-#define PIPE_DDI_SELECT_PORT(x) ((x)<<28)
-#define PIPE_DDI_PORT_NONE (0<<28)
-#define PIPE_DDI_MODE_SELECT_MASK (7<<24)
-#define PIPE_DDI_MODE_SELECT_HDMI (0<<24)
-#define PIPE_DDI_MODE_SELECT_DVI (1<<24)
-#define PIPE_DDI_MODE_SELECT_DP_SST (2<<24)
-#define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
-#define PIPE_DDI_MODE_SELECT_FDI (4<<24)
-#define PIPE_DDI_BPC_MASK (7<<20)
-#define PIPE_DDI_BPC_8 (0<<20)
-#define PIPE_DDI_BPC_10 (1<<20)
-#define PIPE_DDI_BPC_6 (2<<20)
-#define PIPE_DDI_BPC_12 (3<<20)
-#define PIPE_DDI_PVSYNC (1<<17)
-#define PIPE_DDI_PHSYNC (1<<16)
-#define PIPE_DDI_BFI_ENABLE (1<<4)
-#define PIPE_DDI_PORT_WIDTH_X1 (0<<1)
-#define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
-#define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
+#define TRANS_DDI_PORT_MASK (7<<28)
+#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
+#define TRANS_DDI_PORT_NONE (0<<28)
+#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
+#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
+#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
+#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
+#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
+#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
+#define TRANS_DDI_BPC_MASK (7<<20)
+#define TRANS_DDI_BPC_8 (0<<20)
+#define TRANS_DDI_BPC_10 (1<<20)
+#define TRANS_DDI_BPC_6 (2<<20)
+#define TRANS_DDI_BPC_12 (3<<20)
+#define TRANS_DDI_PVSYNC (1<<17)
+#define TRANS_DDI_PHSYNC (1<<16)
+#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
+#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
+#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
+#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
+#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
+#define TRANS_DDI_BFI_ENABLE (1<<4)
+#define TRANS_DDI_PORT_WIDTH_X1 (0<<1)
+#define TRANS_DDI_PORT_WIDTH_X2 (1<<1)
+#define TRANS_DDI_PORT_WIDTH_X4 (3<<1)
/* DisplayPort Transport Control */
#define DP_TP_CTL_A 0x64040
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f568862..8d3ce3a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -924,68 +924,69 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
int type = intel_encoder->type;
uint32_t temp;
- /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
- temp = PIPE_DDI_FUNC_ENABLE;
+ /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
+ temp = TRANS_DDI_FUNC_ENABLE;
switch (intel_crtc->bpp) {
case 18:
- temp |= PIPE_DDI_BPC_6;
+ temp |= TRANS_DDI_BPC_6;
break;
case 24:
- temp |= PIPE_DDI_BPC_8;
+ temp |= TRANS_DDI_BPC_8;
break;
case 30:
- temp |= PIPE_DDI_BPC_10;
+ temp |= TRANS_DDI_BPC_10;
break;
case 36:
- temp |= PIPE_DDI_BPC_12;
+ temp |= TRANS_DDI_BPC_12;
break;
default:
- WARN(1, "%d bpp unsupported by pipe DDI function\n",
+ WARN(1, "%d bpp unsupported by transcoder DDI function\n",
intel_crtc->bpp);
}
if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
- temp |= PIPE_DDI_PVSYNC;
+ temp |= TRANS_DDI_PVSYNC;
if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
- temp |= PIPE_DDI_PHSYNC;
+ temp |= TRANS_DDI_PHSYNC;
if (type == INTEL_OUTPUT_HDMI) {
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
if (intel_hdmi->has_hdmi_sink)
- temp |= PIPE_DDI_MODE_SELECT_HDMI;
+ temp |= TRANS_DDI_MODE_SELECT_HDMI;
else
- temp |= PIPE_DDI_MODE_SELECT_DVI;
+ temp |= TRANS_DDI_MODE_SELECT_DVI;
- temp |= PIPE_DDI_SELECT_PORT(intel_hdmi->ddi_port);
+ temp |= TRANS_DDI_SELECT_PORT(intel_hdmi->ddi_port);
} else if (type == INTEL_OUTPUT_ANALOG) {
- temp |= PIPE_DDI_MODE_SELECT_FDI;
- temp |= PIPE_DDI_SELECT_PORT(PORT_E);
+ temp |= TRANS_DDI_MODE_SELECT_FDI;
+ temp |= TRANS_DDI_SELECT_PORT(PORT_E);
} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- temp |= PIPE_DDI_MODE_SELECT_DP_SST;
- temp |= PIPE_DDI_SELECT_PORT(intel_dp->port);
+ temp |= TRANS_DDI_MODE_SELECT_DP_SST;
+ temp |= TRANS_DDI_SELECT_PORT(intel_dp->port);
switch (intel_dp->lane_count) {
case 1:
- temp |= PIPE_DDI_PORT_WIDTH_X1;
+ temp |= TRANS_DDI_PORT_WIDTH_X1;
break;
case 2:
- temp |= PIPE_DDI_PORT_WIDTH_X2;
+ temp |= TRANS_DDI_PORT_WIDTH_X2;
break;
case 4:
- temp |= PIPE_DDI_PORT_WIDTH_X4;
+ temp |= TRANS_DDI_PORT_WIDTH_X4;
break;
default:
- temp |= PIPE_DDI_PORT_WIDTH_X4;
+ temp |= TRANS_DDI_PORT_WIDTH_X4;
WARN(1, "Unsupported lane count %d\n",
intel_dp->lane_count);
}
@@ -995,17 +996,17 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
intel_encoder->type, pipe);
}
- I915_WRITE(DDI_FUNC_CTL(pipe), temp);
+ I915_WRITE(DDI_FUNC_CTL(cpu_transcoder), temp);
}
-void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
- enum pipe pipe)
+void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder)
{
- uint32_t reg = DDI_FUNC_CTL(pipe);
+ uint32_t reg = DDI_FUNC_CTL(cpu_transcoder);
uint32_t val = I915_READ(reg);
- val &= ~(PIPE_DDI_FUNC_ENABLE | PIPE_DDI_PORT_MASK);
- val |= PIPE_DDI_PORT_NONE;
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
+ val |= TRANS_DDI_PORT_NONE;
I915_WRITE(reg, val);
}
@@ -1023,13 +1024,32 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
if (!(tmp & DDI_BUF_CTL_ENABLE))
return false;
- for_each_pipe(i) {
- tmp = I915_READ(DDI_FUNC_CTL(i));
+ if (port == PORT_A) {
+ tmp = I915_READ(DDI_FUNC_CTL(TRANSCODER_EDP));
- if ((tmp & PIPE_DDI_PORT_MASK)
- == PIPE_DDI_SELECT_PORT(port)) {
- *pipe = i;
- return true;
+ switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+ case TRANS_DDI_EDP_INPUT_A_ON:
+ case TRANS_DDI_EDP_INPUT_A_ONOFF:
+ *pipe = PIPE_A;
+ break;
+ case TRANS_DDI_EDP_INPUT_B_ONOFF:
+ *pipe = PIPE_B;
+ break;
+ case TRANS_DDI_EDP_INPUT_C_ONOFF:
+ *pipe = PIPE_C;
+ break;
+ }
+
+ return true;
+ } else {
+ for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
+ tmp = I915_READ(DDI_FUNC_CTL(i));
+
+ if ((tmp & TRANS_DDI_PORT_MASK)
+ == TRANS_DDI_SELECT_PORT(port)) {
+ *pipe = i;
+ return true;
+ }
}
}
@@ -1043,13 +1063,19 @@ static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
{
uint32_t temp, ret;
enum port port;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
int i;
- temp = I915_READ(DDI_FUNC_CTL(pipe));
- temp &= PIPE_DDI_PORT_MASK;
- for (i = PORT_A; i <= PORT_E; i++)
- if (temp == PIPE_DDI_SELECT_PORT(i))
- port = i;
+ if (cpu_transcoder == TRANSCODER_EDP) {
+ port = PORT_A;
+ } else {
+ temp = I915_READ(DDI_FUNC_CTL(cpu_transcoder));
+ temp &= TRANS_DDI_PORT_MASK;
+
+ for (i = PORT_B; i <= PORT_E; i++)
+ if (temp == TRANS_DDI_SELECT_PORT(i))
+ port = i;
+ }
ret = I915_READ(PORT_CLK_SEL(port));
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6bf5ea8..73ce007 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1112,12 +1112,13 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
int reg;
u32 val;
bool cur_state;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
if (IS_HASWELL(dev_priv->dev)) {
/* On Haswell, DDI is used instead of FDI_TX_CTL */
- reg = DDI_FUNC_CTL(pipe);
+ reg = DDI_FUNC_CTL(cpu_transcoder);
val = I915_READ(reg);
- cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
+ cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
} else {
reg = FDI_TX_CTL(pipe);
val = I915_READ(reg);
@@ -3259,6 +3260,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe;
int plane = intel_crtc->plane;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
u32 reg, temp;
@@ -3280,7 +3282,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
intel_disable_pipe(dev_priv, pipe);
if (IS_HASWELL(dev))
- intel_ddi_disable_pipe_func(dev_priv, pipe);
+ intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
/* Disable PF */
I915_WRITE(PF_CTL(pipe), 0);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8f6eee5..5bc1ddd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -595,8 +595,8 @@ extern void intel_ddi_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *adjusted_mode);
extern void intel_ddi_pll_init(struct drm_device *dev);
extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
-extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
- enum pipe pipe);
+extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder);
extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 04/14] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (2 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 03/14] drm/i915: convert DDI_FUNC_CTL " Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 22:02 ` Daniel Vetter
2012-10-18 21:21 ` [PATCH 05/14] drm/i915: convert PIPECONF to use transcoder instead of pipe Paulo Zanoni
` (9 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
We need to check if any of the pipes is using TRANSCODER_EDP.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 73ce007..827c5ba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8551,6 +8551,31 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
struct intel_encoder *encoder;
struct intel_connector *connector;
+ if (IS_HASWELL(dev)) {
+ tmp = I915_READ(DDI_FUNC_CTL(TRANSCODER_EDP));
+
+ if (tmp & TRANS_DDI_FUNC_ENABLE) {
+ switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+ case TRANS_DDI_EDP_INPUT_A_ON:
+ case TRANS_DDI_EDP_INPUT_A_ONOFF:
+ pipe = PIPE_A;
+ break;
+ case TRANS_DDI_EDP_INPUT_B_ONOFF:
+ pipe = PIPE_B;
+ break;
+ case TRANS_DDI_EDP_INPUT_C_ONOFF:
+ pipe = PIPE_C;
+ break;
+ }
+
+ crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+ crtc->cpu_transcoder = TRANSCODER_EDP;
+
+ DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
+ pipe_name(pipe));
+ }
+ }
+
for_each_pipe(pipe) {
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 04/14] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state
2012-10-18 21:21 ` [PATCH 04/14] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state Paulo Zanoni
@ 2012-10-18 22:02 ` Daniel Vetter
2012-10-19 19:30 ` Paulo Zanoni
0 siblings, 1 reply; 22+ messages in thread
From: Daniel Vetter @ 2012-10-18 22:02 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Thu, Oct 18, 2012 at 06:21:34PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> We need to check if any of the pipes is using TRANSCODER_EDP.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
I wonder whether it doesn't make more sense for haswell to return the
transcoder in the encoder->get_hw_state function, and then map that to the
crtc with the intel_pipe_to_cpu_transcoder. That way we don't need to add
a special-case for eDP.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 73ce007..827c5ba 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8551,6 +8551,31 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
> struct intel_encoder *encoder;
> struct intel_connector *connector;
>
> + if (IS_HASWELL(dev)) {
> + tmp = I915_READ(DDI_FUNC_CTL(TRANSCODER_EDP));
> +
> + if (tmp & TRANS_DDI_FUNC_ENABLE) {
> + switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> + case TRANS_DDI_EDP_INPUT_A_ON:
> + case TRANS_DDI_EDP_INPUT_A_ONOFF:
> + pipe = PIPE_A;
> + break;
> + case TRANS_DDI_EDP_INPUT_B_ONOFF:
> + pipe = PIPE_B;
> + break;
> + case TRANS_DDI_EDP_INPUT_C_ONOFF:
> + pipe = PIPE_C;
> + break;
> + }
> +
> + crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> + crtc->cpu_transcoder = TRANSCODER_EDP;
> +
> + DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
> + pipe_name(pipe));
> + }
> + }
> +
> for_each_pipe(pipe) {
> crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 04/14] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state
2012-10-18 22:02 ` Daniel Vetter
@ 2012-10-19 19:30 ` Paulo Zanoni
0 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-19 19:30 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Paulo Zanoni
Hi
2012/10/18 Daniel Vetter <daniel@ffwll.ch>:
> On Thu, Oct 18, 2012 at 06:21:34PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> We need to check if any of the pipes is using TRANSCODER_EDP.
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> I wonder whether it doesn't make more sense for haswell to return the
> transcoder in the encoder->get_hw_state function, and then map that to the
> crtc with the intel_pipe_to_cpu_transcoder. That way we don't need to add
> a special-case for eDP.
I know we had some IRC discussions about this comment, but after this
I tried to implement your suggestion. It won't work unless we
completely rewrite a lot of code. For example, on
intel_modeset_setup_hw_state (the function this patch changes) we need
to know which transcoder is associated to the pipe before doing
I915_READ(PIPECONF(pipe)) (because PIPECONF(pipe) is wrong, we need
PIPECONF(cpu_transcoder), which comes later in the patch series), so
we will need to discover the encoder state before discovering the pipe
state, which is not what we do now. Also, having
dev_priv->transcoder_to_pipe_mapping is not as clean as having
pipe_to_transcoder_mapping because every pipe is always associated
with a transcoder, but not every transcoder is associated to a pipe,
so we'd need to keep checking for NULL on unused transcoders.
My first strategy to implement this code also tried to use
"for_each_transcoder" instead of "for_each_pipe" when checking the
pipe state, but it added even more complexity to the function.
I really believe my approach here is as KISS as we can get. A single
special haswell case here prevents a lot of "is this cpu transcoder
being used by some pipe?" checks in a lot of places.
> -Daniel
>
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
>> 1 file changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 73ce007..827c5ba 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -8551,6 +8551,31 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
>> struct intel_encoder *encoder;
>> struct intel_connector *connector;
>>
>> + if (IS_HASWELL(dev)) {
>> + tmp = I915_READ(DDI_FUNC_CTL(TRANSCODER_EDP));
>> +
>> + if (tmp & TRANS_DDI_FUNC_ENABLE) {
>> + switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
>> + case TRANS_DDI_EDP_INPUT_A_ON:
>> + case TRANS_DDI_EDP_INPUT_A_ONOFF:
>> + pipe = PIPE_A;
>> + break;
>> + case TRANS_DDI_EDP_INPUT_B_ONOFF:
>> + pipe = PIPE_B;
>> + break;
>> + case TRANS_DDI_EDP_INPUT_C_ONOFF:
>> + pipe = PIPE_C;
>> + break;
>> + }
>> +
>> + crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>> + crtc->cpu_transcoder = TRANSCODER_EDP;
>> +
>> + DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
>> + pipe_name(pipe));
>> + }
>> + }
>> +
>> for_each_pipe(pipe) {
>> crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>>
>> --
>> 1.7.11.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 05/14] drm/i915: convert PIPECONF to use transcoder instead of pipe
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (3 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 04/14] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 22:23 ` Daniel Vetter
2012-10-18 21:21 ` [PATCH 06/14] drm/i915: convert PIPE_MSA_MISC to transcoder Paulo Zanoni
` (8 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Because the PIPECONF register is actually part of the CPU transcoder,
not the CPU pipe.
Ideally we would also rename PIPECONF to TRANSCONF to remind people
that they should use the transcoder instead of the pipe, but let's
keep it like this for now since most Gens still name it PIPECONF.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_crt.c | 6 ++--
drivers/gpu/drm/i915/intel_display.c | 61 ++++++++++++++++++++++--------------
drivers/gpu/drm/i915/intel_sprite.c | 3 +-
drivers/gpu/drm/i915/intel_tv.c | 4 +--
6 files changed, 49 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d07c787..c9b186d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -123,7 +123,9 @@ static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
- return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
+
+ return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
}
/* Called from drm generic code, passed a 'crtc', which
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72a61b5..9fecd3b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2714,7 +2714,7 @@
#define PIPE_12BPC (3 << 5)
#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
-#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
+#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 53f3e87..2a2c976 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -467,7 +467,9 @@ intel_crt_load_detect(struct intel_crt *crt)
{
struct drm_device *dev = crt->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crt->base.base.crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
uint32_t save_bclrpat;
uint32_t save_vtotal;
uint32_t vtotal, vactive;
@@ -489,7 +491,7 @@ intel_crt_load_detect(struct intel_crt *crt)
vtotal_reg = VTOTAL(pipe);
vblank_reg = VBLANK(pipe);
vsync_reg = VSYNC(pipe);
- pipeconf_reg = PIPECONF(pipe);
+ pipeconf_reg = PIPECONF(cpu_transcoder);
pipe_dsl_reg = PIPEDSL(pipe);
save_bclrpat = I915_READ(bclrpat_reg);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 827c5ba..dc93c39 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1008,9 +1008,10 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
if (INTEL_INFO(dev)->gen >= 4) {
- int reg = PIPECONF(pipe);
+ int reg = PIPECONF(cpu_transcoder);
/* Wait for the Pipe State to go off */
if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
@@ -1222,12 +1223,13 @@ void assert_pipe(struct drm_i915_private *dev_priv,
int reg;
u32 val;
bool cur_state;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
/* if we need the pipe A quirk it must be always on */
if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
state = true;
- reg = PIPECONF(pipe);
+ reg = PIPECONF(cpu_transcoder);
val = I915_READ(reg);
cur_state = !!(val & PIPECONF_ENABLE);
WARN(cur_state != state,
@@ -1661,6 +1663,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
int reg;
u32 val, pipeconf_val;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
@@ -1680,7 +1683,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
}
reg = TRANSCONF(pipe);
val = I915_READ(reg);
- pipeconf_val = I915_READ(PIPECONF(pipe));
+ pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
if (HAS_PCH_IBX(dev_priv->dev)) {
/*
@@ -1745,6 +1748,7 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
bool pch_port)
{
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
int reg;
u32 val;
@@ -1764,7 +1768,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
/* FIXME: assert CPU port conditions for SNB+ */
}
- reg = PIPECONF(pipe);
+ reg = PIPECONF(cpu_transcoder);
val = I915_READ(reg);
if (val & PIPECONF_ENABLE)
return;
@@ -1788,6 +1792,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
static void intel_disable_pipe(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
int reg;
u32 val;
@@ -1801,7 +1806,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
return;
- reg = PIPECONF(pipe);
+ reg = PIPECONF(cpu_transcoder);
val = I915_READ(reg);
if ((val & PIPECONF_ENABLE) == 0)
return;
@@ -2679,6 +2684,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
u32 reg, temp;
/* Write the TU size bits so error detection works */
@@ -2690,7 +2696,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
temp = I915_READ(reg);
temp &= ~((0x7 << 19) | (0x7 << 16));
temp |= (intel_crtc->fdi_lanes - 1) << 19;
- temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
+ temp |= (I915_READ(PIPECONF(cpu_transcoder)) & PIPE_BPC_MASK) << 11;
I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
POSTING_READ(reg);
@@ -2764,6 +2770,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
u32 reg, temp;
/* disable CPU FDI tx and PCH FDI rx */
@@ -2775,7 +2782,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
reg = FDI_RX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~(0x7 << 16);
- temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
+ temp |= (I915_READ(PIPECONF(cpu_transcoder)) & PIPE_BPC_MASK) << 11;
I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
POSTING_READ(reg);
@@ -2809,7 +2816,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
}
/* BPC in FDI rx is consistent with that in PIPECONF */
temp &= ~(0x07 << 16);
- temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
+ temp |= (I915_READ(PIPECONF(cpu_transcoder)) & PIPE_BPC_MASK) << 11;
I915_WRITE(reg, temp);
POSTING_READ(reg);
@@ -2971,6 +2978,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
u32 reg, temp;
assert_transcoder_disabled(dev_priv, pipe);
@@ -3027,7 +3035,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
if (HAS_PCH_CPT(dev) &&
(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
- u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
+ u32 bpc = (I915_READ(PIPECONF(cpu_transcoder)) &
+ PIPE_BPC_MASK) >> 5;
reg = TRANS_DP_CTL(pipe);
temp = I915_READ(reg);
temp &= ~(TRANS_DP_PORT_SEL_MASK |
@@ -4383,6 +4392,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
int plane = intel_crtc->plane;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
int refclk, num_connectors = 0;
intel_clock_t clock, reduced_clock;
u32 dspcntr, pipeconf;
@@ -4463,7 +4473,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
num_connectors);
/* setup pipeconf */
- pipeconf = I915_READ(PIPECONF(pipe));
+ pipeconf = I915_READ(PIPECONF(cpu_transcoder));
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4535,8 +4545,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
(mode->hdisplay - 1));
I915_WRITE(DSPPOS(plane), 0);
- I915_WRITE(PIPECONF(pipe), pipeconf);
- POSTING_READ(PIPECONF(pipe));
+ I915_WRITE(PIPECONF(cpu_transcoder), pipeconf);
+ POSTING_READ(PIPECONF(cpu_transcoder));
intel_enable_pipe(dev_priv, pipe, false);
intel_wait_for_vblank(dev, pipe);
@@ -4704,10 +4714,10 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
{
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
uint32_t val;
- val = I915_READ(PIPECONF(pipe));
+ val = I915_READ(PIPECONF(cpu_transcoder));
val &= ~PIPE_BPC_MASK;
switch (intel_crtc->bpp) {
@@ -4738,8 +4748,8 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
else
val |= PIPECONF_PROGRESSIVE;
- I915_WRITE(PIPECONF(pipe), val);
- POSTING_READ(PIPECONF(pipe));
+ I915_WRITE(PIPECONF(cpu_transcoder), val);
+ POSTING_READ(PIPECONF(cpu_transcoder));
}
static void haswell_set_pipeconf(struct drm_crtc *crtc,
@@ -4748,10 +4758,10 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
{
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
uint32_t val;
- val = I915_READ(PIPECONF(pipe));
+ val = I915_READ(PIPECONF(cpu_transcoder));
val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
if (dither)
@@ -4763,8 +4773,8 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
else
val |= PIPECONF_PROGRESSIVE;
- I915_WRITE(PIPECONF(pipe), val);
- POSTING_READ(PIPECONF(pipe));
+ I915_WRITE(PIPECONF(cpu_transcoder), val);
+ POSTING_READ(PIPECONF(cpu_transcoder));
}
static bool ironlake_compute_clocks(struct drm_crtc *crtc,
@@ -5238,7 +5248,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
num_connectors, pipe_name(pipe));
- WARN_ON(I915_READ(PIPECONF(pipe)) &
+ WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
@@ -8416,7 +8426,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
u32 reg, val;
/* Clear any frame start delays used for debugging left by the BIOS */
- reg = PIPECONF(crtc->pipe);
+ reg = PIPECONF(crtc->cpu_transcoder);
I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
/* We need to sanitize the plane -> pipe mapping first because this will
@@ -8579,7 +8589,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
for_each_pipe(pipe) {
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
- tmp = I915_READ(PIPECONF(pipe));
+ tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
if (tmp & PIPECONF_ENABLE)
crtc->active = true;
else
@@ -8773,6 +8783,7 @@ intel_display_capture_error_state(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
struct intel_display_error_state *error;
+ enum transcoder cpu_transcoder;
int i;
error = kmalloc(sizeof(*error), GFP_ATOMIC);
@@ -8780,6 +8791,8 @@ intel_display_capture_error_state(struct drm_device *dev)
return NULL;
for_each_pipe(i) {
+ cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, i);
+
error->cursor[i].control = I915_READ(CURCNTR(i));
error->cursor[i].position = I915_READ(CURPOS(i));
error->cursor[i].base = I915_READ(CURBASE(i));
@@ -8794,7 +8807,7 @@ intel_display_capture_error_state(struct drm_device *dev)
error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
}
- error->pipe[i].conf = I915_READ(PIPECONF(i));
+ error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
error->pipe[i].source = I915_READ(PIPESRC(i));
error->pipe[i].htotal = I915_READ(HTOTAL(i));
error->pipe[i].hblank = I915_READ(HBLANK(i));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 7644f31..f2ca943 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -422,6 +422,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
struct intel_framebuffer *intel_fb;
struct drm_i915_gem_object *obj, *old_obj;
int pipe = intel_plane->pipe;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
int ret = 0;
int x = src_x >> 16, y = src_y >> 16;
int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
@@ -436,7 +437,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
src_h = src_h >> 16;
/* Pipe must be running... */
- if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
+ if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE))
return -EINVAL;
if (crtc_x >= primary_w || crtc_y >= primary_h)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index d2c5c8f..fcdbb66 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -941,7 +941,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
const struct video_levels *video_levels;
const struct color_conversion *color_conversion;
bool burst_ena;
- int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
if (!tv_mode)
return; /* can't happen (mode_prepare prevents this) */
@@ -1085,7 +1085,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
(video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
{
- int pipeconf_reg = PIPECONF(pipe);
+ int pipeconf_reg = PIPECONF(cpu_transcoder);
int dspcntr_reg = DSPCNTR(intel_crtc->plane);
int pipeconf = I915_READ(pipeconf_reg);
int dspcntr = I915_READ(dspcntr_reg);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 05/14] drm/i915: convert PIPECONF to use transcoder instead of pipe
2012-10-18 21:21 ` [PATCH 05/14] drm/i915: convert PIPECONF to use transcoder instead of pipe Paulo Zanoni
@ 2012-10-18 22:23 ` Daniel Vetter
2012-10-19 18:36 ` Paulo Zanoni
0 siblings, 1 reply; 22+ messages in thread
From: Daniel Vetter @ 2012-10-18 22:23 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Thu, Oct 18, 2012 at 06:21:35PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Because the PIPECONF register is actually part of the CPU transcoder,
> not the CPU pipe.
>
> Ideally we would also rename PIPECONF to TRANSCONF to remind people
> that they should use the transcoder instead of the pipe, but let's
> keep it like this for now since most Gens still name it PIPECONF.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
I think as a general rule it makes sense to not convert codepaths that are
never run on haswell to cpu_transcoder, since that thing really doesn't
exist that much on earlier platforms. Also, it makes the patch smaller ;-)
Below some comments about which hunks I think we can drop.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_irq.c | 4 ++-
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_crt.c | 6 ++--
> drivers/gpu/drm/i915/intel_display.c | 61 ++++++++++++++++++++++--------------
> drivers/gpu/drm/i915/intel_sprite.c | 3 +-
> drivers/gpu/drm/i915/intel_tv.c | 4 +--
> 6 files changed, 49 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d07c787..c9b186d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -123,7 +123,9 @@ static int
> i915_pipe_enabled(struct drm_device *dev, int pipe)
> {
> drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> - return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
> +
> + return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
> }
Oh, how I hate our vblank code and it's insistency to deal with pipes
instead of crtc numbers.
>
> /* Called from drm generic code, passed a 'crtc', which
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 72a61b5..9fecd3b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2714,7 +2714,7 @@
> #define PIPE_12BPC (3 << 5)
>
> #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
> -#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
> +#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
> #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
> #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
> #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 53f3e87..2a2c976 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -467,7 +467,9 @@ intel_crt_load_detect(struct intel_crt *crt)
> {
> struct drm_device *dev = crt->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crt->base.base.crtc);
> + enum pipe pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> uint32_t save_bclrpat;
> uint32_t save_vtotal;
> uint32_t vtotal, vactive;
> @@ -489,7 +491,7 @@ intel_crt_load_detect(struct intel_crt *crt)
> vtotal_reg = VTOTAL(pipe);
> vblank_reg = VBLANK(pipe);
> vsync_reg = VSYNC(pipe);
> - pipeconf_reg = PIPECONF(pipe);
> + pipeconf_reg = PIPECONF(cpu_transcoder);
> pipe_dsl_reg = PIPEDSL(pipe);
>
> save_bclrpat = I915_READ(bclrpat_reg);
Load detect is only used by gen2/3 vga connectors and by the tv out
connector, nothing else. So I think we can just leave this as-is.
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 827c5ba..dc93c39 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1008,9 +1008,10 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
> void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>
> if (INTEL_INFO(dev)->gen >= 4) {
> - int reg = PIPECONF(pipe);
> + int reg = PIPECONF(cpu_transcoder);
>
> /* Wait for the Pipe State to go off */
> if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
> @@ -1222,12 +1223,13 @@ void assert_pipe(struct drm_i915_private *dev_priv,
> int reg;
> u32 val;
> bool cur_state;
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>
> /* if we need the pipe A quirk it must be always on */
> if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
> state = true;
>
> - reg = PIPECONF(pipe);
> + reg = PIPECONF(cpu_transcoder);
> val = I915_READ(reg);
> cur_state = !!(val & PIPECONF_ENABLE);
> WARN(cur_state != state,
> @@ -1661,6 +1663,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
> int reg;
> u32 val, pipeconf_val;
> struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>
> /* PCH only available on ILK+ */
> BUG_ON(dev_priv->info->gen < 5);
Do we really need this on hsw for the pch vga port? Since the only pch
port we have is vga, and that is currently restricted to pipe 0 I'd prefer
if we fix this up once we really put the code to some use (i.e. lift the
pipe == 0 restriction).
> @@ -1680,7 +1683,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
> }
> reg = TRANSCONF(pipe);
> val = I915_READ(reg);
> - pipeconf_val = I915_READ(PIPECONF(pipe));
> + pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
>
> if (HAS_PCH_IBX(dev_priv->dev)) {
> /*
> @@ -1745,6 +1748,7 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
> static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> bool pch_port)
> {
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
> int reg;
> u32 val;
>
> @@ -1764,7 +1768,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> /* FIXME: assert CPU port conditions for SNB+ */
> }
>
> - reg = PIPECONF(pipe);
> + reg = PIPECONF(cpu_transcoder);
> val = I915_READ(reg);
> if (val & PIPECONF_ENABLE)
> return;
> @@ -1788,6 +1792,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> static void intel_disable_pipe(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
> int reg;
> u32 val;
>
> @@ -1801,7 +1806,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
> if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
> return;
>
> - reg = PIPECONF(pipe);
> + reg = PIPECONF(cpu_transcoder);
> val = I915_READ(reg);
> if ((val & PIPECONF_ENABLE) == 0)
> return;
> @@ -2679,6 +2684,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
> struct drm_device *dev = intel_crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> u32 reg, temp;
Dito for all the fdi stuff here, I think that's better done when we
enable/fix-up VGA.
>
> /* Write the TU size bits so error detection works */
> @@ -2690,7 +2696,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
> temp = I915_READ(reg);
> temp &= ~((0x7 << 19) | (0x7 << 16));
> temp |= (intel_crtc->fdi_lanes - 1) << 19;
> - temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
> + temp |= (I915_READ(PIPECONF(cpu_transcoder)) & PIPE_BPC_MASK) << 11;
> I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
>
> POSTING_READ(reg);
> @@ -2764,6 +2770,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> u32 reg, temp;
>
> /* disable CPU FDI tx and PCH FDI rx */
> @@ -2775,7 +2782,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
> reg = FDI_RX_CTL(pipe);
> temp = I915_READ(reg);
> temp &= ~(0x7 << 16);
> - temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
> + temp |= (I915_READ(PIPECONF(cpu_transcoder)) & PIPE_BPC_MASK) << 11;
> I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
>
> POSTING_READ(reg);
> @@ -2809,7 +2816,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
> }
> /* BPC in FDI rx is consistent with that in PIPECONF */
> temp &= ~(0x07 << 16);
> - temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
> + temp |= (I915_READ(PIPECONF(cpu_transcoder)) & PIPE_BPC_MASK) << 11;
> I915_WRITE(reg, temp);
>
> POSTING_READ(reg);
> @@ -2971,6 +2978,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> u32 reg, temp;
>
> assert_transcoder_disabled(dev_priv, pipe);
> @@ -3027,7 +3035,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> if (HAS_PCH_CPT(dev) &&
> (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
> intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
> - u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
> + u32 bpc = (I915_READ(PIPECONF(cpu_transcoder)) &
> + PIPE_BPC_MASK) >> 5;
> reg = TRANS_DP_CTL(pipe);
> temp = I915_READ(reg);
> temp &= ~(TRANS_DP_PORT_SEL_MASK |
> @@ -4383,6 +4392,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int pipe = intel_crtc->pipe;
> int plane = intel_crtc->plane;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> int refclk, num_connectors = 0;
> intel_clock_t clock, reduced_clock;
> u32 dspcntr, pipeconf;
> @@ -4463,7 +4473,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> num_connectors);
i9xx stuff, I think pipeconf is totally ok for these ;-)
>
> /* setup pipeconf */
> - pipeconf = I915_READ(PIPECONF(pipe));
> + pipeconf = I915_READ(PIPECONF(cpu_transcoder));
>
> /* Set up the display plane register */
> dspcntr = DISPPLANE_GAMMA_ENABLE;
> @@ -4535,8 +4545,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> (mode->hdisplay - 1));
> I915_WRITE(DSPPOS(plane), 0);
>
> - I915_WRITE(PIPECONF(pipe), pipeconf);
> - POSTING_READ(PIPECONF(pipe));
> + I915_WRITE(PIPECONF(cpu_transcoder), pipeconf);
> + POSTING_READ(PIPECONF(cpu_transcoder));
> intel_enable_pipe(dev_priv, pipe, false);
>
> intel_wait_for_vblank(dev, pipe);
> @@ -4704,10 +4714,10 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
> {
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> uint32_t val;
ilk_set_pipeconf is not called on hsw, we have the special version now.
>
> - val = I915_READ(PIPECONF(pipe));
> + val = I915_READ(PIPECONF(cpu_transcoder));
>
> val &= ~PIPE_BPC_MASK;
> switch (intel_crtc->bpp) {
> @@ -4738,8 +4748,8 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
> else
> val |= PIPECONF_PROGRESSIVE;
>
> - I915_WRITE(PIPECONF(pipe), val);
> - POSTING_READ(PIPECONF(pipe));
> + I915_WRITE(PIPECONF(cpu_transcoder), val);
> + POSTING_READ(PIPECONF(cpu_transcoder));
> }
>
> static void haswell_set_pipeconf(struct drm_crtc *crtc,
> @@ -4748,10 +4758,10 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
> {
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> uint32_t val;
>
> - val = I915_READ(PIPECONF(pipe));
> + val = I915_READ(PIPECONF(cpu_transcoder));
>
> val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
> if (dither)
> @@ -4763,8 +4773,8 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
> else
> val |= PIPECONF_PROGRESSIVE;
>
> - I915_WRITE(PIPECONF(pipe), val);
> - POSTING_READ(PIPECONF(pipe));
> + I915_WRITE(PIPECONF(cpu_transcoder), val);
> + POSTING_READ(PIPECONF(cpu_transcoder));
> }
>
> static bool ironlake_compute_clocks(struct drm_crtc *crtc,
> @@ -5238,7 +5248,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
> WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
> num_connectors, pipe_name(pipe));
>
> - WARN_ON(I915_READ(PIPECONF(pipe)) &
> + WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
> (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
>
> WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
> @@ -8416,7 +8426,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
> u32 reg, val;
>
> /* Clear any frame start delays used for debugging left by the BIOS */
> - reg = PIPECONF(crtc->pipe);
> + reg = PIPECONF(crtc->cpu_transcoder);
> I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
>
> /* We need to sanitize the plane -> pipe mapping first because this will
> @@ -8579,7 +8589,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
> for_each_pipe(pipe) {
> crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>
> - tmp = I915_READ(PIPECONF(pipe));
> + tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
> if (tmp & PIPECONF_ENABLE)
> crtc->active = true;
> else
> @@ -8773,6 +8783,7 @@ intel_display_capture_error_state(struct drm_device *dev)
> {
> drm_i915_private_t *dev_priv = dev->dev_private;
> struct intel_display_error_state *error;
> + enum transcoder cpu_transcoder;
> int i;
>
> error = kmalloc(sizeof(*error), GFP_ATOMIC);
> @@ -8780,6 +8791,8 @@ intel_display_capture_error_state(struct drm_device *dev)
> return NULL;
>
> for_each_pipe(i) {
> + cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, i);
> +
> error->cursor[i].control = I915_READ(CURCNTR(i));
> error->cursor[i].position = I915_READ(CURPOS(i));
> error->cursor[i].base = I915_READ(CURBASE(i));
> @@ -8794,7 +8807,7 @@ intel_display_capture_error_state(struct drm_device *dev)
> error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
> }
>
> - error->pipe[i].conf = I915_READ(PIPECONF(i));
> + error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
> error->pipe[i].source = I915_READ(PIPESRC(i));
> error->pipe[i].htotal = I915_READ(HTOTAL(i));
> error->pipe[i].hblank = I915_READ(HBLANK(i));
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 7644f31..f2ca943 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -422,6 +422,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> struct intel_framebuffer *intel_fb;
> struct drm_i915_gem_object *obj, *old_obj;
> int pipe = intel_plane->pipe;
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
I think we can leave that until we enable sprite support on hsw, too.
> int ret = 0;
> int x = src_x >> 16, y = src_y >> 16;
> int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
> @@ -436,7 +437,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> src_h = src_h >> 16;
>
> /* Pipe must be running... */
> - if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
> + if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE))
> return -EINVAL;
>
> if (crtc_x >= primary_w || crtc_y >= primary_h)
> diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
> index d2c5c8f..fcdbb66 100644
> --- a/drivers/gpu/drm/i915/intel_tv.c
> +++ b/drivers/gpu/drm/i915/intel_tv.c
> @@ -941,7 +941,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> const struct video_levels *video_levels;
> const struct color_conversion *color_conversion;
> bool burst_ena;
> - int pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
TV-out is non-existing on hsw ...
>
> if (!tv_mode)
> return; /* can't happen (mode_prepare prevents this) */
> @@ -1085,7 +1085,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
> (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
> {
> - int pipeconf_reg = PIPECONF(pipe);
> + int pipeconf_reg = PIPECONF(cpu_transcoder);
> int dspcntr_reg = DSPCNTR(intel_crtc->plane);
> int pipeconf = I915_READ(pipeconf_reg);
> int dspcntr = I915_READ(dspcntr_reg);
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 05/14] drm/i915: convert PIPECONF to use transcoder instead of pipe
2012-10-18 22:23 ` Daniel Vetter
@ 2012-10-19 18:36 ` Paulo Zanoni
0 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-19 18:36 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Paulo Zanoni
Hi
2012/10/18 Daniel Vetter <daniel@ffwll.ch>:
> On Thu, Oct 18, 2012 at 06:21:35PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> Because the PIPECONF register is actually part of the CPU transcoder,
>> not the CPU pipe.
>>
>> Ideally we would also rename PIPECONF to TRANSCONF to remind people
>> that they should use the transcoder instead of the pipe, but let's
>> keep it like this for now since most Gens still name it PIPECONF.
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> I think as a general rule it makes sense to not convert codepaths that are
> never run on haswell to cpu_transcoder, since that thing really doesn't
> exist that much on earlier platforms. Also, it makes the patch smaller ;-)
Just making the discussion public...
I also thought about that, but my fear is that as we move code from
one place to another, in the future we might end moving/copying some
code and making Haswell use pipe instead of transcoder.
I will write the smaller version with only haswell-specific bits and send V2.
>
> Below some comments about which hunks I think we can drop.
> -Daniel
>
>> ---
>> drivers/gpu/drm/i915/i915_irq.c | 4 ++-
>> drivers/gpu/drm/i915/i915_reg.h | 2 +-
>> drivers/gpu/drm/i915/intel_crt.c | 6 ++--
>> drivers/gpu/drm/i915/intel_display.c | 61 ++++++++++++++++++++++--------------
>> drivers/gpu/drm/i915/intel_sprite.c | 3 +-
>> drivers/gpu/drm/i915/intel_tv.c | 4 +--
>> 6 files changed, 49 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index d07c787..c9b186d 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -123,7 +123,9 @@ static int
>> i915_pipe_enabled(struct drm_device *dev, int pipe)
>> {
>> drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
>> - return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
>> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>> +
>> + return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
>> }
>
> Oh, how I hate our vblank code and it's insistency to deal with pipes
> instead of crtc numbers.
>
>>
>> /* Called from drm generic code, passed a 'crtc', which
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 72a61b5..9fecd3b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2714,7 +2714,7 @@
>> #define PIPE_12BPC (3 << 5)
>>
>> #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
>> -#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
>> +#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
>> #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
>> #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
>> #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
>> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
>> index 53f3e87..2a2c976 100644
>> --- a/drivers/gpu/drm/i915/intel_crt.c
>> +++ b/drivers/gpu/drm/i915/intel_crt.c
>> @@ -467,7 +467,9 @@ intel_crt_load_detect(struct intel_crt *crt)
>> {
>> struct drm_device *dev = crt->base.base.dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> - uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
>> + struct intel_crtc *intel_crtc = to_intel_crtc(crt->base.base.crtc);
>> + enum pipe pipe = intel_crtc->pipe;
>> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>> uint32_t save_bclrpat;
>> uint32_t save_vtotal;
>> uint32_t vtotal, vactive;
>> @@ -489,7 +491,7 @@ intel_crt_load_detect(struct intel_crt *crt)
>> vtotal_reg = VTOTAL(pipe);
>> vblank_reg = VBLANK(pipe);
>> vsync_reg = VSYNC(pipe);
>> - pipeconf_reg = PIPECONF(pipe);
>> + pipeconf_reg = PIPECONF(cpu_transcoder);
>> pipe_dsl_reg = PIPEDSL(pipe);
>>
>> save_bclrpat = I915_READ(bclrpat_reg);
>
> Load detect is only used by gen2/3 vga connectors and by the tv out
> connector, nothing else. So I think we can just leave this as-is.
>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 827c5ba..dc93c39 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -1008,9 +1008,10 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
>> void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
>> {
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>>
>> if (INTEL_INFO(dev)->gen >= 4) {
>> - int reg = PIPECONF(pipe);
>> + int reg = PIPECONF(cpu_transcoder);
>>
>> /* Wait for the Pipe State to go off */
>> if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
>> @@ -1222,12 +1223,13 @@ void assert_pipe(struct drm_i915_private *dev_priv,
>> int reg;
>> u32 val;
>> bool cur_state;
>> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>>
>> /* if we need the pipe A quirk it must be always on */
>> if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
>> state = true;
>>
>> - reg = PIPECONF(pipe);
>> + reg = PIPECONF(cpu_transcoder);
>> val = I915_READ(reg);
>> cur_state = !!(val & PIPECONF_ENABLE);
>> WARN(cur_state != state,
>> @@ -1661,6 +1663,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
>> int reg;
>> u32 val, pipeconf_val;
>> struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
>> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>>
>> /* PCH only available on ILK+ */
>> BUG_ON(dev_priv->info->gen < 5);
>
> Do we really need this on hsw for the pch vga port? Since the only pch
> port we have is vga, and that is currently restricted to pipe 0 I'd prefer
> if we fix this up once we really put the code to some use (i.e. lift the
> pipe == 0 restriction).
>
>> @@ -1680,7 +1683,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
>> }
>> reg = TRANSCONF(pipe);
>> val = I915_READ(reg);
>> - pipeconf_val = I915_READ(PIPECONF(pipe));
>> + pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
>>
>> if (HAS_PCH_IBX(dev_priv->dev)) {
>> /*
>> @@ -1745,6 +1748,7 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
>> static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
>> bool pch_port)
>> {
>> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>> int reg;
>> u32 val;
>>
>> @@ -1764,7 +1768,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
>> /* FIXME: assert CPU port conditions for SNB+ */
>> }
>>
>> - reg = PIPECONF(pipe);
>> + reg = PIPECONF(cpu_transcoder);
>> val = I915_READ(reg);
>> if (val & PIPECONF_ENABLE)
>> return;
>> @@ -1788,6 +1792,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
>> static void intel_disable_pipe(struct drm_i915_private *dev_priv,
>> enum pipe pipe)
>> {
>> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>> int reg;
>> u32 val;
>>
>> @@ -1801,7 +1806,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
>> if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
>> return;
>>
>> - reg = PIPECONF(pipe);
>> + reg = PIPECONF(cpu_transcoder);
>> val = I915_READ(reg);
>> if ((val & PIPECONF_ENABLE) == 0)
>> return;
>> @@ -2679,6 +2684,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
>> struct drm_device *dev = intel_crtc->base.dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> int pipe = intel_crtc->pipe;
>> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>> u32 reg, temp;
>
> Dito for all the fdi stuff here, I think that's better done when we
> enable/fix-up VGA.
>
>>
>> /* Write the TU size bits so error detection works */
>> @@ -2690,7 +2696,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
>> temp = I915_READ(reg);
>> temp &= ~((0x7 << 19) | (0x7 << 16));
>> temp |= (intel_crtc->fdi_lanes - 1) << 19;
>> - temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
>> + temp |= (I915_READ(PIPECONF(cpu_transcoder)) & PIPE_BPC_MASK) << 11;
>> I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
>>
>> POSTING_READ(reg);
>> @@ -2764,6 +2770,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> int pipe = intel_crtc->pipe;
>> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>> u32 reg, temp;
>>
>> /* disable CPU FDI tx and PCH FDI rx */
>> @@ -2775,7 +2782,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
>> reg = FDI_RX_CTL(pipe);
>> temp = I915_READ(reg);
>> temp &= ~(0x7 << 16);
>> - temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
>> + temp |= (I915_READ(PIPECONF(cpu_transcoder)) & PIPE_BPC_MASK) << 11;
>> I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
>>
>> POSTING_READ(reg);
>> @@ -2809,7 +2816,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
>> }
>> /* BPC in FDI rx is consistent with that in PIPECONF */
>> temp &= ~(0x07 << 16);
>> - temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
>> + temp |= (I915_READ(PIPECONF(cpu_transcoder)) & PIPE_BPC_MASK) << 11;
>> I915_WRITE(reg, temp);
>>
>> POSTING_READ(reg);
>> @@ -2971,6 +2978,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> int pipe = intel_crtc->pipe;
>> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>> u32 reg, temp;
>>
>> assert_transcoder_disabled(dev_priv, pipe);
>> @@ -3027,7 +3035,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>> if (HAS_PCH_CPT(dev) &&
>> (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
>> intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
>> - u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
>> + u32 bpc = (I915_READ(PIPECONF(cpu_transcoder)) &
>> + PIPE_BPC_MASK) >> 5;
>> reg = TRANS_DP_CTL(pipe);
>> temp = I915_READ(reg);
>> temp &= ~(TRANS_DP_PORT_SEL_MASK |
>> @@ -4383,6 +4392,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> int pipe = intel_crtc->pipe;
>> int plane = intel_crtc->plane;
>> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>> int refclk, num_connectors = 0;
>> intel_clock_t clock, reduced_clock;
>> u32 dspcntr, pipeconf;
>> @@ -4463,7 +4473,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>> num_connectors);
>
> i9xx stuff, I think pipeconf is totally ok for these ;-)
>
>>
>> /* setup pipeconf */
>> - pipeconf = I915_READ(PIPECONF(pipe));
>> + pipeconf = I915_READ(PIPECONF(cpu_transcoder));
>>
>> /* Set up the display plane register */
>> dspcntr = DISPPLANE_GAMMA_ENABLE;
>> @@ -4535,8 +4545,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>> (mode->hdisplay - 1));
>> I915_WRITE(DSPPOS(plane), 0);
>>
>> - I915_WRITE(PIPECONF(pipe), pipeconf);
>> - POSTING_READ(PIPECONF(pipe));
>> + I915_WRITE(PIPECONF(cpu_transcoder), pipeconf);
>> + POSTING_READ(PIPECONF(cpu_transcoder));
>> intel_enable_pipe(dev_priv, pipe, false);
>>
>> intel_wait_for_vblank(dev, pipe);
>> @@ -4704,10 +4714,10 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
>> {
>> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> - int pipe = intel_crtc->pipe;
>> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>> uint32_t val;
>
> ilk_set_pipeconf is not called on hsw, we have the special version now.
>
>>
>> - val = I915_READ(PIPECONF(pipe));
>> + val = I915_READ(PIPECONF(cpu_transcoder));
>>
>> val &= ~PIPE_BPC_MASK;
>> switch (intel_crtc->bpp) {
>> @@ -4738,8 +4748,8 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
>> else
>> val |= PIPECONF_PROGRESSIVE;
>>
>> - I915_WRITE(PIPECONF(pipe), val);
>> - POSTING_READ(PIPECONF(pipe));
>> + I915_WRITE(PIPECONF(cpu_transcoder), val);
>> + POSTING_READ(PIPECONF(cpu_transcoder));
>> }
>>
>> static void haswell_set_pipeconf(struct drm_crtc *crtc,
>> @@ -4748,10 +4758,10 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
>> {
>> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> - int pipe = intel_crtc->pipe;
>> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>> uint32_t val;
>>
>> - val = I915_READ(PIPECONF(pipe));
>> + val = I915_READ(PIPECONF(cpu_transcoder));
>>
>> val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
>> if (dither)
>> @@ -4763,8 +4773,8 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
>> else
>> val |= PIPECONF_PROGRESSIVE;
>>
>> - I915_WRITE(PIPECONF(pipe), val);
>> - POSTING_READ(PIPECONF(pipe));
>> + I915_WRITE(PIPECONF(cpu_transcoder), val);
>> + POSTING_READ(PIPECONF(cpu_transcoder));
>> }
>>
>> static bool ironlake_compute_clocks(struct drm_crtc *crtc,
>> @@ -5238,7 +5248,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
>> WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
>> num_connectors, pipe_name(pipe));
>>
>> - WARN_ON(I915_READ(PIPECONF(pipe)) &
>> + WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
>> (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
>>
>> WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
>> @@ -8416,7 +8426,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
>> u32 reg, val;
>>
>> /* Clear any frame start delays used for debugging left by the BIOS */
>> - reg = PIPECONF(crtc->pipe);
>> + reg = PIPECONF(crtc->cpu_transcoder);
>> I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
>>
>> /* We need to sanitize the plane -> pipe mapping first because this will
>> @@ -8579,7 +8589,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
>> for_each_pipe(pipe) {
>> crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>>
>> - tmp = I915_READ(PIPECONF(pipe));
>> + tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
>> if (tmp & PIPECONF_ENABLE)
>> crtc->active = true;
>> else
>> @@ -8773,6 +8783,7 @@ intel_display_capture_error_state(struct drm_device *dev)
>> {
>> drm_i915_private_t *dev_priv = dev->dev_private;
>> struct intel_display_error_state *error;
>> + enum transcoder cpu_transcoder;
>> int i;
>>
>> error = kmalloc(sizeof(*error), GFP_ATOMIC);
>> @@ -8780,6 +8791,8 @@ intel_display_capture_error_state(struct drm_device *dev)
>> return NULL;
>>
>> for_each_pipe(i) {
>> + cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, i);
>> +
>> error->cursor[i].control = I915_READ(CURCNTR(i));
>> error->cursor[i].position = I915_READ(CURPOS(i));
>> error->cursor[i].base = I915_READ(CURBASE(i));
>> @@ -8794,7 +8807,7 @@ intel_display_capture_error_state(struct drm_device *dev)
>> error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
>> }
>>
>> - error->pipe[i].conf = I915_READ(PIPECONF(i));
>> + error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
>> error->pipe[i].source = I915_READ(PIPESRC(i));
>> error->pipe[i].htotal = I915_READ(HTOTAL(i));
>> error->pipe[i].hblank = I915_READ(HBLANK(i));
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index 7644f31..f2ca943 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -422,6 +422,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>> struct intel_framebuffer *intel_fb;
>> struct drm_i915_gem_object *obj, *old_obj;
>> int pipe = intel_plane->pipe;
>> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>
> I think we can leave that until we enable sprite support on hsw, too.
>
>> int ret = 0;
>> int x = src_x >> 16, y = src_y >> 16;
>> int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
>> @@ -436,7 +437,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>> src_h = src_h >> 16;
>>
>> /* Pipe must be running... */
>> - if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
>> + if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE))
>> return -EINVAL;
>>
>> if (crtc_x >= primary_w || crtc_y >= primary_h)
>> diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
>> index d2c5c8f..fcdbb66 100644
>> --- a/drivers/gpu/drm/i915/intel_tv.c
>> +++ b/drivers/gpu/drm/i915/intel_tv.c
>> @@ -941,7 +941,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>> const struct video_levels *video_levels;
>> const struct color_conversion *color_conversion;
>> bool burst_ena;
>> - int pipe = intel_crtc->pipe;
>> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>
> TV-out is non-existing on hsw ...
>>
>> if (!tv_mode)
>> return; /* can't happen (mode_prepare prevents this) */
>> @@ -1085,7 +1085,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>> ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
>> (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
>> {
>> - int pipeconf_reg = PIPECONF(pipe);
>> + int pipeconf_reg = PIPECONF(cpu_transcoder);
>> int dspcntr_reg = DSPCNTR(intel_crtc->plane);
>> int pipeconf = I915_READ(pipeconf_reg);
>> int dspcntr = I915_READ(dspcntr_reg);
>> --
>> 1.7.11.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 06/14] drm/i915: convert PIPE_MSA_MISC to transcoder
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (4 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 05/14] drm/i915: convert PIPECONF to use transcoder instead of pipe Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 21:21 ` [PATCH 07/14] drm/i915: convert CPU M/N timings " Paulo Zanoni
` (7 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Same as the other registers. This one also appeared on Haswell for the
first time, so that's why we are renaming it.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 19 ++++++++++---------
drivers/gpu/drm/i915/intel_ddi.c | 18 +++++++++---------
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9fecd3b..9eab732 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4552,15 +4552,16 @@
#define TRANS_CLK_SEL_DISABLED (0x0<<29)
#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
-#define _PIPEA_MSA_MISC 0x60410
-#define _PIPEB_MSA_MISC 0x61410
-#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC)
-#define PIPE_MSA_SYNC_CLK (1<<0)
-#define PIPE_MSA_6_BPC (0<<5)
-#define PIPE_MSA_8_BPC (1<<5)
-#define PIPE_MSA_10_BPC (2<<5)
-#define PIPE_MSA_12_BPC (3<<5)
-#define PIPE_MSA_16_BPC (4<<5)
+#define _TRANSA_MSA_MISC 0x60410
+#define _TRANSB_MSA_MISC 0x61410
+#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
+ _TRANSB_MSA_MISC)
+#define TRANS_MSA_SYNC_CLK (1<<0)
+#define TRANS_MSA_6_BPC (0<<5)
+#define TRANS_MSA_8_BPC (1<<5)
+#define TRANS_MSA_10_BPC (2<<5)
+#define TRANS_MSA_12_BPC (3<<5)
+#define TRANS_MSA_16_BPC (4<<5)
/* LCPLL Control */
#define LCPLL_CTL 0x130040
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8d3ce3a..c30cb14 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -888,32 +888,32 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
int type = intel_encoder->type;
uint32_t temp;
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
- temp = PIPE_MSA_SYNC_CLK;
+ temp = TRANS_MSA_SYNC_CLK;
switch (intel_crtc->bpp) {
case 18:
- temp |= PIPE_MSA_6_BPC;
+ temp |= TRANS_MSA_6_BPC;
break;
case 24:
- temp |= PIPE_MSA_8_BPC;
+ temp |= TRANS_MSA_8_BPC;
break;
case 30:
- temp |= PIPE_MSA_10_BPC;
+ temp |= TRANS_MSA_10_BPC;
break;
case 36:
- temp |= PIPE_MSA_12_BPC;
+ temp |= TRANS_MSA_12_BPC;
break;
default:
- temp |= PIPE_MSA_8_BPC;
- WARN(1, "%d bpp unsupported by pipe DDI function\n",
+ temp |= TRANS_MSA_8_BPC;
+ WARN(1, "%d bpp unsupported by DDI function\n",
intel_crtc->bpp);
}
- I915_WRITE(PIPE_MSA_MISC(pipe), temp);
+ I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 07/14] drm/i915: convert CPU M/N timings to transcoder
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (5 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 06/14] drm/i915: convert PIPE_MSA_MISC to transcoder Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 22:25 ` Daniel Vetter
2012-10-18 21:21 ` [PATCH 08/14] drm/i915: convert pipe timing definitions " Paulo Zanoni
` (6 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Same thing as the previous commits. Not renaming this one since it
exists since way before Haswell.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++--------
drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
drivers/gpu/drm/i915/intel_dp.c | 10 ++++++----
3 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9eab732..5b4f608 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3304,14 +3304,14 @@
#define _PIPEB_LINK_M2 0x61048
#define _PIPEB_LINK_N2 0x6104c
-#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
-#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
-#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
-#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
-#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
-#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
-#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
-#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
+#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
+#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
+#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
+#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
+#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
+#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
+#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
+#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
/* CPU panel fitter */
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dc93c39..95a4a5f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2689,7 +2689,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
/* Write the TU size bits so error detection works */
I915_WRITE(FDI_RX_TUSIZE1(pipe),
- I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+ I915_READ(PIPE_DATA_M1(cpu_transcoder)) & TU_SIZE_MASK);
/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
reg = FDI_RX_CTL(pipe);
@@ -4847,7 +4847,7 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
struct intel_encoder *intel_encoder, *edp_encoder = NULL;
struct fdi_m_n m_n = {0};
int target_clock, pixel_multiplier, lane, link_bw;
@@ -4910,10 +4910,10 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
&m_n);
- I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
- I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
- I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
- I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
}
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 697b176..244cb6a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -791,6 +791,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
int lane_count = 4;
struct intel_dp_m_n m_n;
int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
/*
* Find the lane count in the intel_encoder private
@@ -815,10 +816,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
mode->clock, adjusted_mode->clock, &m_n);
if (IS_HASWELL(dev)) {
- I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
- I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
- I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
- I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
+ TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
} else if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 07/14] drm/i915: convert CPU M/N timings to transcoder
2012-10-18 21:21 ` [PATCH 07/14] drm/i915: convert CPU M/N timings " Paulo Zanoni
@ 2012-10-18 22:25 ` Daniel Vetter
0 siblings, 0 replies; 22+ messages in thread
From: Daniel Vetter @ 2012-10-18 22:25 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Thu, Oct 18, 2012 at 06:21:37PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Same thing as the previous commits. Not renaming this one since it
> exists since way before Haswell.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Again I think we can drop the fdi hunks here. We better keep the set_m_n
hunks (I think we only need the dp one though), since that part of the
code is a convoluted mess and needs a cleanup. I have plans for pre-hsw
pch platforms ;-)
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++--------
> drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_dp.c | 10 ++++++----
> 3 files changed, 20 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9eab732..5b4f608 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3304,14 +3304,14 @@
> #define _PIPEB_LINK_M2 0x61048
> #define _PIPEB_LINK_N2 0x6104c
>
> -#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
> -#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
> -#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
> -#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
> -#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
> -#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
> -#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
> -#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
> +#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
> +#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
> +#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
> +#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
> +#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
> +#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
> +#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
> +#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
>
> /* CPU panel fitter */
> /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index dc93c39..95a4a5f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2689,7 +2689,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
>
> /* Write the TU size bits so error detection works */
> I915_WRITE(FDI_RX_TUSIZE1(pipe),
> - I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
> + I915_READ(PIPE_DATA_M1(cpu_transcoder)) & TU_SIZE_MASK);
>
> /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
> reg = FDI_RX_CTL(pipe);
> @@ -4847,7 +4847,7 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> struct intel_encoder *intel_encoder, *edp_encoder = NULL;
> struct fdi_m_n m_n = {0};
> int target_clock, pixel_multiplier, lane, link_bw;
> @@ -4910,10 +4910,10 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
> ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
> &m_n);
>
> - I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
> - I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
> - I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
> - I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
> + I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
> + I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
> + I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
> + I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
> }
>
> static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 697b176..244cb6a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -791,6 +791,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
> int lane_count = 4;
> struct intel_dp_m_n m_n;
> int pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>
> /*
> * Find the lane count in the intel_encoder private
> @@ -815,10 +816,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
> mode->clock, adjusted_mode->clock, &m_n);
>
> if (IS_HASWELL(dev)) {
> - I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
> - I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
> - I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
> - I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
> + I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
> + TU_SIZE(m_n.tu) | m_n.gmch_m);
> + I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
> + I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
> + I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
> } else if (HAS_PCH_SPLIT(dev)) {
> I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
> I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 08/14] drm/i915: convert pipe timing definitions to transcoder
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (6 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 07/14] drm/i915: convert CPU M/N timings " Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 22:29 ` Daniel Vetter
2012-10-18 21:21 ` [PATCH 09/14] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP Paulo Zanoni
` (5 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 7 ++---
drivers/gpu/drm/i915/i915_reg.h | 14 +++++-----
drivers/gpu/drm/i915/intel_crt.c | 6 ++---
drivers/gpu/drm/i915/intel_display.c | 52 +++++++++++++++++++-----------------
4 files changed, 41 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c9b186d..31b266b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -185,6 +185,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
int vbl_start, vbl_end, htotal, vtotal;
bool in_vbl = true;
int ret = 0;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
if (!i915_pipe_enabled(dev, pipe)) {
DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
@@ -193,7 +194,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
}
/* Get vtotal. */
- vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
+ vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
if (INTEL_INFO(dev)->gen >= 4) {
/* No obvious pixelcount register. Only query vertical
@@ -213,13 +214,13 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
*/
position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
- htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
+ htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
*vpos = position / htotal;
*hpos = position - (*vpos * htotal);
}
/* Query vblank area. */
- vbl = I915_READ(VBLANK(pipe));
+ vbl = I915_READ(VBLANK(cpu_transcoder));
/* Test position against vblank region. */
vbl_start = vbl & 0x1fff;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b4f608..f22059e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1565,14 +1565,14 @@
#define _VSYNCSHIFT_B 0x61028
-#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
-#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
-#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
-#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
-#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
-#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
+#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
+#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
+#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
+#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
+#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
+#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
-#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
+#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
/* VGA port control */
#define ADPA 0x61100
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 2a2c976..6e96ba6 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -488,9 +488,9 @@ intel_crt_load_detect(struct intel_crt *crt)
DRM_DEBUG_KMS("starting load-detect on CRT\n");
bclrpat_reg = BCLRPAT(pipe);
- vtotal_reg = VTOTAL(pipe);
- vblank_reg = VBLANK(pipe);
- vsync_reg = VSYNC(pipe);
+ vtotal_reg = VTOTAL(cpu_transcoder);
+ vblank_reg = VBLANK(cpu_transcoder);
+ vsync_reg = VSYNC(cpu_transcoder);
pipeconf_reg = PIPECONF(cpu_transcoder);
pipe_dsl_reg = PIPEDSL(pipe);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 95a4a5f..9202cb6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3019,14 +3019,15 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
/* set transcoder timing, panel must allow it */
assert_panel_unlocked(dev_priv, pipe);
- I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
- I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
- I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
+ I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(cpu_transcoder)));
+ I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(cpu_transcoder)));
+ I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(cpu_transcoder)));
- I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
- I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
- I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
- I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
+ I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
+ I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(cpu_transcoder)));
+ I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(cpu_transcoder)));
+ I915_WRITE(TRANS_VSYNCSHIFT(pipe),
+ I915_READ(VSYNCSHIFT(cpu_transcoder)));
if (!IS_HASWELL(dev))
intel_fdi_normal_train(crtc);
@@ -4339,6 +4340,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
uint32_t vsyncshift;
if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
@@ -4352,25 +4354,25 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
}
if (INTEL_INFO(dev)->gen > 3)
- I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
+ I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
- I915_WRITE(HTOTAL(pipe),
+ I915_WRITE(HTOTAL(cpu_transcoder),
(adjusted_mode->crtc_hdisplay - 1) |
((adjusted_mode->crtc_htotal - 1) << 16));
- I915_WRITE(HBLANK(pipe),
+ I915_WRITE(HBLANK(cpu_transcoder),
(adjusted_mode->crtc_hblank_start - 1) |
((adjusted_mode->crtc_hblank_end - 1) << 16));
- I915_WRITE(HSYNC(pipe),
+ I915_WRITE(HSYNC(cpu_transcoder),
(adjusted_mode->crtc_hsync_start - 1) |
((adjusted_mode->crtc_hsync_end - 1) << 16));
- I915_WRITE(VTOTAL(pipe),
+ I915_WRITE(VTOTAL(cpu_transcoder),
(adjusted_mode->crtc_vdisplay - 1) |
((adjusted_mode->crtc_vtotal - 1) << 16));
- I915_WRITE(VBLANK(pipe),
+ I915_WRITE(VBLANK(cpu_transcoder),
(adjusted_mode->crtc_vblank_start - 1) |
((adjusted_mode->crtc_vblank_end - 1) << 16));
- I915_WRITE(VSYNC(pipe),
+ I915_WRITE(VSYNC(cpu_transcoder),
(adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16));
@@ -6333,12 +6335,12 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
struct drm_display_mode *mode;
- int htot = I915_READ(HTOTAL(pipe));
- int hsync = I915_READ(HSYNC(pipe));
- int vtot = I915_READ(VTOTAL(pipe));
- int vsync = I915_READ(VSYNC(pipe));
+ int htot = I915_READ(HTOTAL(cpu_transcoder));
+ int hsync = I915_READ(HSYNC(cpu_transcoder));
+ int vtot = I915_READ(VTOTAL(cpu_transcoder));
+ int vsync = I915_READ(VSYNC(cpu_transcoder));
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
@@ -8809,12 +8811,12 @@ intel_display_capture_error_state(struct drm_device *dev)
error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
error->pipe[i].source = I915_READ(PIPESRC(i));
- error->pipe[i].htotal = I915_READ(HTOTAL(i));
- error->pipe[i].hblank = I915_READ(HBLANK(i));
- error->pipe[i].hsync = I915_READ(HSYNC(i));
- error->pipe[i].vtotal = I915_READ(VTOTAL(i));
- error->pipe[i].vblank = I915_READ(VBLANK(i));
- error->pipe[i].vsync = I915_READ(VSYNC(i));
+ error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
+ error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
+ error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
+ error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
+ error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
+ error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
}
return error;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 08/14] drm/i915: convert pipe timing definitions to transcoder
2012-10-18 21:21 ` [PATCH 08/14] drm/i915: convert pipe timing definitions " Paulo Zanoni
@ 2012-10-18 22:29 ` Daniel Vetter
0 siblings, 0 replies; 22+ messages in thread
From: Daniel Vetter @ 2012-10-18 22:29 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Thu, Oct 18, 2012 at 06:21:38PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Again, I think we can drop the hunks for the load detect code and the pch
stuff for now. For the pch stuff I think we'll better do that once we give
vga a good look.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_irq.c | 7 ++---
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++-----
> drivers/gpu/drm/i915/intel_crt.c | 6 ++---
> drivers/gpu/drm/i915/intel_display.c | 52 +++++++++++++++++++-----------------
> 4 files changed, 41 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c9b186d..31b266b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -185,6 +185,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
> int vbl_start, vbl_end, htotal, vtotal;
> bool in_vbl = true;
> int ret = 0;
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>
> if (!i915_pipe_enabled(dev, pipe)) {
> DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
> @@ -193,7 +194,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
> }
>
> /* Get vtotal. */
> - vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
> + vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
>
> if (INTEL_INFO(dev)->gen >= 4) {
> /* No obvious pixelcount register. Only query vertical
> @@ -213,13 +214,13 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
> */
> position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
>
> - htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
> + htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
> *vpos = position / htotal;
> *hpos = position - (*vpos * htotal);
> }
>
> /* Query vblank area. */
> - vbl = I915_READ(VBLANK(pipe));
> + vbl = I915_READ(VBLANK(cpu_transcoder));
>
> /* Test position against vblank region. */
> vbl_start = vbl & 0x1fff;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5b4f608..f22059e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1565,14 +1565,14 @@
> #define _VSYNCSHIFT_B 0x61028
>
>
> -#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
> -#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
> -#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
> -#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
> -#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
> -#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
> +#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
> +#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
> +#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
> +#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
> +#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
> +#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
> #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
> -#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
> +#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
>
> /* VGA port control */
> #define ADPA 0x61100
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 2a2c976..6e96ba6 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -488,9 +488,9 @@ intel_crt_load_detect(struct intel_crt *crt)
> DRM_DEBUG_KMS("starting load-detect on CRT\n");
>
> bclrpat_reg = BCLRPAT(pipe);
> - vtotal_reg = VTOTAL(pipe);
> - vblank_reg = VBLANK(pipe);
> - vsync_reg = VSYNC(pipe);
> + vtotal_reg = VTOTAL(cpu_transcoder);
> + vblank_reg = VBLANK(cpu_transcoder);
> + vsync_reg = VSYNC(cpu_transcoder);
> pipeconf_reg = PIPECONF(cpu_transcoder);
> pipe_dsl_reg = PIPEDSL(pipe);
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 95a4a5f..9202cb6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3019,14 +3019,15 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>
> /* set transcoder timing, panel must allow it */
> assert_panel_unlocked(dev_priv, pipe);
> - I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
> - I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
> - I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
> + I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(cpu_transcoder)));
> + I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(cpu_transcoder)));
> + I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(cpu_transcoder)));
>
> - I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
> - I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
> - I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
> - I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
> + I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
> + I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(cpu_transcoder)));
> + I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(cpu_transcoder)));
> + I915_WRITE(TRANS_VSYNCSHIFT(pipe),
> + I915_READ(VSYNCSHIFT(cpu_transcoder)));
>
> if (!IS_HASWELL(dev))
> intel_fdi_normal_train(crtc);
> @@ -4339,6 +4340,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
> struct drm_device *dev = intel_crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum pipe pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> uint32_t vsyncshift;
>
> if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -4352,25 +4354,25 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
> }
>
> if (INTEL_INFO(dev)->gen > 3)
> - I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
> + I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
>
> - I915_WRITE(HTOTAL(pipe),
> + I915_WRITE(HTOTAL(cpu_transcoder),
> (adjusted_mode->crtc_hdisplay - 1) |
> ((adjusted_mode->crtc_htotal - 1) << 16));
> - I915_WRITE(HBLANK(pipe),
> + I915_WRITE(HBLANK(cpu_transcoder),
> (adjusted_mode->crtc_hblank_start - 1) |
> ((adjusted_mode->crtc_hblank_end - 1) << 16));
> - I915_WRITE(HSYNC(pipe),
> + I915_WRITE(HSYNC(cpu_transcoder),
> (adjusted_mode->crtc_hsync_start - 1) |
> ((adjusted_mode->crtc_hsync_end - 1) << 16));
>
> - I915_WRITE(VTOTAL(pipe),
> + I915_WRITE(VTOTAL(cpu_transcoder),
> (adjusted_mode->crtc_vdisplay - 1) |
> ((adjusted_mode->crtc_vtotal - 1) << 16));
> - I915_WRITE(VBLANK(pipe),
> + I915_WRITE(VBLANK(cpu_transcoder),
> (adjusted_mode->crtc_vblank_start - 1) |
> ((adjusted_mode->crtc_vblank_end - 1) << 16));
> - I915_WRITE(VSYNC(pipe),
> + I915_WRITE(VSYNC(cpu_transcoder),
> (adjusted_mode->crtc_vsync_start - 1) |
> ((adjusted_mode->crtc_vsync_end - 1) << 16));
>
> @@ -6333,12 +6335,12 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> struct drm_display_mode *mode;
> - int htot = I915_READ(HTOTAL(pipe));
> - int hsync = I915_READ(HSYNC(pipe));
> - int vtot = I915_READ(VTOTAL(pipe));
> - int vsync = I915_READ(VSYNC(pipe));
> + int htot = I915_READ(HTOTAL(cpu_transcoder));
> + int hsync = I915_READ(HSYNC(cpu_transcoder));
> + int vtot = I915_READ(VTOTAL(cpu_transcoder));
> + int vsync = I915_READ(VSYNC(cpu_transcoder));
>
> mode = kzalloc(sizeof(*mode), GFP_KERNEL);
> if (!mode)
> @@ -8809,12 +8811,12 @@ intel_display_capture_error_state(struct drm_device *dev)
>
> error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
> error->pipe[i].source = I915_READ(PIPESRC(i));
> - error->pipe[i].htotal = I915_READ(HTOTAL(i));
> - error->pipe[i].hblank = I915_READ(HBLANK(i));
> - error->pipe[i].hsync = I915_READ(HSYNC(i));
> - error->pipe[i].vtotal = I915_READ(VTOTAL(i));
> - error->pipe[i].vblank = I915_READ(VBLANK(i));
> - error->pipe[i].vsync = I915_READ(VSYNC(i));
> + error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
> + error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
> + error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
> + error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
> + error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
> + error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
> }
>
> return error;
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 09/14] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (7 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 08/14] drm/i915: convert pipe timing definitions " Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 21:21 ` [PATCH 10/14] drm/i915: select the correct pipe " Paulo Zanoni
` (4 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
See the documentation for the DDI_FUNC_CTL register, EDP Input Select
bits: when the EDP input selection is B, the VTOTAL_B must be
programmed with the VTOTAL_EDP value, same thing for selection C.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9202cb6..cc859b3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4376,6 +4376,17 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
(adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16));
+ /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
+ * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
+ * documented on the DDI_FUNC_CTL register description, EDP Input Select
+ * bits. */
+ if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
+ (pipe == PIPE_B || pipe == PIPE_C)) {
+ I915_WRITE(VTOTAL(pipe),
+ (adjusted_mode->crtc_vdisplay - 1) |
+ ((adjusted_mode->crtc_vtotal - 1) << 16));
+ }
+
/* pipesrc controls the size that is scaled from, which should
* always be the user's requested size.
*/
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 10/14] drm/i915: select the correct pipe when using TRANSCODER_EDP
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (8 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 09/14] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 21:21 ` [PATCH 11/14] drm/i915: set the correct eDP aux channel clock divider on DDI Paulo Zanoni
` (3 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c30cb14..08881f1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -954,6 +954,23 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
temp |= TRANS_DDI_PHSYNC;
+ if (cpu_transcoder == TRANSCODER_EDP) {
+ switch (pipe) {
+ case PIPE_A:
+ temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
+ break;
+ case PIPE_B:
+ temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
+ break;
+ case PIPE_C:
+ temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
+ break;
+ default:
+ BUG();
+ break;
+ }
+ }
+
if (type == INTEL_OUTPUT_HDMI) {
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 11/14] drm/i915: set the correct eDP aux channel clock divider on DDI
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (9 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 10/14] drm/i915: select the correct pipe " Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 21:21 ` [PATCH 12/14] drm/i915: set/unset the DDI eDP backlight Paulo Zanoni
` (2 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
The cdclk frequency is not always the same, so the value here should
be adjusted to match it.
Version 2: call intel_ddi_get_cdclk_freq instead of reading
CDCLK_FREQ, because the register is just for earlier HW steppings.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 4 +++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 08881f1..5e21bc1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1238,7 +1238,7 @@ void intel_disable_ddi(struct intel_encoder *encoder)
/* This will be needed in the future, so leave it here for now */
}
-static int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
+int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
{
if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
return 450;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 244cb6a..9486f11 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -386,7 +386,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
* clock divider.
*/
if (is_cpu_edp(intel_dp)) {
- if (IS_VALLEYVIEW(dev))
+ if (IS_HASWELL(dev))
+ aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
+ else if (IS_VALLEYVIEW(dev))
aux_clock_divider = 100;
else if (IS_GEN6(dev) || IS_GEN7(dev))
aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5bc1ddd..ed436d0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -593,6 +593,7 @@ extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
extern void intel_ddi_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
+extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
extern void intel_ddi_pll_init(struct drm_device *dev);
extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 12/14] drm/i915: set/unset the DDI eDP backlight
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (10 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 11/14] drm/i915: set the correct eDP aux channel clock divider on DDI Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 21:21 ` [PATCH 13/14] drm/i915: turn the eDP DDI panel on/off Paulo Zanoni
2012-10-18 21:21 ` [PATCH 14/14] drm/i915: enable DDI eDP Paulo Zanoni
13 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 15 +++++++++++++--
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 6 ++++--
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5e21bc1..48eb125 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1230,12 +1230,23 @@ void intel_enable_ddi(struct intel_encoder *intel_encoder)
* enabling the port.
*/
I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE);
+ } else if (type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ ironlake_edp_backlight_on(intel_dp);
}
}
-void intel_disable_ddi(struct intel_encoder *encoder)
+void intel_disable_ddi(struct intel_encoder *intel_encoder)
{
- /* This will be needed in the future, so leave it here for now */
+ struct drm_encoder *encoder = &intel_encoder->base;
+ int type = intel_encoder->type;
+
+ if (type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ ironlake_edp_backlight_off(intel_dp);
+ }
}
int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9486f11..f241f49 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1178,7 +1178,7 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
ironlake_wait_panel_off(intel_dp);
}
-static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
+void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1201,7 +1201,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
POSTING_READ(PCH_PP_CONTROL);
}
-static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
+void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ed436d0..7247950 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -428,6 +428,8 @@ extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
extern bool intel_dpd_is_edp(struct drm_device *dev);
+extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
+extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
extern int intel_edp_target_clock(struct intel_encoder *,
struct drm_display_mode *mode);
@@ -586,8 +588,8 @@ extern void intel_disable_gt_powersave(struct drm_device *dev);
extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
extern void ironlake_teardown_rc6(struct drm_device *dev);
-extern void intel_enable_ddi(struct intel_encoder *encoder);
-extern void intel_disable_ddi(struct intel_encoder *encoder);
+extern void intel_enable_ddi(struct intel_encoder *intel_encoder);
+extern void intel_disable_ddi(struct intel_encoder *intel_encoder);
extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe);
extern void intel_ddi_mode_set(struct drm_encoder *encoder,
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 13/14] drm/i915: turn the eDP DDI panel on/off
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (11 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 12/14] drm/i915: set/unset the DDI eDP backlight Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
2012-10-18 21:21 ` [PATCH 14/14] drm/i915: enable DDI eDP Paulo Zanoni
13 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
It's an important step :)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++++++--
drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
drivers/gpu/drm/i915/intel_drv.h | 4 ++++
3 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 48eb125..91f126b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1162,12 +1162,19 @@ void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ int type = intel_encoder->type;
- WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
+ if (type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ ironlake_edp_panel_vdd_on(intel_dp);
+ ironlake_edp_panel_on(intel_dp);
+ ironlake_edp_panel_vdd_off(intel_dp, true);
+ }
+ WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
- if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+ if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
@@ -1195,6 +1202,7 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ int type = intel_encoder->type;
uint32_t val;
bool wait = false;
@@ -1213,6 +1221,12 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
+ if (type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ ironlake_edp_panel_vdd_on(intel_dp);
+ ironlake_edp_panel_off(intel_dp);
+ }
+
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f241f49..14921a8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -667,9 +667,6 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
return -EREMOTEIO;
}
-static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
-static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
-
static int
intel_dp_i2c_init(struct intel_dp *intel_dp,
struct intel_connector *intel_connector, const char *name)
@@ -1018,7 +1015,7 @@ static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
return control;
}
-static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
+void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1088,7 +1085,7 @@ static void ironlake_panel_vdd_work(struct work_struct *__work)
mutex_unlock(&dev->mode_config.mutex);
}
-static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
+void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
{
if (!is_edp(intel_dp))
return;
@@ -1111,7 +1108,7 @@ static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
}
}
-static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
+void ironlake_edp_panel_on(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1153,7 +1150,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
}
}
-static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
+void ironlake_edp_panel_off(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7247950..b9eb888 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -430,6 +430,10 @@ extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
extern bool intel_dpd_is_edp(struct drm_device *dev);
extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
+extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
+extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
+extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
+extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
extern int intel_edp_target_clock(struct intel_encoder *,
struct drm_display_mode *mode);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 14/14] drm/i915: enable DDI eDP
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
` (12 preceding siblings ...)
2012-10-18 21:21 ` [PATCH 13/14] drm/i915: turn the eDP DDI panel on/off Paulo Zanoni
@ 2012-10-18 21:21 ` Paulo Zanoni
13 siblings, 0 replies; 22+ messages in thread
From: Paulo Zanoni @ 2012-10-18 21:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Now that all the eDP enablement bits are there, we can actually try to
use the eDP.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 91f126b..4890f67 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -242,8 +242,8 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
switch(port){
case PORT_A:
- /* We don't handle eDP and DP yet */
DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
+ intel_dp_init(dev, DDI_BUF_CTL_A, PORT_A);
break;
/* Assume that the ports B, C and D are working in HDMI mode for now */
case PORT_B:
--
1.7.11.4
^ permalink raw reply related [flat|nested] 22+ messages in thread