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From: Shobhit Kumar <shobhit.kumar@intel.com>
To: intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: jani.nikula@intel.com, vijayakumar.balakrishnan@intel.com,
	yogesh.mohan.marimuthu@intel.com
Subject: [PATCH v2 4/7] drm/i915: Try harder to get best m, n, p values with minimal error
Date: Sat,  9 Nov 2013 15:19:05 +0530	[thread overview]
Message-ID: <1383990548-30737-5-git-send-email-shobhit.kumar@intel.com> (raw)
In-Reply-To: <1383990548-30737-1-git-send-email-shobhit.kumar@intel.com>

Basically check for both +ive and -ive deviation from target clock and
pick the one with minimal error. If we get a direct match, break from
loop to acheive some optimization.

Signed-off-by: Vijayakumar Balakrishnan <vijayakumar.balakrishnan@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |   26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 9f3e6b0..16bc6b2 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -243,22 +243,32 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
 	ref_clk = 25000;
 	target_dsi_clk = dsi_clk;
 	error = 0xFFFFFFFF;
+	tmp_error = 0xFFFFFFFF;
 	calc_m = 0;
 	calc_p = 0;
 
 	for (m = 62; m <= 92; m++) {
 		for (p = 2; p <= 6; p++) {
-
+			/* Find the optimal m and p divisors
+			with minimal error +/- the required clock */
 			calc_dsi_clk = (m * ref_clk) / p;
-			if (calc_dsi_clk >= target_dsi_clk) {
-				tmp_error = calc_dsi_clk - target_dsi_clk;
-				if (tmp_error < error) {
-					error = tmp_error;
-					calc_m = m;
-					calc_p = p;
-				}
+			if (calc_dsi_clk == target_dsi_clk) {
+				calc_m = m;
+				calc_p = p;
+				error = 0;
+				break;
+			} else
+				tmp_error = abs(target_dsi_clk - calc_dsi_clk);
+
+			if (tmp_error < error) {
+				error = tmp_error;
+				calc_m = m;
+				calc_p = p;
 			}
 		}
+
+		if (error == 0)
+			break;
 	}
 
 	m_seed = lfsr_converts[calc_m - 62];
-- 
1.7.9.5

  parent reply	other threads:[~2013-11-09  9:41 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-11-09  9:49 [PATCH v2 0/7] drm/i915: Baytrail MIPI DSI support Updated Shobhit Kumar
2013-11-09  9:49 ` [PATCH v2 1/7] drm/i915: Add more dev ops for MIPI sub encoder Shobhit Kumar
2013-11-15  8:29   ` Jani Nikula
2013-11-09  9:49 ` [PATCH v2 2/7] drm/i915: Use FLISDSI interface for band gap reset Shobhit Kumar
2013-11-15  9:10   ` Jani Nikula
2013-11-09  9:49 ` [PATCH v2 3/7] drm/i915: Compute dsi_clk from pixel clock Shobhit Kumar
2013-11-15  7:22   ` Jani Nikula
2013-11-15  8:40     ` Jani Nikula
2013-11-09  9:49 ` Shobhit Kumar [this message]
2013-11-15  7:19   ` [PATCH v2 4/7] drm/i915: Try harder to get best m, n, p values with minimal error Jani Nikula
2013-11-09  9:49 ` [PATCH v2 5/7] drm/i915: Reorganize the DSI enable/disable sequence Shobhit Kumar
2013-11-15  8:27   ` Jani Nikula
2013-11-15  8:55     ` Daniel Vetter
2013-11-20  1:39       ` Shobhit Kumar
2013-12-06 11:20         ` Shobhit Kumar
2013-12-06 11:25     ` Shobhit Kumar
2013-11-09  9:49 ` [PATCH v2 6/7] drm/i915: Remove redundant DSI PLL enabling Shobhit Kumar
2013-11-15  8:41   ` Jani Nikula
2013-11-09  9:49 ` [PATCH v2 7/7] drm/i915: Parametrize the dphy and other spec specific parameters Shobhit Kumar
2013-11-15  7:52   ` Jani Nikula
2013-11-15  8:42     ` Jani Nikula
2013-11-09 10:28 ` [PATCH v2 0/7] drm/i915: Baytrail MIPI DSI support Updated Daniel Vetter
2013-11-11  8:50   ` [Intel-gfx] " Thierry Reding
2013-11-11 10:28     ` Shobhit Kumar
     [not found]       ` <52A7F4A0.6050902@intel.com>
     [not found]         ` <CAKMK7uGU=R3j1TDgLZzUKtztrY6P_akzHHeWEQy_Jw7DdQpiTg@mail.gmail.com>
     [not found]           ` <87r49j60ym.fsf@intel.com>
     [not found]             ` <52A86FF2.5050200@intel.com>
     [not found]               ` <CAKMK7uGA-ENZRQySGVrDkBy7dTOigkKpwpTn63rfGM+UAGvPZA@mail.gmail.com>
2013-12-11 14:25                 ` Daniel Vetter

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