From: Jani Nikula <jani.nikula@intel.com>
To: Shobhit Kumar <shobhit.kumar@intel.com>,
intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: vijayakumar.balakrishnan@intel.com, yogesh.mohan.marimuthu@intel.com
Subject: Re: [PATCH v2 6/7] drm/i915: Remove redundant DSI PLL enabling
Date: Fri, 15 Nov 2013 10:41:55 +0200 [thread overview]
Message-ID: <87iovugip8.fsf@intel.com> (raw)
In-Reply-To: <1383990548-30737-7-git-send-email-shobhit.kumar@intel.com>
On Sat, 09 Nov 2013, Shobhit Kumar <shobhit.kumar@intel.com> wrote:
> DSI PLL will get configured during crtc_enable using ->pre_pll_enable
> and no need to do in ->mode_set
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 9e67f78..4dccb4b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -373,9 +373,6 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
>
> DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
>
> - /* Update the DSI PLL */
> - vlv_enable_dsi_pll(intel_encoder);
> -
> /* XXX: Location of the call */
> band_gap_reset(dev_priv);
>
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
next prev parent reply other threads:[~2013-11-15 8:45 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-09 9:49 [PATCH v2 0/7] drm/i915: Baytrail MIPI DSI support Updated Shobhit Kumar
2013-11-09 9:49 ` [PATCH v2 1/7] drm/i915: Add more dev ops for MIPI sub encoder Shobhit Kumar
2013-11-15 8:29 ` Jani Nikula
2013-11-09 9:49 ` [PATCH v2 2/7] drm/i915: Use FLISDSI interface for band gap reset Shobhit Kumar
2013-11-15 9:10 ` Jani Nikula
2013-11-09 9:49 ` [PATCH v2 3/7] drm/i915: Compute dsi_clk from pixel clock Shobhit Kumar
2013-11-15 7:22 ` Jani Nikula
2013-11-15 8:40 ` Jani Nikula
2013-11-09 9:49 ` [PATCH v2 4/7] drm/i915: Try harder to get best m, n, p values with minimal error Shobhit Kumar
2013-11-15 7:19 ` Jani Nikula
2013-11-09 9:49 ` [PATCH v2 5/7] drm/i915: Reorganize the DSI enable/disable sequence Shobhit Kumar
2013-11-15 8:27 ` Jani Nikula
2013-11-15 8:55 ` Daniel Vetter
2013-11-20 1:39 ` Shobhit Kumar
2013-12-06 11:20 ` Shobhit Kumar
2013-12-06 11:25 ` Shobhit Kumar
2013-11-09 9:49 ` [PATCH v2 6/7] drm/i915: Remove redundant DSI PLL enabling Shobhit Kumar
2013-11-15 8:41 ` Jani Nikula [this message]
2013-11-09 9:49 ` [PATCH v2 7/7] drm/i915: Parametrize the dphy and other spec specific parameters Shobhit Kumar
2013-11-15 7:52 ` Jani Nikula
2013-11-15 8:42 ` Jani Nikula
2013-11-09 10:28 ` [PATCH v2 0/7] drm/i915: Baytrail MIPI DSI support Updated Daniel Vetter
2013-11-11 8:50 ` [Intel-gfx] " Thierry Reding
2013-11-11 10:28 ` Shobhit Kumar
[not found] ` <52A7F4A0.6050902@intel.com>
[not found] ` <CAKMK7uGU=R3j1TDgLZzUKtztrY6P_akzHHeWEQy_Jw7DdQpiTg@mail.gmail.com>
[not found] ` <87r49j60ym.fsf@intel.com>
[not found] ` <52A86FF2.5050200@intel.com>
[not found] ` <CAKMK7uGA-ENZRQySGVrDkBy7dTOigkKpwpTn63rfGM+UAGvPZA@mail.gmail.com>
2013-12-11 14:25 ` Daniel Vetter
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