From: tom.orourke@intel.com
To: intel-gfx@lists.freedesktop.org
Cc: paulo.r.zanoni@intel.com, Tom O'Rourke <Tom.O'Rourke@intel.com>
Subject: [PATCH 14/26] drm/i915/slpc: Notification of Display mode change
Date: Tue, 8 Mar 2016 16:34:17 -0800 [thread overview]
Message-ID: <1457483669-155235-15-git-send-email-tom.orourke@intel.com> (raw)
In-Reply-To: <1457483669-155235-1-git-send-email-tom.orourke@intel.com>
From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
GuC SLPC need to be sent data related to Active pipes, refresh rates,
widi pipes, fullscreen pipes related via host to GuC display mode
change event. Based on this, SLPC will track FPS on active pipes.
This patch defines the event and implements trigger of the event.
v2: Addressed review comments from Paulo and Ville. Changed the way
display mode information is collected in intel_atomic_commit. Coupled
display mode change event with SLPC enable/reset event. Updated inactive
crtc state in display mode data. Updated refresh rate and vsync_ft_usec
calculations to get more accurate value. (Paulo)
v2(torourke): Updates suggested by Paulo: replace HAS_SLPC with
intel_slpc_active. return void instead of ignored error code.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +
drivers/gpu/drm/i915/intel_slpc.c | 142 ++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_slpc.h | 3 +
3 files changed, 146 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 62d36a7..ac398f3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13820,6 +13820,8 @@ static int intel_atomic_commit(struct drm_device *dev,
if (hw_check)
intel_modeset_check_state(dev, state);
+ intel_slpc_update_atomic_commit_info(dev, state);
+
drm_atomic_state_free(state);
/* As one of the primary mmio accessors, KMS has a high likelihood
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index b6ba071..58f90b3 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -73,6 +73,21 @@ static void host2guc_slpc_shutdown(struct drm_device *dev)
host2guc_slpc(dev_priv, data, 4);
}
+static void host2guc_slpc_display_mode_change(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 data[7];
+ int i;
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_DISPLAY_MODE_CHANGE, SLPC_MAX_NUM_OF_PIPES + 1);
+ data[2] = dev_priv->guc.slpc.display_mode_params.global_data;
+ for(i = 0; i < SLPC_MAX_NUM_OF_PIPES; ++i)
+ data[3+i] = dev_priv->guc.slpc.display_mode_params.per_pipe_info[i].data;
+
+ host2guc_slpc(dev_priv, data, 7);
+}
+
static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
{
struct drm_device *dev = obj->base.dev;
@@ -181,8 +196,10 @@ void intel_slpc_disable(struct drm_device *dev)
void intel_slpc_enable(struct drm_device *dev)
{
- if (intel_slpc_active(dev))
+ if (intel_slpc_active(dev)) {
host2guc_slpc_reset(dev);
+ intel_slpc_update_display_mode_info(dev);
+ }
}
void intel_slpc_reset(struct drm_device *dev)
@@ -192,3 +209,126 @@ void intel_slpc_reset(struct drm_device *dev)
host2guc_slpc_reset(dev);
}
}
+
+void intel_slpc_update_display_mode_info(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc;
+ struct intel_display_pipe_info *per_pipe_info;
+ struct intel_slpc_display_mode_event_params *cur_params, old_params;
+ bool notify = false;
+
+ if (!intel_slpc_active(dev))
+ return;
+
+ /* Copy display mode parameters for comparison */
+ cur_params = &dev_priv->guc.slpc.display_mode_params;
+ old_params.global_data = cur_params->global_data;
+ cur_params->global_data = 0;
+
+ intel_runtime_pm_get(dev_priv);
+ drm_modeset_lock_all(dev);
+
+ for_each_intel_crtc(dev, intel_crtc) {
+ per_pipe_info = &cur_params->per_pipe_info[intel_crtc->pipe];
+ old_params.per_pipe_info[intel_crtc->pipe].data = per_pipe_info->data;
+ per_pipe_info->data = 0;
+
+ if (intel_crtc->active) {
+ struct drm_display_mode *mode = &intel_crtc->base.mode;
+ /* FIXME: Update is_widi based on encoder */
+ per_pipe_info->is_widi = 0;
+ per_pipe_info->refresh_rate =
+ (mode->clock * 1000)/ (mode->htotal * mode->vtotal);
+ if (!per_pipe_info->refresh_rate) {
+ DRM_ERROR("Invalid mode refresh rate\n");
+ drm_modeset_unlock_all(dev);
+ intel_runtime_pm_put(dev_priv);
+ return;
+ }
+ per_pipe_info->vsync_ft_usec =
+ (mode->htotal * mode->vtotal * 1000) / mode->clock;
+ cur_params->active_pipes_bitmask |= (1 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes |= (1 << intel_crtc->pipe);
+ } else {
+ cur_params->active_pipes_bitmask &= (0 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes &= (0 << intel_crtc->pipe);
+ }
+
+ if (old_params.per_pipe_info[intel_crtc->pipe].data != per_pipe_info->data)
+ notify = true;
+ }
+
+ drm_modeset_unlock_all(dev);
+
+ cur_params->num_active_pipes = hweight32(cur_params->active_pipes_bitmask);
+
+ /* Compare old display mode with current mode. Notify SLPC if it is changed. */
+ if (cur_params->global_data != old_params.global_data)
+ notify = true;
+
+ if (notify) {
+ host2guc_slpc_display_mode_change(dev);
+ }
+
+ intel_runtime_pm_put(dev_priv);
+}
+
+void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
+ struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *crtc_state;
+ struct intel_display_pipe_info *per_pipe_info;
+ struct intel_slpc_display_mode_event_params *cur_params, old_params;
+ bool notify = false;
+ int i;
+
+ if (!intel_slpc_active(dev))
+ return;
+
+ /* Copy display mode parameters for comparison */
+ cur_params = &dev_priv->guc.slpc.display_mode_params;
+ old_params.global_data = cur_params->global_data;
+
+ for_each_crtc_in_state(state, crtc, crtc_state, i) {
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ per_pipe_info = &cur_params->per_pipe_info[intel_crtc->pipe];
+ old_params.per_pipe_info[intel_crtc->pipe].data = per_pipe_info->data;
+
+ per_pipe_info->data = 0;
+ cur_params->active_pipes_bitmask &= (0 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes &= (0 << intel_crtc->pipe);
+
+ if (crtc_state->active) {
+ struct drm_display_mode *mode = &crtc->mode;
+ /* FIXME: Update is_widi based on encoder */
+ per_pipe_info->is_widi = 0;
+ per_pipe_info->refresh_rate =
+ (mode->clock * 1000)/ (mode->htotal * mode->vtotal);
+ if (!per_pipe_info->refresh_rate) {
+ DRM_ERROR("Invalid mode refresh rate\n");
+ return;
+ }
+ per_pipe_info->vsync_ft_usec =
+ (mode->htotal * mode->vtotal * 1000) / mode->clock;
+ cur_params->active_pipes_bitmask |= (1 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes |= (1 << intel_crtc->pipe);
+ }
+
+ if (old_params.per_pipe_info[intel_crtc->pipe].data != per_pipe_info->data)
+ notify = true;
+ }
+
+ cur_params->num_active_pipes = hweight32(cur_params->active_pipes_bitmask);
+
+ /* Compare old display mode with current mode. Notify SLPC if it is changed. */
+ if (cur_params->global_data != old_params.global_data)
+ notify = true;
+
+ if (notify) {
+ host2guc_slpc_display_mode_change(dev);
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index b963fe7..d560d86 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -149,5 +149,8 @@ void intel_slpc_suspend(struct drm_device *dev);
void intel_slpc_disable(struct drm_device *dev);
void intel_slpc_enable(struct drm_device *dev);
void intel_slpc_reset(struct drm_device *dev);
+void intel_slpc_update_display_mode_info(struct drm_device *dev);
+void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
+ struct drm_atomic_state *state);
#endif
--
1.9.1
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next prev parent reply other threads:[~2016-03-09 0:35 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
2016-03-09 0:34 ` [PATCH 01/26] drm/i915/slpc: Expose guc functions for use with SLPC tom.orourke
2016-03-09 0:34 ` [PATCH 02/26] drm/i915/slpc: Add has_slpc capability flag tom.orourke
2016-03-09 0:34 ` [PATCH 03/26] drm/i915/slpc: Add slpc_version_check tom.orourke
2016-03-09 0:34 ` [PATCH 04/26] drm/i915/slpc: Add enable_slpc module parameter tom.orourke
2016-03-09 0:34 ` [PATCH 05/26] drm/i915/slpc: Use intel_slpc_* functions if supported tom.orourke
2016-03-09 0:34 ` [PATCH 06/26] drm/i915/slpc: Enable SLPC in guc " tom.orourke
2016-03-09 0:34 ` [PATCH 07/26] drm/i915/slpc: If using SLPC, do not set frequency tom.orourke
2016-03-09 0:34 ` [PATCH 08/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data tom.orourke
2016-03-09 0:34 ` [PATCH 09/26] drm/i915/slpc: Setup rps frequency values during SLPC init tom.orourke
2016-03-09 0:34 ` [PATCH 10/26] drm/i915/slpc: Update current requested frequency tom.orourke
2016-03-09 0:34 ` [PATCH 11/26] drm/i915/slpc: Send reset event tom.orourke
2016-03-09 0:34 ` [PATCH 12/26] drm/i915/slpc: Send shutdown event tom.orourke
2016-03-09 0:34 ` [PATCH 13/26] drm/i915/slpc: Add Display mode event related data structures tom.orourke
2016-03-09 0:34 ` tom.orourke [this message]
2016-03-09 0:34 ` [PATCH 15/26] drm/i915/slpc: Notification of Refresh Rate change tom.orourke
2016-03-09 0:34 ` [PATCH 16/26] drm/i915/slpc: Add slpc_status enum values tom.orourke
2016-03-09 0:34 ` [PATCH 17/26] drm/i915/slpc: Add parameter unset/set/get functions tom.orourke
2016-03-09 0:34 ` [PATCH 18/26] drm/i915/slpc: Add slpc support for max/min freq tom.orourke
2016-03-09 0:34 ` [PATCH 19/26] drm/i915/slpc: Add enable/disable debugfs for slpc tom.orourke
2016-03-09 0:34 ` [PATCH 20/26] drm/i915/slpc: Add broxton support tom.orourke
2016-03-09 0:34 ` [PATCH 21/26] drm/i915/slpc: Add i915_slpc_info to debugfs tom.orourke
2016-03-09 0:34 ` [PATCH 22/26] DO NOT MERGE: drm/i915: Change SKL guc version wanted to 6.0 tom.orourke
2016-03-09 0:34 ` [PATCH 23/26] DO NOT MERGE: drm/i915/bxt: Add Broxton to guc loader tom.orourke
2016-03-09 0:34 ` [PATCH 24/26] DO NOT MERGE: drm/i915: resize the GuC WOPCM for rc6 tom.orourke
2016-03-09 0:34 ` [PATCH 25/26] DO NOT MERGE: drm/i915: Enable GuC submission, where supported tom.orourke
2016-03-09 0:34 ` [PATCH 26/26] DO NOT MERGE: drm/i915: Enable SLPC, " tom.orourke
2016-03-09 8:03 ` ✗ Fi.CI.BAT: failure for Add support for GuC-based SLPC (rev2) Patchwork
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