From: tom.orourke@intel.com
To: intel-gfx@lists.freedesktop.org
Cc: paulo.r.zanoni@intel.com, Tom O'Rourke <Tom.O'Rourke@intel.com>
Subject: [PATCH 04/26] drm/i915/slpc: Add enable_slpc module parameter
Date: Tue, 8 Mar 2016 16:34:07 -0800 [thread overview]
Message-ID: <1457483669-155235-5-git-send-email-tom.orourke@intel.com> (raw)
In-Reply-To: <1457483669-155235-1-git-send-email-tom.orourke@intel.com>
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check(). This function also enforces the requirement
that guc_submission is required for slpc.
intel_slpc_enabled() returns 1 if SLPC should be used.
Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 6 ++++++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_guc.h | 6 ++++++
drivers/gpu/drm/i915/intel_guc_loader.c | 17 +++++++++++++++++
4 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 278c9c4..1cee0ea 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
.enable_dc = -1,
.enable_fbc = -1,
.enable_execlists = -1,
+ .enable_slpc = 0,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = -1,
@@ -125,6 +126,11 @@ MODULE_PARM_DESC(enable_execlists,
"Override execlists usage. "
"(-1=auto [default], 0=disabled, 1=enabled)");
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+ "Override single-loop-power-controller (slpc) usage. "
+ "(-1=auto, 0=disabled [default], 1=enabled)");
+
module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
MODULE_PARM_DESC(enable_psr, "Enable PSR "
"(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index bd5026b..3de9fb8 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
int enable_fbc;
int enable_ppgtt;
int enable_execlists;
+ int enable_slpc;
int enable_psr;
unsigned int preliminary_hw_support;
int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index b18f5c3..298e243 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -110,6 +110,12 @@ struct intel_guc {
uint32_t last_seqno[GUC_MAX_ENGINES_NUM];
};
+static inline int intel_slpc_enabled(void)
+{
+ WARN_ON(i915.enable_slpc < 0);
+ return i915.enable_slpc;
+}
+
/* intel_guc_loader.c */
extern void intel_guc_ucode_init(struct drm_device *dev);
extern int intel_guc_ucode_load(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 22d7587..d63f358 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -116,6 +116,21 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
I915_WRITE(GUC_WD_VECS_IER, ~irqs);
}
+static void slpc_enable_sanitize(struct drm_device *dev)
+{
+ /* handle default case */
+ if (i915.enable_slpc < 0)
+ i915.enable_slpc = HAS_SLPC(dev);
+
+ /* slpc requires hardware support and compatible firmware */
+ if (!HAS_SLPC(dev))
+ i915.enable_slpc = 0;
+
+ /* slpc requires guc submission */
+ if (!i915.enable_guc_submission)
+ i915.enable_slpc = 0;
+}
+
static void slpc_version_check(struct drm_device *dev, struct intel_guc_fw *guc_fw)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -125,6 +140,8 @@ static void slpc_version_check(struct drm_device *dev, struct intel_guc_fw *guc_
info = (struct intel_device_info *) &dev_priv->info;
info->has_slpc = 0;
}
+
+ slpc_enable_sanitize(dev);
}
static u32 get_gttype(struct drm_i915_private *dev_priv)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-03-09 0:35 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
2016-03-09 0:34 ` [PATCH 01/26] drm/i915/slpc: Expose guc functions for use with SLPC tom.orourke
2016-03-09 0:34 ` [PATCH 02/26] drm/i915/slpc: Add has_slpc capability flag tom.orourke
2016-03-09 0:34 ` [PATCH 03/26] drm/i915/slpc: Add slpc_version_check tom.orourke
2016-03-09 0:34 ` tom.orourke [this message]
2016-03-09 0:34 ` [PATCH 05/26] drm/i915/slpc: Use intel_slpc_* functions if supported tom.orourke
2016-03-09 0:34 ` [PATCH 06/26] drm/i915/slpc: Enable SLPC in guc " tom.orourke
2016-03-09 0:34 ` [PATCH 07/26] drm/i915/slpc: If using SLPC, do not set frequency tom.orourke
2016-03-09 0:34 ` [PATCH 08/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data tom.orourke
2016-03-09 0:34 ` [PATCH 09/26] drm/i915/slpc: Setup rps frequency values during SLPC init tom.orourke
2016-03-09 0:34 ` [PATCH 10/26] drm/i915/slpc: Update current requested frequency tom.orourke
2016-03-09 0:34 ` [PATCH 11/26] drm/i915/slpc: Send reset event tom.orourke
2016-03-09 0:34 ` [PATCH 12/26] drm/i915/slpc: Send shutdown event tom.orourke
2016-03-09 0:34 ` [PATCH 13/26] drm/i915/slpc: Add Display mode event related data structures tom.orourke
2016-03-09 0:34 ` [PATCH 14/26] drm/i915/slpc: Notification of Display mode change tom.orourke
2016-03-09 0:34 ` [PATCH 15/26] drm/i915/slpc: Notification of Refresh Rate change tom.orourke
2016-03-09 0:34 ` [PATCH 16/26] drm/i915/slpc: Add slpc_status enum values tom.orourke
2016-03-09 0:34 ` [PATCH 17/26] drm/i915/slpc: Add parameter unset/set/get functions tom.orourke
2016-03-09 0:34 ` [PATCH 18/26] drm/i915/slpc: Add slpc support for max/min freq tom.orourke
2016-03-09 0:34 ` [PATCH 19/26] drm/i915/slpc: Add enable/disable debugfs for slpc tom.orourke
2016-03-09 0:34 ` [PATCH 20/26] drm/i915/slpc: Add broxton support tom.orourke
2016-03-09 0:34 ` [PATCH 21/26] drm/i915/slpc: Add i915_slpc_info to debugfs tom.orourke
2016-03-09 0:34 ` [PATCH 22/26] DO NOT MERGE: drm/i915: Change SKL guc version wanted to 6.0 tom.orourke
2016-03-09 0:34 ` [PATCH 23/26] DO NOT MERGE: drm/i915/bxt: Add Broxton to guc loader tom.orourke
2016-03-09 0:34 ` [PATCH 24/26] DO NOT MERGE: drm/i915: resize the GuC WOPCM for rc6 tom.orourke
2016-03-09 0:34 ` [PATCH 25/26] DO NOT MERGE: drm/i915: Enable GuC submission, where supported tom.orourke
2016-03-09 0:34 ` [PATCH 26/26] DO NOT MERGE: drm/i915: Enable SLPC, " tom.orourke
2016-03-09 8:03 ` ✗ Fi.CI.BAT: failure for Add support for GuC-based SLPC (rev2) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1457483669-155235-5-git-send-email-tom.orourke@intel.com \
--to=tom.orourke@intel.com \
--cc=Tom.O'Rourke@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=paulo.r.zanoni@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox