[PATCH 1/6] drm/i915/skl+: Add and enable DP AUX CH mutex

[PATCH 1/6] drm/i915/skl+: Add and enable DP AUX CH mutex

[José Roberto de Souza]

***
Please do not send review to this patch here, it was sent separated
https://lists.freedesktop.org/archives/intel-gfx/2018-February/156921.html
it is only included here to avoid concurrency access when reading
sink PSR status and errors registers
***

When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
self, so lets use the mutex register that is available in gen9+ to
avoid concurrent access by hardware and driver.
Older gen handling will be done separated.

Reference: https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol12-display.pdf
Page 198 - AUX programming sequence

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  9 ++++++
 drivers/gpu/drm/i915/intel_dp.c  | 67 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 3 files changed, 77 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eea5b2c537d4..f36e839b4b4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5385,6 +5385,15 @@ enum {
 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
 
+#define _DPA_AUX_CH_MUTEX	(dev_priv->info.display_mmio_offset + 0x6402C)
+#define _DPB_AUX_CH_MUTEX	(dev_priv->info.display_mmio_offset + 0x6412C)
+#define _DPC_AUX_CH_MUTEX	(dev_priv->info.display_mmio_offset + 0x6422C)
+#define _DPD_AUX_CH_MUTEX	(dev_priv->info.display_mmio_offset + 0x6432C)
+#define _DPF_AUX_CH_MUTEX	(dev_priv->info.display_mmio_offset + 0x6452C)
+#define DP_AUX_CH_MUTEX(port)	_MMIO_PORT(port, _DPA_AUX_CH_MUTEX, _DPB_AUX_CH_MUTEX)
+#define   DP_AUX_CH_MUTEX_ENABLE		(1 << 31)
+#define   DP_AUX_CH_MUTEX_STATUS		(1 << 30)
+
 /*
  * Computing GMCH M and N values for the Display Port link
  *
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2c3eb90b9499..7be2fec51651 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1081,6 +1081,45 @@ static uint32_t intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
 						aux_clock_divider);
 }
 
+static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv =
+			to_i915(intel_dig_port->base.base.dev);
+	i915_reg_t ch_mutex;
+
+	if (!intel_dp->aux_ch_mutex_reg)
+		return true;
+
+	ch_mutex = intel_dp->aux_ch_mutex_reg(intel_dp);
+	I915_WRITE(ch_mutex, DP_AUX_CH_MUTEX_ENABLE);
+
+	/* Spec says that mutex is acquired when status bit is read as unset,
+	 * here waiting for 2msec or 4 tries before give up.
+	 */
+	if (intel_wait_for_register(dev_priv, ch_mutex, DP_AUX_CH_MUTEX_STATUS,
+				    0, 2)) {
+		DRM_WARN("dp_aux_ch port locked for too long");
+		return false;
+	}
+
+	return true;
+}
+
+static void intel_dp_aux_ch_unlock(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv =
+			to_i915(intel_dig_port->base.base.dev);
+
+	if (!intel_dp->aux_ch_mutex_reg)
+		return;
+
+	/* setting the status bit releases the mutex + keep mutex enabled */
+	I915_WRITE(intel_dp->aux_ch_mutex_reg(intel_dp),
+		   DP_AUX_CH_MUTEX_ENABLE | DP_AUX_CH_MUTEX_STATUS);
+}
+
 static int
 intel_dp_aux_ch(struct intel_dp *intel_dp,
 		const uint8_t *send, int send_bytes,
@@ -1119,6 +1158,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 
 	intel_dp_check_edp(intel_dp);
 
+	if (!intel_dp_aux_ch_trylock(intel_dp)) {
+		ret = -EBUSY;
+		goto out_locked;
+	}
+
 	/* Try to wait for any previous AUX channel activity */
 	for (try = 0; try < 3; try++) {
 		status = I915_READ_NOTRACE(ch_ctl);
@@ -1248,6 +1292,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 
 	ret = recv_bytes;
 out:
+	intel_dp_aux_ch_unlock(intel_dp);
+out_locked:
 	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 
 	if (vdd)
@@ -1504,6 +1550,24 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
 	}
 }
 
+static i915_reg_t skl_aux_mutex_reg(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+	enum aux_ch aux_ch = intel_dp->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_C:
+	case AUX_CH_D:
+	case AUX_CH_F:
+		return DP_AUX_CH_MUTEX(aux_ch);
+	default:
+		MISSING_CASE(aux_ch);
+		return DP_AUX_CH_MUTEX(AUX_CH_A);
+	}
+}
+
 static void
 intel_dp_aux_fini(struct intel_dp *intel_dp)
 {
@@ -1544,6 +1608,9 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
 	else
 		intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
 
+	if (INTEL_GEN(dev_priv) >= 9)
+		intel_dp->aux_ch_mutex_reg = skl_aux_mutex_reg;
+
 	drm_dp_aux_init(&intel_dp->aux);
 
 	/* Failure to allocate our preferred name is not critical */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8f38e584d375..267cc6c5a89f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1128,6 +1128,7 @@ struct intel_dp {
 
 	i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
 	i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
+	i915_reg_t (*aux_ch_mutex_reg)(struct intel_dp *dp);
 
 	/* This is called before a link training is starterd */
 	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
-- 
2.16.2

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[PATCH 2/6] drm/i915/psr: Share the common code between PSR exit and disable

[José Roberto de Souza]

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |   1 +
 drivers/gpu/drm/i915/intel_psr.c | 199 +++++++++++++++++++--------------------
 2 files changed, 96 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 82a106b1bdbc..44b551f1576d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,7 @@ struct i915_psr {
 	void (*enable_sink)(struct intel_dp *);
 	void (*activate)(struct intel_dp *);
 	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
+	void (*exit)(struct intel_dp *intel_dp, bool wait_exit);
 };
 
 enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2ef374f936b9..e8c32c3afb0e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -551,25 +551,12 @@ static void vlv_psr_disable(struct intel_dp *intel_dp,
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
 	uint32_t val;
 
-	if (dev_priv->psr.active) {
-		/* Put VLV PSR back to PSR_state 0 (disabled). */
-		if (intel_wait_for_register(dev_priv,
-					    VLV_PSRSTAT(crtc->pipe),
-					    VLV_EDP_PSR_IN_TRANS,
-					    0,
-					    1))
-			WARN(1, "PSR transition took longer than expected\n");
+	dev_priv->psr.exit(intel_dp, true);
 
-		val = I915_READ(VLV_PSRCTL(crtc->pipe));
-		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
-		val &= ~VLV_EDP_PSR_ENABLE;
-		val &= ~VLV_EDP_PSR_MODE_MASK;
-		I915_WRITE(VLV_PSRCTL(crtc->pipe), val);
-
-		dev_priv->psr.active = false;
-	} else {
-		WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe));
-	}
+	val = I915_READ(VLV_PSRCTL(crtc->pipe));
+	val &= ~VLV_EDP_PSR_ENABLE;
+	val &= ~VLV_EDP_PSR_MODE_MASK;
+	I915_WRITE(VLV_PSRCTL(crtc->pipe), val);
 }
 
 static void hsw_psr_disable(struct intel_dp *intel_dp,
@@ -579,44 +566,100 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (dev_priv->psr.active) {
-		i915_reg_t psr_status;
-		u32 psr_status_mask;
-
-		if (dev_priv->psr.aux_frame_sync)
-			drm_dp_dpcd_writeb(&intel_dp->aux,
-					DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
-					0);
+	dev_priv->psr.exit(intel_dp, true);
+}
 
-		if (dev_priv->psr.psr2_support) {
-			psr_status = EDP_PSR2_STATUS;
-			psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
+static void hsw_psr_exit(struct intel_dp *intel_dp, bool wait_exit)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	i915_reg_t psr_status;
+	u32 psr_status_mask;
 
-			I915_WRITE(EDP_PSR2_CTL,
-				   I915_READ(EDP_PSR2_CTL) &
-				   ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
+	if (!dev_priv->psr.active) {
+		if (dev_priv->psr.psr2_support)
+			WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
+		else
+			WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+		return;
+	}
 
-		} else {
-			psr_status = EDP_PSR_STATUS;
-			psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
+	if (dev_priv->psr.aux_frame_sync)
+		drm_dp_dpcd_writeb(&intel_dp->aux,
+				   DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, 0);
 
-			I915_WRITE(EDP_PSR_CTL,
-				   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
-		}
+	if (dev_priv->psr.psr2_support) {
+		psr_status = EDP_PSR2_STATUS;
+		psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
 
-		/* Wait till PSR is idle */
-		if (intel_wait_for_register(dev_priv,
-					    psr_status, psr_status_mask, 0,
-					    2000))
-			DRM_ERROR("Timed out waiting for PSR Idle State\n");
+		I915_WRITE(EDP_PSR2_CTL,
+			   I915_READ(EDP_PSR2_CTL) &
+			   ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
 
-		dev_priv->psr.active = false;
 	} else {
-		if (dev_priv->psr.psr2_support)
-			WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
-		else
-			WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+		psr_status = EDP_PSR_STATUS;
+		psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
+
+		I915_WRITE(EDP_PSR_CTL,
+			   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
+	}
+
+	/* Wait till PSR is idle */
+	if (wait_exit && intel_wait_for_register(dev_priv, psr_status,
+						 psr_status_mask, 0, 2000))
+		DRM_ERROR("Timed out waiting for PSR Idle State\n");
+
+	dev_priv->psr.active = false;
+}
+
+static void vlv_psr_exit(struct intel_dp *intel_dp, bool wait_exit)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+	uint32_t val;
+
+	if (!dev_priv->psr.active) {
+		WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe));
+		return;
 	}
+
+	if (intel_wait_for_register(dev_priv, VLV_PSRSTAT(crtc->pipe),
+				    VLV_EDP_PSR_IN_TRANS, 0, 1))
+		WARN(1, "PSR transition took longer than expected\n");
+
+	/*
+	 * Here we do the transition directly from
+	 * PSR_state 3 (active - no Remote Frame Buffer (RFB) update) to
+	 * PSR_state 5 (exit).
+	 * PSR State 4 (active with single frame update) can be skipped.
+	 * On PSR_state 5 (exit) Hardware is responsible to transition
+	 * back to PSR_state 1 (inactive).
+	 * Now we are at Same state after vlv_psr_enable_source.
+	 */
+	val = I915_READ(VLV_PSRCTL(crtc->pipe));
+	val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
+	I915_WRITE(VLV_PSRCTL(crtc->pipe), val);
+
+	/*
+	 * Send AUX wake up - Spec says after transitioning to PSR
+	 * active we have to send AUX wake up by writing 01h in DPCD
+	 * 600h of sink device.
+	 * XXX: This might slow down the transition, but without this
+	 * HW doesn't complete the transition to PSR_state 1 and we
+	 * never get the screen updated.
+	 */
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
+
+	if (wait_exit && intel_wait_for_register(dev_priv,
+						 VLV_PSRSTAT(crtc->pipe),
+						 VLV_EDP_PSR_INACTIVE,
+						 VLV_EDP_PSR_INACTIVE, 2000))
+		DRM_ERROR("Timed out waiting for PSR inactive state\n");
+
+	dev_priv->psr.active = false;
 }
 
 /**
@@ -718,60 +761,6 @@ static void intel_psr_work(struct work_struct *work)
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
-static void intel_psr_exit(struct drm_i915_private *dev_priv)
-{
-	struct intel_dp *intel_dp = dev_priv->psr.enabled;
-	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
-	u32 val;
-
-	if (!dev_priv->psr.active)
-		return;
-
-	if (HAS_DDI(dev_priv)) {
-		if (dev_priv->psr.aux_frame_sync)
-			drm_dp_dpcd_writeb(&intel_dp->aux,
-					DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
-					0);
-		if (dev_priv->psr.psr2_support) {
-			val = I915_READ(EDP_PSR2_CTL);
-			WARN_ON(!(val & EDP_PSR2_ENABLE));
-			I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
-		} else {
-			val = I915_READ(EDP_PSR_CTL);
-			WARN_ON(!(val & EDP_PSR_ENABLE));
-			I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
-		}
-	} else {
-		val = I915_READ(VLV_PSRCTL(pipe));
-
-		/*
-		 * Here we do the transition drirectly from
-		 * PSR_state 3 (active - no Remote Frame Buffer (RFB) update) to
-		 * PSR_state 5 (exit).
-		 * PSR State 4 (active with single frame update) can be skipped.
-		 * On PSR_state 5 (exit) Hardware is responsible to transition
-		 * back to PSR_state 1 (inactive).
-		 * Now we are at Same state after vlv_psr_enable_source.
-		 */
-		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
-		I915_WRITE(VLV_PSRCTL(pipe), val);
-
-		/*
-		 * Send AUX wake up - Spec says after transitioning to PSR
-		 * active we have to send AUX wake up by writing 01h in DPCD
-		 * 600h of sink device.
-		 * XXX: This might slow down the transition, but without this
-		 * HW doesn't complete the transition to PSR_state 1 and we
-		 * never get the screen updated.
-		 */
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
-				   DP_SET_POWER_D0);
-	}
-
-	dev_priv->psr.active = false;
-}
-
 /**
  * intel_psr_single_frame_update - Single Frame Update
  * @dev_priv: i915 device
@@ -854,7 +843,7 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv,
 	dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
 
 	if (frontbuffer_bits)
-		intel_psr_exit(dev_priv);
+		dev_priv->psr.exit(dev_priv->psr.enabled, false);
 
 	mutex_unlock(&dev_priv->psr.lock);
 }
@@ -895,7 +884,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 
 	/* By definition flush = invalidate + flush */
 	if (frontbuffer_bits)
-		intel_psr_exit(dev_priv);
+		dev_priv->psr.exit(dev_priv->psr.enabled, false);
 
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 		if (!work_busy(&dev_priv->psr.work.work))
@@ -956,11 +945,13 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
 		dev_priv->psr.enable_sink = vlv_psr_enable_sink;
 		dev_priv->psr.activate = vlv_psr_activate;
 		dev_priv->psr.setup_vsc = vlv_psr_setup_vsc;
+		dev_priv->psr.exit = vlv_psr_exit;
 	} else {
 		dev_priv->psr.enable_source = hsw_psr_enable_source;
 		dev_priv->psr.disable_source = hsw_psr_disable;
 		dev_priv->psr.enable_sink = hsw_psr_enable_sink;
 		dev_priv->psr.activate = hsw_psr_activate;
 		dev_priv->psr.setup_vsc = hsw_psr_setup_vsc;
+		dev_priv->psr.exit = hsw_psr_exit;
 	}
 }
-- 
2.16.2

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[PATCH 3/6] drm/i915: Exit PSR before do a aux transaction in gen < 9

[José Roberto de Souza]

As gen < 9 hardware don't have the aux ch mutex, we need to exit PSR
and wait until it is back to inactive state before do any aux ch
transaction.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  |  8 +++++++-
 drivers/gpu/drm/i915/intel_drv.h |  9 +++++++++
 drivers/gpu/drm/i915/intel_psr.c | 42 ++++++++++++++++++++++++++++++++++------
 3 files changed, 52 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7be2fec51651..dacdd98bbb2e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1088,8 +1088,14 @@ static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
 			to_i915(intel_dig_port->base.base.dev);
 	i915_reg_t ch_mutex;
 
-	if (!intel_dp->aux_ch_mutex_reg)
+	if (!intel_dp->aux_ch_mutex_reg) {
+		/* As gen < 9 hardware don't have the aux ch mutex, we need to
+		 * exit PSR and wait until it is back to inactive state before
+		 * do any aux ch transaction
+		 */
+		intel_psr_exit(intel_dp, true);
 		return true;
+	}
 
 	ch_mutex = intel_dp->aux_ch_mutex_reg(intel_dp);
 	I915_WRITE(ch_mutex, DP_AUX_CH_MUTEX_ENABLE);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 267cc6c5a89f..7adcd5955d1b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1881,6 +1881,15 @@ void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
 				   unsigned frontbuffer_bits);
 void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state);
+/**
+ * Exit PSR in the given DisplayPort.
+ * @intel_dp: DisplayPort which PSR should be exit if running
+ * @wait_exit: if true it will wait until PSR have changed to inactive state,
+ * otherwise there is not wait.
+ *
+ * It will also schedule a work to try to active PSR again.
+ */
+void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit);
 
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index e8c32c3afb0e..0b889c85e8da 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,6 +56,8 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
+#define PSR_ACTIVE_DELAY_MSEC 100
+
 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -486,6 +488,16 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
 	}
 }
 
+static void intel_psr_active_schedule(struct i915_psr *psr,
+				      unsigned int msec_delay)
+{
+	if (psr->active || psr->busy_frontbuffer_bits)
+		return;
+
+	if (!work_busy(&psr->work.work))
+		schedule_delayed_work(&psr->work, msecs_to_jiffies(msec_delay));
+}
+
 /**
  * intel_psr_enable - Enable PSR
  * @intel_dp: Intel DP
@@ -534,8 +546,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
 		 *     - On HSW/BDW we get a recoverable frozen screen until
 		 *       next exit-activate sequence.
 		 */
-		schedule_delayed_work(&dev_priv->psr.work,
-				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
+		intel_psr_active_schedule(&dev_priv->psr,
+					  intel_dp->panel_power_cycle_delay
+					  * 5);
 	}
 
 unlock:
@@ -886,10 +899,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 	if (frontbuffer_bits)
 		dev_priv->psr.exit(dev_priv->psr.enabled, false);
 
-	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
-		if (!work_busy(&dev_priv->psr.work.work))
-			schedule_delayed_work(&dev_priv->psr.work,
-					      msecs_to_jiffies(100));
+	intel_psr_active_schedule(&dev_priv->psr, PSR_ACTIVE_DELAY_MSEC);
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
@@ -955,3 +965,23 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
 		dev_priv->psr.exit = hsw_psr_exit;
 	}
 }
+
+void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	if (!HAS_PSR(dev_priv))
+		return;
+
+	mutex_lock(&dev_priv->psr.lock);
+
+	if (dev_priv->psr.enabled != intel_dp)
+		goto out;
+
+	dev_priv->psr.exit(intel_dp, wait_exit);
+	intel_psr_active_schedule(&dev_priv->psr, PSR_ACTIVE_DELAY_MSEC);
+out:
+	mutex_unlock(&dev_priv->psr.lock);
+}
-- 
2.16.2

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[PATCH 4/6] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink

[José Roberto de Souza]

Sink device will do a short pulse in HPD line when there is some
PSR/PSR2 error that needs to be handled by source, this is handling
the first and most simples error: DP_PSR_SINK_INTERNAL_ERROR.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  |  2 ++
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 31 +++++++++++++++++++++++++++++++
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dacdd98bbb2e..955bf85e9b20 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4549,6 +4549,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 
 	intel_dp_check_link_status(intel_dp);
 
+	intel_psr_hpd_short_pulse_handle(intel_dp);
+
 	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
 		DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
 		/* Send a Hotplug Uevent to userspace to start modeset */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7adcd5955d1b..a0bd00787a98 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1890,6 +1890,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
  * It will also schedule a work to try to active PSR again.
  */
 void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit);
+void intel_psr_hpd_short_pulse_handle(struct intel_dp *intel_dp);
 
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0b889c85e8da..ab3713c2582b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -985,3 +985,34 @@ void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit)
 out:
 	mutex_unlock(&dev_priv->psr.lock);
 }
+
+void intel_psr_hpd_short_pulse_handle(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct i915_psr *psr = &dev_priv->psr;
+	uint8_t val;
+
+	if (!HAS_PSR(dev_priv))
+		return;
+
+	mutex_lock(&psr->lock);
+
+	if (psr->enabled != intel_dp)
+		goto out;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
+		DRM_DEBUG_KMS("PSR_STATUS read failed\n");
+		goto dpcd_read_error;
+	}
+
+	if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR)
+		psr->exit(intel_dp, false);
+
+	/* TODO: handle other PSR/PSR2 errors */
+dpcd_read_error:
+	intel_psr_active_schedule(psr, PSR_ACTIVE_DELAY_MSEC);
+out:
+	mutex_unlock(&psr->lock);
+}
-- 
2.16.2

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[PATCH 5/6] drm/i915/psr: Handle PSR RFB storage error

[José Roberto de Souza]

Sink will interrupt source when it have any problem saving or reading
the remote frame buffer.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index ab3713c2582b..4e73edf1ea5b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1010,6 +1010,16 @@ void intel_psr_hpd_short_pulse_handle(struct intel_dp *intel_dp)
 	if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR)
 		psr->exit(intel_dp, false);
 
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
+		DRM_DEBUG_KMS("PSR_ERROR_STATUS read failed\n");
+		goto dpcd_read_error;
+	}
+
+	if (val & DP_PSR_RFB_STORAGE_ERROR)
+		dev_priv->psr.exit(intel_dp, false);
+	/* clear status register */
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
+
 	/* TODO: handle other PSR/PSR2 errors */
 dpcd_read_error:
 	intel_psr_active_schedule(psr, PSR_ACTIVE_DELAY_MSEC);
-- 
2.16.2

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[PATCH 6/6] drm/i915/psr/hsw+: Enable CRC check in the static frame on the sink side

[José Roberto de Souza]

Sink can be configured to calculate the CRC over the static frame and
compare with the CRC calculated and transmited in the VSC SDP by
source, if there is a mismatch sink will do a short pulse in HPD
and set DP_PSR_LINK_CRC_ERROR on DP_PSR_ERROR_STATUS.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 15 +++++++--------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f36e839b4b4f..ca68eef8d90a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4122,6 +4122,7 @@ enum {
 #define   EDP_PSR_SKIP_AUX_EXIT			(1<<12)
 #define   EDP_PSR_TP1_TP2_SEL			(0<<11)
 #define   EDP_PSR_TP1_TP3_SEL			(1<<11)
+#define   EDP_PSR_CRC_ENABLE			(1<<10)
 #define   EDP_PSR_TP2_TP3_TIME_500us		(0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us		(1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us		(2<<8)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4e73edf1ea5b..f6af8e8039c9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -160,6 +160,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 	enum port port = dig_port->base.port;
 	u32 aux_ctl;
 	int i;
+	uint8_t val;
 
 	BUILD_BUG_ON(sizeof(aux_msg) > 20);
 
@@ -175,12 +176,10 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 		drm_dp_dpcd_writeb(&intel_dp->aux,
 				DP_RECEIVER_ALPM_CONFIG,
 				DP_ALPM_ENABLE);
+	val = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
 	if (dev_priv->psr.link_standby)
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
-	else
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-				   DP_PSR_ENABLE);
+		val |= DP_PSR_MAIN_LINK_ACTIVE;
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
 
 	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
 
@@ -241,7 +240,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	 * with the 5 or 6 idle patterns.
 	 */
 	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-	uint32_t val = EDP_PSR_ENABLE;
+	uint32_t val = EDP_PSR_ENABLE | EDP_PSR_CRC_ENABLE;
 
 	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -1015,12 +1014,12 @@ void intel_psr_hpd_short_pulse_handle(struct intel_dp *intel_dp)
 		goto dpcd_read_error;
 	}
 
-	if (val & DP_PSR_RFB_STORAGE_ERROR)
+	if (val & (DP_PSR_RFB_STORAGE_ERROR | DP_PSR_LINK_CRC_ERROR))
 		dev_priv->psr.exit(intel_dp, false);
 	/* clear status register */
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
 
-	/* TODO: handle other PSR/PSR2 errors */
+	/* TODO: handle PSR2 errors */
 dpcd_read_error:
 	intel_psr_active_schedule(psr, PSR_ACTIVE_DELAY_MSEC);
 out:
-- 
2.16.2

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✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915/skl+: Add and enable DP AUX CH mutex

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/skl+: Add and enable DP AUX CH mutex
URL   : https://patchwork.freedesktop.org/series/38902/
State : failure

== Summary ==

Series 38902v1 series starting with [1/6] drm/i915/skl+: Add and enable DP AUX CH mutex
https://patchwork.freedesktop.org/api/1.0/series/38902/revisions/1/mbox/

Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> FAIL       (fi-skl-guc)
Test kms_busy:
        Subgroup basic-flip-a:
                pass       -> DMESG-WARN (fi-skl-6700k2)
Test kms_force_connector_basic:
        Subgroup force-connector-state:
                skip       -> PASS       (fi-snb-2520m)
        Subgroup force-edid:
                skip       -> PASS       (fi-snb-2520m)
        Subgroup force-load-detect:
                skip       -> PASS       (fi-snb-2520m)
        Subgroup prune-stale-modes:
                skip       -> PASS       (fi-snb-2520m)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                incomplete -> PASS       (fi-bxt-dsi) fdo#103927

fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:406s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:423s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:373s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:440s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:283s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:476s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:485s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:424s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:417s
fi-cfl-8700k     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:393s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:565s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:576s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:419s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:283s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:508s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:384s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:407s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:452s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:412s
fi-kbl-7500u     total:288  pass:262  dwarn:1   dfail:0   fail:1   skip:24  time:439s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:491s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:444s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:494s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:591s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:428s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:502s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:517s
fi-skl-6700k2    total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:478s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:458s
fi-skl-guc       total:288  pass:259  dwarn:0   dfail:0   fail:1   skip:28  time:404s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:430s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:523s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:392s

316ba650abe6c1e8ac2f812ff21eee5771546ba1 drm-tip: 2018y-02m-23d-16h-41m-52s UTC integration manifest
ef1e257d5daa drm/i915/psr/hsw+: Enable CRC check in the static frame on the sink side
5c88fa2403cd drm/i915/psr: Handle PSR RFB storage error
44e795fcba6e drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink
7ff88cb1e65b drm/i915: Exit PSR before do a aux transaction in gen < 9
c796fc99157a drm/i915/psr: Share the common code between PSR exit and disable
daa39e989d5f drm/i915/skl+: Add and enable DP AUX CH mutex

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8152/issues.html
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Re: [PATCH 3/6] drm/i915: Exit PSR before do a aux transaction in gen < 9

[Pandiyan, Dhinakaran]

On Fri, 2018-02-23 at 18:03 -0800, José Roberto de Souza wrote:
> As gen < 9 hardware don't have the aux ch mutex, we need to exit PSR
> and wait until it is back to inactive state before do any aux ch
> transaction.
> 

I wonder if we need this for CHV/VLV since the HW does not send PSR aux
transactions on it's own.

> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  |  8 +++++++-
>  drivers/gpu/drm/i915/intel_drv.h |  9 +++++++++
>  drivers/gpu/drm/i915/intel_psr.c | 42 ++++++++++++++++++++++++++++++++++------
>  3 files changed, 52 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7be2fec51651..dacdd98bbb2e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1088,8 +1088,14 @@ static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
>  			to_i915(intel_dig_port->base.base.dev);
>  	i915_reg_t ch_mutex;
>  
> -	if (!intel_dp->aux_ch_mutex_reg)
> +	if (!intel_dp->aux_ch_mutex_reg) {
> +		/* As gen < 9 hardware don't have the aux ch mutex, we need to
> +		 * exit PSR and wait until it is back to inactive state before
> +		 * do any aux ch transaction
> +		 */
> +		intel_psr_exit(intel_dp, true);
>  		return true;
> +	}
>  
>  	ch_mutex = intel_dp->aux_ch_mutex_reg(intel_dp);
>  	I915_WRITE(ch_mutex, DP_AUX_CH_MUTEX_ENABLE);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 267cc6c5a89f..7adcd5955d1b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1881,6 +1881,15 @@ void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
>  				   unsigned frontbuffer_bits);
>  void intel_psr_compute_config(struct intel_dp *intel_dp,
>  			      struct intel_crtc_state *crtc_state);
> +/**
> + * Exit PSR in the given DisplayPort.
> + * @intel_dp: DisplayPort which PSR should be exit if running
> + * @wait_exit: if true it will wait until PSR have changed to inactive state,
> + * otherwise there is not wait.
> + *
> + * It will also schedule a work to try to active PSR again.
> + */
> +void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit);
>  
>  /* intel_runtime_pm.c */
>  int intel_power_domains_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index e8c32c3afb0e..0b889c85e8da 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -56,6 +56,8 @@
>  #include "intel_drv.h"
>  #include "i915_drv.h"
>  
> +#define PSR_ACTIVE_DELAY_MSEC 100
> +
>  static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -486,6 +488,16 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
>  	}
>  }
>  
> +static void intel_psr_active_schedule(struct i915_psr *psr,
> +				      unsigned int msec_delay)
> +{
> +	if (psr->active || psr->busy_frontbuffer_bits)
> +		return;
> +
> +	if (!work_busy(&psr->work.work))
> +		schedule_delayed_work(&psr->work, msecs_to_jiffies(msec_delay));

This change will conflict with
https://patchwork.freedesktop.org/series/38199/


> +}
> +
>  /**
>   * intel_psr_enable - Enable PSR
>   * @intel_dp: Intel DP
> @@ -534,8 +546,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>  		 *     - On HSW/BDW we get a recoverable frozen screen until
>  		 *       next exit-activate sequence.
>  		 */
> -		schedule_delayed_work(&dev_priv->psr.work,
> -				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
> +		intel_psr_active_schedule(&dev_priv->psr,
> +					  intel_dp->panel_power_cycle_delay
> +					  * 5);
>  	}
>  
>  unlock:
> @@ -886,10 +899,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>  	if (frontbuffer_bits)
>  		dev_priv->psr.exit(dev_priv->psr.enabled, false);
>  
> -	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
> -		if (!work_busy(&dev_priv->psr.work.work))
> -			schedule_delayed_work(&dev_priv->psr.work,
> -					      msecs_to_jiffies(100));
> +	intel_psr_active_schedule(&dev_priv->psr, PSR_ACTIVE_DELAY_MSEC);
>  	mutex_unlock(&dev_priv->psr.lock);
>  }
>  
> @@ -955,3 +965,23 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
>  		dev_priv->psr.exit = hsw_psr_exit;
>  	}
>  }
> +
> +void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = intel_dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +
> +	if (!HAS_PSR(dev_priv))
> +		return;
> +
> +	mutex_lock(&dev_priv->psr.lock);
> +
> +	if (dev_priv->psr.enabled != intel_dp)
> +		goto out;
> +
> +	dev_priv->psr.exit(intel_dp, wait_exit);
> +	intel_psr_active_schedule(&dev_priv->psr, PSR_ACTIVE_DELAY_MSEC);

psr_exit scheduling an activate looks wrong and it is also exactly what
psr_flush does.

I suppose we could call psr_invalidate at the beginning of the aux
transaction and psr_flush at the end. But the question is what arguments
do we pass to those functions.

Or we could just call psr_exit at the start (without scheduling
activate) and psr_activate at the end.


> +out:
> +	mutex_unlock(&dev_priv->psr.lock);
> +}
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