[PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Eric Anholt]

We have always been using the wrong bit -- it's bit 12.  However, the
bit also doesn't do anything -- hardware has always accepted the
MI_FLUSH command even when it was specced not to.

Given that there is only one MI_FLUSH emitted in all of the driver
stack on gen6+ (in i965_video.c of the 2d driver, and it should be
using other code to do its flush instead), just remove the MI_FLUSH
enable instead of trying to fix it.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2df35e3..d21346b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -389,8 +389,6 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 
 	if (INTEL_INFO(dev)->gen > 3) {
 		int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
-		if (IS_GEN6(dev) || IS_GEN7(dev))
-			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 		I915_WRITE(MI_MODE, mode);
 		if (IS_GEN7(dev))
 			I915_WRITE(GFX_MODE_GEN7,
-- 
1.7.7.3

[PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.

[Eric Anholt]

Older specs claimed this was bit 11, but newer specs and the actual
simulator code say it was bit 12.  Regardless, we don't use MI_FLUSH,
or try to enable it any more.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_reg.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3afb78..bbad788 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -391,7 +391,7 @@
 
 #define MI_MODE		0x0209c
 # define VS_TIMER_DISPATCH				(1 << 6)
-# define MI_FLUSH_ENABLE				(1 << 11)
+# define MI_FLUSH_ENABLE				(1 << 12)
 
 #define GFX_MODE	0x02520
 #define GFX_MODE_GEN7	0x0229c
-- 
1.7.7.3

Re: [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.

[Daniel Vetter]

On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote:
> Older specs claimed this was bit 11, but newer specs and the actual
> simulator code say it was bit 12.  Regardless, we don't use MI_FLUSH,
> or try to enable it any more.
> 
> Signed-off-by: Eric Anholt <eric@anholt.net>

I'd like to amend this with the following (on this patch instead of the
other, so that ppl actually can find it with git blame):

"Furthermore actually setting bit12 results in gpu hangs both on snb and
ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bit11
must be set, but that doesn't help either. And last but not least,
MI_FLUSH seems to work regardless of the setting of these bits."

Eric, Ben, is that ok?
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.

[Eric Anholt]

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On Sat, 21 Jan 2012 17:36:13 +0100, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote:
> > Older specs claimed this was bit 11, but newer specs and the actual
> > simulator code say it was bit 12.  Regardless, we don't use MI_FLUSH,
> > or try to enable it any more.
> > 
> > Signed-off-by: Eric Anholt <eric@anholt.net>
> 
> I'd like to amend this with the following (on this patch instead of the
> other, so that ppl actually can find it with git blame):
> 
> "Furthermore actually setting bit12 results in gpu hangs both on snb and
> ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bit11
> must be set, but that doesn't help either. And last but not least,
> MI_FLUSH seems to work regardless of the setting of these bits."

I haven't seen bit12 hanging snb/ivb -- I only knew of it hanging ilk
(since it doesn't exist there).  On my snb, running xvideo so that
MI_FLUSHes are generated by the userland (I think -- I haven't caught
them in cat i915_batchbuffers | intel_dump_decode -), with
intel_reg_read 0x209c saying 0x1240, things are going fine.  Also with
0x209c saying 0x240 (the result of this patch).

That 2008 PPT mentioned also said "the bit" and "bit 12", and only in
one cut-and-paste of a command line did I see it say two bits should be
set.  I would trust the actual code more than a ppt.

But basically, whatever we do to make this broken code go away, I'm fine
with.

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Re: [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.

[Ben Widawsky]

On 01/24/12 18:55, Eric Anholt wrote:
> On Sat, 21 Jan 2012 17:36:13 +0100, Daniel Vetter<daniel@ffwll.ch>  wrote:
>> On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote:
>>> Older specs claimed this was bit 11, but newer specs and the actual
>>> simulator code say it was bit 12.  Regardless, we don't use MI_FLUSH,
>>> or try to enable it any more.
>>>
>>> Signed-off-by: Eric Anholt<eric@anholt.net>
>>
>> I'd like to amend this with the following (on this patch instead of the
>> other, so that ppl actually can find it with git blame):
>>
>> "Furthermore actually setting bit12 results in gpu hangs both on snb and
>> ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bit11
>> must be set, but that doesn't help either. And last but not least,
>> MI_FLUSH seems to work regardless of the setting of these bits."
>
> I haven't seen bit12 hanging snb/ivb -- I only knew of it hanging ilk
> (since it doesn't exist there).  On my snb, running xvideo so that
> MI_FLUSHes are generated by the userland (I think -- I haven't caught
> them in cat i915_batchbuffers | intel_dump_decode -), with
> intel_reg_read 0x209c saying 0x1240, things are going fine.  Also with
> 0x209c saying 0x240 (the result of this patch).

Daniel has a failing test on IVB. I haven't tried hard enough to make it 
fail on SNB, so I cannot speak to that.

>
> That 2008 PPT mentioned also said "the bit" and "bit 12", and only in
> one cut-and-paste of a command line did I see it say two bits should be
> set.  I would trust the actual code more than a ppt.
>
> But basically, whatever we do to make this broken code go away, I'm fine
> with.

I'm in the same boat. I think trying to figure out which source to trust 
is a losing game for all, and our best bet is to find out what the 
Windows driver does, and presumably that cut-and-paste is not from the 
Windows driver.

Ben

Re: [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.

[Daniel Vetter]

On Tue, Jan 24, 2012 at 08:22:57PM -0800, Ben Widawsky wrote:
> On 01/24/12 18:55, Eric Anholt wrote:
> >On Sat, 21 Jan 2012 17:36:13 +0100, Daniel Vetter<daniel@ffwll.ch>  wrote:
> >>On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote:
> >>>Older specs claimed this was bit 11, but newer specs and the actual
> >>>simulator code say it was bit 12.  Regardless, we don't use MI_FLUSH,
> >>>or try to enable it any more.
> >>>
> >>>Signed-off-by: Eric Anholt<eric@anholt.net>
> >>
> >>I'd like to amend this with the following (on this patch instead of the
> >>other, so that ppl actually can find it with git blame):
> >>
> >>"Furthermore actually setting bit12 results in gpu hangs both on snb and
> >>ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bit11
> >>must be set, but that doesn't help either. And last but not least,
> >>MI_FLUSH seems to work regardless of the setting of these bits."
> >
> >I haven't seen bit12 hanging snb/ivb -- I only knew of it hanging ilk
> >(since it doesn't exist there).  On my snb, running xvideo so that
> >MI_FLUSHes are generated by the userland (I think -- I haven't caught
> >them in cat i915_batchbuffers | intel_dump_decode -), with
> >intel_reg_read 0x209c saying 0x1240, things are going fine.  Also with
> >0x209c saying 0x240 (the result of this patch).
> 
> Daniel has a failing test on IVB. I haven't tried hard enough to
> make it fail on SNB, so I cannot speak to that.

Could be some other crash and I've just had an unlucky day and it died
much earlier than usual. Anyway, with things tested I'm happy with these 2
patches and queued them for -next.

> >That 2008 PPT mentioned also said "the bit" and "bit 12", and only in
> >one cut-and-paste of a command line did I see it say two bits should be
> >set.  I would trust the actual code more than a ppt.
> >
> >But basically, whatever we do to make this broken code go away, I'm fine
> >with.
> 
> I'm in the same boat. I think trying to figure out which source to
> trust is a losing game for all, and our best bet is to find out what
> the Windows driver does, and presumably that cut-and-paste is not
> from the Windows driver.

I've added a small comment to patch 2 to urge people to get a clue before
trying to use this bit ;-)

Thanks, Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.

[Chris Wilson]

On Tue, 24 Jan 2012 18:55:53 -0800, Eric Anholt <eric@anholt.net> wrote:
> On Sat, 21 Jan 2012 17:36:13 +0100, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote:
> > > Older specs claimed this was bit 11, but newer specs and the actual
> > > simulator code say it was bit 12.  Regardless, we don't use MI_FLUSH,
> > > or try to enable it any more.
> > > 
> > > Signed-off-by: Eric Anholt <eric@anholt.net>
> > 
> > I'd like to amend this with the following (on this patch instead of the
> > other, so that ppl actually can find it with git blame):
> > 
> > "Furthermore actually setting bit12 results in gpu hangs both on snb and
> > ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bit11
> > must be set, but that doesn't help either. And last but not least,
> > MI_FLUSH seems to work regardless of the setting of these bits."
> 
> I haven't seen bit12 hanging snb/ivb -- I only knew of it hanging ilk
> (since it doesn't exist there).  On my snb, running xvideo so that
> MI_FLUSHes are generated by the userland (I think -- I haven't caught
> them in cat i915_batchbuffers | intel_dump_decode -), with
> intel_reg_read 0x209c saying 0x1240, things are going fine.  Also with
> 0x209c saying 0x240 (the result of this patch).

The SNB Xv path, that is the code called by Gen6DisplayVideoTexture, 
never used MI_FLUSH.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.

[Daniel Vetter]

On Wed, Jan 25, 2012 at 09:57:58AM +0000, Chris Wilson wrote:
> On Tue, 24 Jan 2012 18:55:53 -0800, Eric Anholt <eric@anholt.net> wrote:
> > On Sat, 21 Jan 2012 17:36:13 +0100, Daniel Vetter <daniel@ffwll.ch> wrote:
> > > On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote:
> > > > Older specs claimed this was bit 11, but newer specs and the actual
> > > > simulator code say it was bit 12.  Regardless, we don't use MI_FLUSH,
> > > > or try to enable it any more.
> > > > 
> > > > Signed-off-by: Eric Anholt <eric@anholt.net>
> > > 
> > > I'd like to amend this with the following (on this patch instead of the
> > > other, so that ppl actually can find it with git blame):
> > > 
> > > "Furthermore actually setting bit12 results in gpu hangs both on snb and
> > > ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bit11
> > > must be set, but that doesn't help either. And last but not least,
> > > MI_FLUSH seems to work regardless of the setting of these bits."
> > 
> > I haven't seen bit12 hanging snb/ivb -- I only knew of it hanging ilk
> > (since it doesn't exist there).  On my snb, running xvideo so that
> > MI_FLUSHes are generated by the userland (I think -- I haven't caught
> > them in cat i915_batchbuffers | intel_dump_decode -), with
> > intel_reg_read 0x209c saying 0x1240, things are going fine.  Also with
> > 0x209c saying 0x240 (the result of this patch).
> 
> The SNB Xv path, that is the code called by Gen6DisplayVideoTexture, 
> never used MI_FLUSH.

Ok, I've quickly tested this with intel_reg_write and installing older
userspace. Doesn't seem to blow up.
-Daniel
-- 
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Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.

[Eric Anholt]

[-- Attachment #1.1: Type: text/plain, Size: 1653 bytes --]

On Wed, 25 Jan 2012 09:57:58 +0000, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Tue, 24 Jan 2012 18:55:53 -0800, Eric Anholt <eric@anholt.net> wrote:
> > On Sat, 21 Jan 2012 17:36:13 +0100, Daniel Vetter <daniel@ffwll.ch> wrote:
> > > On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote:
> > > > Older specs claimed this was bit 11, but newer specs and the actual
> > > > simulator code say it was bit 12.  Regardless, we don't use MI_FLUSH,
> > > > or try to enable it any more.
> > > > 
> > > > Signed-off-by: Eric Anholt <eric@anholt.net>
> > > 
> > > I'd like to amend this with the following (on this patch instead of the
> > > other, so that ppl actually can find it with git blame):
> > > 
> > > "Furthermore actually setting bit12 results in gpu hangs both on snb and
> > > ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bit11
> > > must be set, but that doesn't help either. And last but not least,
> > > MI_FLUSH seems to work regardless of the setting of these bits."
> > 
> > I haven't seen bit12 hanging snb/ivb -- I only knew of it hanging ilk
> > (since it doesn't exist there).  On my snb, running xvideo so that
> > MI_FLUSHes are generated by the userland (I think -- I haven't caught
> > them in cat i915_batchbuffers | intel_dump_decode -), with
> > intel_reg_read 0x209c saying 0x1240, things are going fine.  Also with
> > 0x209c saying 0x240 (the result of this patch).
> 
> The SNB Xv path, that is the code called by Gen6DisplayVideoTexture, 
> never used MI_FLUSH.

Oops.  Not sure why I remembered confirming that that code still
MI_FLUSHed on newer chipsets.

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Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Daniel Vetter]

On Thu, Jan 19, 2012 at 10:50:05AM -0800, Eric Anholt wrote:
> We have always been using the wrong bit -- it's bit 12.  However, the
> bit also doesn't do anything -- hardware has always accepted the
> MI_FLUSH command even when it was specced not to.
> 
> Given that there is only one MI_FLUSH emitted in all of the driver
> stack on gen6+ (in i965_video.c of the 2d driver, and it should be
> using other code to do its flush instead), just remove the MI_FLUSH
> enable instead of trying to fix it.
> 
> Signed-off-by: Eric Anholt <eric@anholt.net>

The other thing is that I've just tested the bit11 | bit12 patch from Ben
on my ivb, and it resulted in a nice system death, like setting bit12 on
snb. So whoever wrote that piece of bspec didn't talk with whomever
implemented it ...

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Keith Packard]

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On Thu, 19 Jan 2012 10:50:05 -0800, Eric Anholt <eric@anholt.net> wrote:

> -		if (IS_GEN6(dev) || IS_GEN7(dev))
> -			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;

This seems better than setting random bits that don't do anything but
annoy the simulator.

-- 
keith.packard@intel.com

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Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Ben Widawsky]

On 01/19/2012 10:54 AM, Keith Packard wrote:
> On Thu, 19 Jan 2012 10:50:05 -0800, Eric Anholt <eric@anholt.net> wrote:
> 
>> -		if (IS_GEN6(dev) || IS_GEN7(dev))
>> -			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
> 
> This seems better than setting random bits that don't do anything but
> annoy the simulator.

The simulator complains unless both bits are set iirc. I can double
check, but it's been a while since I've run without my patch.

Ben

Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Keith Packard]

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On Thu, 19 Jan 2012 10:59:57 -0800, Ben Widawsky <ben@bwidawsk.net> wrote:

> The simulator complains unless both bits are set iirc. I can double
> check, but it's been a while since I've run without my patch.

Oh, I thought it complained if one of the two was set. Sigh.

-- 
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Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Eric Anholt]

[-- Attachment #1.1: Type: text/plain, Size: 745 bytes --]

On Thu, 19 Jan 2012 10:59:57 -0800, Ben Widawsky <ben@bwidawsk.net> wrote:
> On 01/19/2012 10:54 AM, Keith Packard wrote:
> > On Thu, 19 Jan 2012 10:50:05 -0800, Eric Anholt <eric@anholt.net> wrote:
> > 
> >> -		if (IS_GEN6(dev) || IS_GEN7(dev))
> >> -			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
> > 
> > This seems better than setting random bits that don't do anything but
> > annoy the simulator.
> 
> The simulator complains unless both bits are set iirc. I can double
> check, but it's been a while since I've run without my patch.

Can you please cite the message you're getting?  I've read a lot of the
simulator at this point, particularly pieces relating to flushing, and I
can't find what you're talking about.

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Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Ben Widawsky]

On 01/20/2012 11:16 AM, Eric Anholt wrote:
> On Thu, 19 Jan 2012 10:59:57 -0800, Ben Widawsky <ben@bwidawsk.net> wrote:
>> On 01/19/2012 10:54 AM, Keith Packard wrote:
>>> On Thu, 19 Jan 2012 10:50:05 -0800, Eric Anholt <eric@anholt.net> wrote:
>>>
>>>> -		if (IS_GEN6(dev) || IS_GEN7(dev))
>>>> -			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
>>>
>>> This seems better than setting random bits that don't do anything but
>>> annoy the simulator.
>>
>> The simulator complains unless both bits are set iirc. I can double
>> check, but it's been a while since I've run without my patch.
> 
> Can you please cite the message you're getting?  I've read a lot of the
> simulator at this point, particularly pieces relating to flushing, and I
> can't find what you're talking about.
> 

It is not email friendly paste.

Gen7GT/Render/src/CsMiCommonCatcher.cpp +293

It links to a power point which shows the workaround is to set both
bits. The powerpoint is kind enough to crash libreoffice for me.

Ben

Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Eric Anholt]

[-- Attachment #1.1: Type: text/plain, Size: 1213 bytes --]

On Fri, 20 Jan 2012 14:57:44 -0800, Ben Widawsky <ben@bwidawsk.net> wrote:
> On 01/20/2012 11:16 AM, Eric Anholt wrote:
> > On Thu, 19 Jan 2012 10:59:57 -0800, Ben Widawsky <ben@bwidawsk.net> wrote:
> >> On 01/19/2012 10:54 AM, Keith Packard wrote:
> >>> On Thu, 19 Jan 2012 10:50:05 -0800, Eric Anholt <eric@anholt.net> wrote:
> >>>
> >>>> -		if (IS_GEN6(dev) || IS_GEN7(dev))
> >>>> -			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
> >>>
> >>> This seems better than setting random bits that don't do anything but
> >>> annoy the simulator.
> >>
> >> The simulator complains unless both bits are set iirc. I can double
> >> check, but it's been a while since I've run without my patch.
> > 
> > Can you please cite the message you're getting?  I've read a lot of the
> > simulator at this point, particularly pieces relating to flushing, and I
> > can't find what you're talking about.
> > 
> 
> It is not email friendly paste.
> 
> Gen7GT/Render/src/CsMiCommonCatcher.cpp +293
> 
> It links to a power point which shows the workaround is to set both
> bits. The powerpoint is kind enough to crash libreoffice for me.

That block is checking exactly one bit, bit 12, in my tree.

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Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Ben Widawsky]

On 01/20/2012 04:40 PM, Eric Anholt wrote:
> On Fri, 20 Jan 2012 14:57:44 -0800, Ben Widawsky <ben@bwidawsk.net> wrote:
>> On 01/20/2012 11:16 AM, Eric Anholt wrote:
>>> On Thu, 19 Jan 2012 10:59:57 -0800, Ben Widawsky <ben@bwidawsk.net> wrote:
>>>> On 01/19/2012 10:54 AM, Keith Packard wrote:
>>>>> On Thu, 19 Jan 2012 10:50:05 -0800, Eric Anholt <eric@anholt.net> wrote:
>>>>>
>>>>>> -		if (IS_GEN6(dev) || IS_GEN7(dev))
>>>>>> -			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
>>>>>
>>>>> This seems better than setting random bits that don't do anything but
>>>>> annoy the simulator.
>>>>
>>>> The simulator complains unless both bits are set iirc. I can double
>>>> check, but it's been a while since I've run without my patch.
>>>
>>> Can you please cite the message you're getting?  I've read a lot of the
>>> simulator at this point, particularly pieces relating to flushing, and I
>>> can't find what you're talking about.
>>>
>>
>> It is not email friendly paste.
>>
>> Gen7GT/Render/src/CsMiCommonCatcher.cpp +293
>>
>> It links to a power point which shows the workaround is to set both
>> bits. The powerpoint is kind enough to crash libreoffice for me.
> 
> That block is checking exactly one bit, bit 12, in my tree.

Hmm, it appears I had some PEBPAC (phone and chair). I sent two earlier
emails, and the semi-useful one never seemed to make it. Well this gives
me a chance to elaborate anyway.

You have to read the powerpoint. In there it says to set both bits. It
looks like I was incorrect about the simulator itself caring, that
indeed only checks for bit 12. I think it's all moot anyway, as it
appears bit 12 (with or without bit 11) doesn't play nice with IVB.

To sum up there are three options
Bit 11, wrong in docs, wrong in simulator, wrong in ppt; doesn't hang
Bit 12, right in docs, right in simulator, wrong in ppt; hangs (I think)
Bit 11|12, sorta wrong/right in docs an simulator, right in ppt; hangs

And I honestly don't care which we go with if the simulator logs don't
tell me everytime that bit 12 wasn't set.

~Ben

Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Kenneth Graunke]

On 01/19/2012 10:50 AM, Eric Anholt wrote:
> We have always been using the wrong bit -- it's bit 12.  However, the
> bit also doesn't do anything -- hardware has always accepted the
> MI_FLUSH command even when it was specced not to.
>
> Given that there is only one MI_FLUSH emitted in all of the driver
> stack on gen6+ (in i965_video.c of the 2d driver, and it should be
> using other code to do its flush instead), just remove the MI_FLUSH
> enable instead of trying to fix it.
>
> Signed-off-by: Eric Anholt<eric@anholt.net>
> ---
>   drivers/gpu/drm/i915/intel_ringbuffer.c |    2 --
>   1 files changed, 0 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2df35e3..d21346b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -389,8 +389,6 @@ static int init_render_ring(struct intel_ring_buffer *ring)
>
>   	if (INTEL_INFO(dev)->gen>  3) {
>   		int mode = VS_TIMER_DISPATCH<<  16 | VS_TIMER_DISPATCH;
> -		if (IS_GEN6(dev) || IS_GEN7(dev))
> -			mode |= MI_FLUSH_ENABLE<<  16 | MI_FLUSH_ENABLE;
>   		I915_WRITE(MI_MODE, mode);
>   		if (IS_GEN7(dev))
>   			I915_WRITE(GFX_MODE_GEN7,

Everything using MI_FLUSH on SNB+ ought to be converted to PIPE_CONTROL. 
  It sounds like everything except i965_video is there already.  There's 
still the issue of old userspace, but...given that we were setting the 
wrong bit and _not_ setting the actual MI_FLUSH enable bit...it seems 
like this patch shouldn't break things.

I'm all in favor of removing this code, as it's definitely a lie.

For both patches:
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting.

[Ben Widawsky]

On 01/19/2012 10:50 AM, Eric Anholt wrote:
> We have always been using the wrong bit -- it's bit 12.  However, the
> bit also doesn't do anything -- hardware has always accepted the
> MI_FLUSH command even when it was specced not to.
> 
> Given that there is only one MI_FLUSH emitted in all of the driver
> stack on gen6+ (in i965_video.c of the 2d driver, and it should be
> using other code to do its flush instead), just remove the MI_FLUSH
> enable instead of trying to fix it.
> 
> Signed-off-by: Eric Anholt <eric@anholt.net>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c |    2 --
>  1 files changed, 0 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2df35e3..d21346b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -389,8 +389,6 @@ static int init_render_ring(struct intel_ring_buffer *ring)
>  
>  	if (INTEL_INFO(dev)->gen > 3) {
>  		int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
> -		if (IS_GEN6(dev) || IS_GEN7(dev))
> -			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
>  		I915_WRITE(MI_MODE, mode);
>  		if (IS_GEN7(dev))
>  			I915_WRITE(GFX_MODE_GEN7,

I'd like to see a tested-by on this with old userspace before pulling
this in. IFF someone does that, r-b me.

Patch 2/2 I still have some gripe with as detailed in that thread.

~Ben