* [PATCH 0/3] drm/i915: Fix BDW sprite colors and a few cleanups
@ 2014-03-05 11:05 ville.syrjala
2014-03-05 11:05 ` [PATCH 1/3] drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW ville.syrjala
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: ville.syrjala @ 2014-03-05 11:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
This series fixes the "colors are wrong with YCbCr sprites" bug on
BDW, and avoids some other bugs that would happend when someone
enables FBC on BDW.
Ville Syrjälä (3):
drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW
drm/i915: Use RMW to update chicken bits in gen7_enable_fbc()
drm/i915: Unify CHICKEN_PIPESL_1 register definitions
drivers/gpu/drm/i915/i915_reg.h | 10 ++--------
drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
2 files changed, 11 insertions(+), 14 deletions(-)
--
1.8.3.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW 2014-03-05 11:05 [PATCH 0/3] drm/i915: Fix BDW sprite colors and a few cleanups ville.syrjala @ 2014-03-05 11:05 ` ville.syrjala 2014-03-05 12:09 ` Damien Lespiau 2014-03-05 11:05 ` [PATCH 2/3] drm/i915: Use RMW to update chicken bits in gen7_enable_fbc() ville.syrjala 2014-03-05 11:05 ` [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions ville.syrjala 2 siblings, 1 reply; 9+ messages in thread From: ville.syrjala @ 2014-03-05 11:05 UTC (permalink / raw) To: intel-gfx; +Cc: stable From: Ville Syrjälä <ville.syrjala@linux.intel.com> Misplaced parens cause us to totally clobber the CHICKEN_PIPESL_1 registers with 0xffffffff. Move the parens to the correct place to avoid this. In particular this caused bit 30 of said registers to be set, which caused the sprite CSC to produce incorrect results. Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72220 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6436b70..245d3ae 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4832,8 +4832,8 @@ static void gen8_init_clock_gating(struct drm_device *dev) /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ for_each_pipe(i) { I915_WRITE(CHICKEN_PIPESL_1(i), - I915_READ(CHICKEN_PIPESL_1(i) | - DPRS_MASK_VBLANK_SRD)); + I915_READ(CHICKEN_PIPESL_1(i)) | + DPRS_MASK_VBLANK_SRD); } /* Use Force Non-Coherent whenever executing a 3D context. This is a -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW 2014-03-05 11:05 ` [PATCH 1/3] drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW ville.syrjala @ 2014-03-05 12:09 ` Damien Lespiau 0 siblings, 0 replies; 9+ messages in thread From: Damien Lespiau @ 2014-03-05 12:09 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx, stable On Wed, Mar 05, 2014 at 01:05:45PM +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Misplaced parens cause us to totally clobber the CHICKEN_PIPESL_1 > registers with 0xffffffff. Move the parens to the correct place > to avoid this. > > In particular this caused bit 30 of said registers to be set, which > caused the sprite CSC to produce incorrect results. > > Cc: stable@vger.kernel.org > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72220 > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> -- Damien > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 6436b70..245d3ae 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4832,8 +4832,8 @@ static void gen8_init_clock_gating(struct drm_device *dev) > /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ > for_each_pipe(i) { > I915_WRITE(CHICKEN_PIPESL_1(i), > - I915_READ(CHICKEN_PIPESL_1(i) | > - DPRS_MASK_VBLANK_SRD)); > + I915_READ(CHICKEN_PIPESL_1(i)) | > + DPRS_MASK_VBLANK_SRD); > } > > /* Use Force Non-Coherent whenever executing a 3D context. This is a > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] drm/i915: Use RMW to update chicken bits in gen7_enable_fbc() 2014-03-05 11:05 [PATCH 0/3] drm/i915: Fix BDW sprite colors and a few cleanups ville.syrjala 2014-03-05 11:05 ` [PATCH 1/3] drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW ville.syrjala @ 2014-03-05 11:05 ` ville.syrjala 2014-03-05 14:31 ` Damien Lespiau 2014-03-21 18:52 ` Ben Widawsky 2014-03-05 11:05 ` [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions ville.syrjala 2 siblings, 2 replies; 9+ messages in thread From: ville.syrjala @ 2014-03-05 11:05 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> gen7_enable_fbc() may write to some registers which we've already touched, so use RMW so that we don't undo any previous updates. Also note that we implemnt WaFbcAsynchFlipDisableFbcQueue:bdw. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 245d3ae..3411ad7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -294,10 +294,13 @@ static void gen7_enable_fbc(struct drm_crtc *crtc) if (IS_IVYBRIDGE(dev)) { /* WaFbcAsynchFlipDisableFbcQueue:ivb */ - I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); + I915_WRITE(ILK_DISPLAY_CHICKEN1, + I915_READ(ILK_DISPLAY_CHICKEN1) | + ILK_FBCQ_DIS); } else { - /* WaFbcAsynchFlipDisableFbcQueue:hsw */ + /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), + I915_READ(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe)) | HSW_BYPASS_FBC_QUEUE); } -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] drm/i915: Use RMW to update chicken bits in gen7_enable_fbc() 2014-03-05 11:05 ` [PATCH 2/3] drm/i915: Use RMW to update chicken bits in gen7_enable_fbc() ville.syrjala @ 2014-03-05 14:31 ` Damien Lespiau 2014-03-21 18:52 ` Ben Widawsky 1 sibling, 0 replies; 9+ messages in thread From: Damien Lespiau @ 2014-03-05 14:31 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Wed, Mar 05, 2014 at 01:05:46PM +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > gen7_enable_fbc() may write to some registers which we've already > touched, so use RMW so that we don't undo any previous updates. > > Also note that we implemnt WaFbcAsynchFlipDisableFbcQueue:bdw. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> -- Damien > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 245d3ae..3411ad7 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -294,10 +294,13 @@ static void gen7_enable_fbc(struct drm_crtc *crtc) > > if (IS_IVYBRIDGE(dev)) { > /* WaFbcAsynchFlipDisableFbcQueue:ivb */ > - I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); > + I915_WRITE(ILK_DISPLAY_CHICKEN1, > + I915_READ(ILK_DISPLAY_CHICKEN1) | > + ILK_FBCQ_DIS); > } else { > - /* WaFbcAsynchFlipDisableFbcQueue:hsw */ > + /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ > I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), > + I915_READ(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe)) | > HSW_BYPASS_FBC_QUEUE); > } > > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] drm/i915: Use RMW to update chicken bits in gen7_enable_fbc() 2014-03-05 11:05 ` [PATCH 2/3] drm/i915: Use RMW to update chicken bits in gen7_enable_fbc() ville.syrjala 2014-03-05 14:31 ` Damien Lespiau @ 2014-03-21 18:52 ` Ben Widawsky 1 sibling, 0 replies; 9+ messages in thread From: Ben Widawsky @ 2014-03-21 18:52 UTC (permalink / raw) To: ville.syrjala, Daniel Vetter; +Cc: intel-gfx On Wed, Mar 05, 2014 at 01:05:46PM +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > gen7_enable_fbc() may write to some registers which we've already > touched, so use RMW so that we don't undo any previous updates. > > Also note that we implemnt WaFbcAsynchFlipDisableFbcQueue:bdw. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> CC stable? > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 245d3ae..3411ad7 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -294,10 +294,13 @@ static void gen7_enable_fbc(struct drm_crtc *crtc) > > if (IS_IVYBRIDGE(dev)) { > /* WaFbcAsynchFlipDisableFbcQueue:ivb */ > - I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); > + I915_WRITE(ILK_DISPLAY_CHICKEN1, > + I915_READ(ILK_DISPLAY_CHICKEN1) | > + ILK_FBCQ_DIS); > } else { > - /* WaFbcAsynchFlipDisableFbcQueue:hsw */ > + /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ > I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), > + I915_READ(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe)) | > HSW_BYPASS_FBC_QUEUE); > } > > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ben Widawsky, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions 2014-03-05 11:05 [PATCH 0/3] drm/i915: Fix BDW sprite colors and a few cleanups ville.syrjala 2014-03-05 11:05 ` [PATCH 1/3] drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW ville.syrjala 2014-03-05 11:05 ` [PATCH 2/3] drm/i915: Use RMW to update chicken bits in gen7_enable_fbc() ville.syrjala @ 2014-03-05 11:05 ` ville.syrjala 2014-03-05 14:40 ` Damien Lespiau 2 siblings, 1 reply; 9+ messages in thread From: ville.syrjala @ 2014-03-05 11:05 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> We have two names for the same register CHICKEN_PIPESL_1 and HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one. Also rename the FBCQ disable bit to resemble the name we've given to a similar bit on earlier platforms. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 10 ++-------- drivers/gpu/drm/i915/intel_pm.c | 8 ++++---- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e313035..ad3151a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1126,13 +1126,6 @@ #define FBC_REND_NUKE (1<<2) #define FBC_REND_CACHE_CLEAN (1<<1) -#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 -#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 -#define HSW_BYPASS_FBC_QUEUE (1<<22) -#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \ - _HSW_PIPE_SLICE_CHICKEN_1_A, + \ - _HSW_PIPE_SLICE_CHICKEN_1_B) - /* * GPIO regs */ @@ -4145,7 +4138,8 @@ #define _CHICKEN_PIPESL_1_A 0x420b0 #define _CHICKEN_PIPESL_1_B 0x420b4 -#define DPRS_MASK_VBLANK_SRD (1 << 0) +#define HSW_FBCQ_DIS (1 << 22) +#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) #define DISP_ARB_CTL 0x45000 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3411ad7..7a693e9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -299,9 +299,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc) ILK_FBCQ_DIS); } else { /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ - I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), - I915_READ(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe)) | - HSW_BYPASS_FBC_QUEUE); + I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), + I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | + HSW_FBCQ_DIS); } I915_WRITE(SNB_DPFC_CTL_SA, @@ -4836,7 +4836,7 @@ static void gen8_init_clock_gating(struct drm_device *dev) for_each_pipe(i) { I915_WRITE(CHICKEN_PIPESL_1(i), I915_READ(CHICKEN_PIPESL_1(i)) | - DPRS_MASK_VBLANK_SRD); + BDW_DPRS_MASK_VBLANK_SRD); } /* Use Force Non-Coherent whenever executing a 3D context. This is a -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions 2014-03-05 11:05 ` [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions ville.syrjala @ 2014-03-05 14:40 ` Damien Lespiau 2014-03-05 18:39 ` Daniel Vetter 0 siblings, 1 reply; 9+ messages in thread From: Damien Lespiau @ 2014-03-05 14:40 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Wed, Mar 05, 2014 at 01:05:47PM +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We have two names for the same register CHICKEN_PIPESL_1 and > HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one. > > Also rename the FBCQ disable bit to resemble the name we've > given to a similar bit on earlier platforms. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> -- Damien > --- > drivers/gpu/drm/i915/i915_reg.h | 10 ++-------- > drivers/gpu/drm/i915/intel_pm.c | 8 ++++---- > 2 files changed, 6 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e313035..ad3151a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1126,13 +1126,6 @@ > #define FBC_REND_NUKE (1<<2) > #define FBC_REND_CACHE_CLEAN (1<<1) > > -#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 > -#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 > -#define HSW_BYPASS_FBC_QUEUE (1<<22) > -#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \ > - _HSW_PIPE_SLICE_CHICKEN_1_A, + \ > - _HSW_PIPE_SLICE_CHICKEN_1_B) > - > /* > * GPIO regs > */ > @@ -4145,7 +4138,8 @@ > > #define _CHICKEN_PIPESL_1_A 0x420b0 > #define _CHICKEN_PIPESL_1_B 0x420b4 > -#define DPRS_MASK_VBLANK_SRD (1 << 0) > +#define HSW_FBCQ_DIS (1 << 22) > +#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) > #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) > > #define DISP_ARB_CTL 0x45000 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 3411ad7..7a693e9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -299,9 +299,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc) > ILK_FBCQ_DIS); > } else { > /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ > - I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), > - I915_READ(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe)) | > - HSW_BYPASS_FBC_QUEUE); > + I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), > + I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | > + HSW_FBCQ_DIS); > } > > I915_WRITE(SNB_DPFC_CTL_SA, > @@ -4836,7 +4836,7 @@ static void gen8_init_clock_gating(struct drm_device *dev) > for_each_pipe(i) { > I915_WRITE(CHICKEN_PIPESL_1(i), > I915_READ(CHICKEN_PIPESL_1(i)) | > - DPRS_MASK_VBLANK_SRD); > + BDW_DPRS_MASK_VBLANK_SRD); > } > > /* Use Force Non-Coherent whenever executing a 3D context. This is a > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions 2014-03-05 14:40 ` Damien Lespiau @ 2014-03-05 18:39 ` Daniel Vetter 0 siblings, 0 replies; 9+ messages in thread From: Daniel Vetter @ 2014-03-05 18:39 UTC (permalink / raw) To: Damien Lespiau; +Cc: intel-gfx On Wed, Mar 05, 2014 at 02:40:58PM +0000, Damien Lespiau wrote: > On Wed, Mar 05, 2014 at 01:05:47PM +0200, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > We have two names for the same register CHICKEN_PIPESL_1 and > > HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one. > > > > Also rename the FBCQ disable bit to resemble the name we've > > given to a similar bit on earlier platforms. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2014-03-21 18:53 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-03-05 11:05 [PATCH 0/3] drm/i915: Fix BDW sprite colors and a few cleanups ville.syrjala 2014-03-05 11:05 ` [PATCH 1/3] drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW ville.syrjala 2014-03-05 12:09 ` Damien Lespiau 2014-03-05 11:05 ` [PATCH 2/3] drm/i915: Use RMW to update chicken bits in gen7_enable_fbc() ville.syrjala 2014-03-05 14:31 ` Damien Lespiau 2014-03-21 18:52 ` Ben Widawsky 2014-03-05 11:05 ` [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions ville.syrjala 2014-03-05 14:40 ` Damien Lespiau 2014-03-05 18:39 ` Daniel Vetter
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox