[PATCH] drm/i915: vlv: fix RPS interrupt mask setting

[PATCH] drm/i915: vlv: fix RPS interrupt mask setting

[Imre Deak]

This typo may lead to missed RPS interrupts and as a result a too
low or too high frequency for the current workload. The interrupt mask
will be set properly at a subsequent GPU idle event, but can get
corrupted again at the next RPS up/down event.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 00e4c7e..ef334f6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3159,7 +3159,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
 	if (val != dev_priv->rps.cur_freq)
 		vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
 
-	I915_WRITE(GEN6_PMINTRMSK, val);
+	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
 
 	dev_priv->rps.cur_freq = val;
 	trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
-- 
1.8.4

Re: [PATCH] drm/i915: vlv: fix RPS interrupt mask setting

[Chris Wilson]

On Thu, Apr 03, 2014 at 08:02:42PM +0300, Imre Deak wrote:
> This typo may lead to missed RPS interrupts and as a result a too
> low or too high frequency for the current workload. The interrupt mask
> will be set properly at a subsequent GPU idle event, but can get
> corrupted again at the next RPS up/down event.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Embarrassing. Really odd as I thought I just cut'n'paste that line.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH] drm/i915: vlv: fix RPS interrupt mask setting

[Daniel Vetter]

On Thu, Apr 03, 2014 at 09:28:34PM +0100, Chris Wilson wrote:
> On Thu, Apr 03, 2014 at 08:02:42PM +0300, Imre Deak wrote:
> > This typo may lead to missed RPS interrupts and as a result a too
> > low or too high frequency for the current workload. The interrupt mask
> > will be set properly at a subsequent GPU idle event, but can get
> > corrupted again at the next RPS up/down event.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> 
> Embarrassing. Really odd as I thought I just cut'n'paste that line.
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Picked up for -fixes, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch