[PATCH v3] drm/i915: Handle RC6 counter wrap

[PATCH v3] drm/i915: Handle RC6 counter wrap

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

We can implement limited RC6 counter wrap-around protection under the
assumption that clients will be reading this value more frequently than
the wrap period on a given platform.

With the typical wrap-around period being ~90 minutes, even with the
exception of Baytrail which wraps every 13 seconds, this sounds like a
reasonable assumption.

Implementation works by storing a 64-bit software copy of a hardware RC6
counter, along with the previous HW counter snapshot. This enables it to
detect wrap is polled frequently enough and keep the software copy
monotonically incrementing.

v2:
 * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
   indexing.
 * Fixed off-by-one in wrap-around handling. (Chris Wilson)

v3:
 * Simplify index checking by using unsigned int. (Chris Wilson)
 * Expand the comment to explain why indexing works.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c | 62 +++++++++++++++++++++++++++++++++++------
 2 files changed, 55 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ad1fc845cd1b..28a2671a26c7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -946,6 +946,8 @@ struct intel_rps {
 
 struct intel_rc6 {
 	bool enabled;
+	u64 prev_hw_residency[4];
+	u64 cur_residency[4];
 };
 
 struct intel_llc_pstate {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 41f26ab46501..063c885175e7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9417,15 +9417,16 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
 			     const i915_reg_t reg)
 {
 	u32 lower, upper, tmp;
-	unsigned long flags;
 	int loop = 2;
 
-	/* The register accessed do not need forcewake. We borrow
+	/*
+	 * The register accessed do not need forcewake. We borrow
 	 * uncore lock to prevent concurrent access to range reg.
 	 */
-	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+	lockdep_assert_held(&dev_priv->uncore.lock);
 
-	/* vlv and chv residency counters are 40 bits in width.
+	/*
+	 * vlv and chv residency counters are 40 bits in width.
 	 * With a control bit, we can choose between upper or lower
 	 * 32bit window into this counter.
 	 *
@@ -9449,29 +9450,49 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
 		upper = I915_READ_FW(reg);
 	} while (upper != tmp && --loop);
 
-	/* Everywhere else we always use VLV_COUNTER_CONTROL with the
+	/*
+	 * Everywhere else we always use VLV_COUNTER_CONTROL with the
 	 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
 	 * now.
 	 */
 
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
-
 	return lower | (u64)upper << 8;
 }
 
 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
 			   const i915_reg_t reg)
 {
-	u64 time_hw;
+	u64 time_hw, prev_hw, overflow_hw;
+	unsigned int fw_domains;
+	unsigned long flags;
+	unsigned int i;
 	u32 mul, div;
 
 	if (!HAS_RC6(dev_priv))
 		return 0;
 
+	/*
+	 * Store previous hw counter values for counter wrap-around handling.
+	 *
+	 * There are only four interesting registers and they live next to each
+	 * other so we can use the relative address, compared to the smallest
+	 * one as the index into driver storage.
+	 */
+	i = (i915_mmio_reg_offset(reg) -
+	     i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
+	if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
+		return 0;
+
+	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
+
+	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
+
 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		mul = 1000000;
 		div = dev_priv->czclk_freq;
+		overflow_hw = BIT_ULL(40);
 		time_hw = vlv_residency_raw(dev_priv, reg);
 	} else {
 		/* 833.33ns units on Gen9LP, 1.28us elsewhere. */
@@ -9483,9 +9504,32 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
 			div = 1;
 		}
 
-		time_hw = I915_READ(reg);
+		overflow_hw = BIT_ULL(32);
+		time_hw = I915_READ_FW(reg);
 	}
 
+	/*
+	 * Counter wrap handling.
+	 *
+	 * But relying on a sufficient frequency of queries otherwise counters
+	 * can still wrap.
+	 */
+	prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
+	dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
+
+	/* RC6 delta from last sample. */
+	if (time_hw >= prev_hw)
+		time_hw -= prev_hw;
+	else
+		time_hw += overflow_hw - prev_hw;
+
+	/* Add delta to RC6 extended raw driver copy. */
+	time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
+	dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
+
+	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
+
 	return DIV_ROUND_UP_ULL(time_hw * mul, div);
 }
 
-- 
2.14.1

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Re: [PATCH v3] drm/i915: Handle RC6 counter wrap

[Ville Syrjälä]

On Thu, Feb 08, 2018 at 08:18:42AM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> We can implement limited RC6 counter wrap-around protection under the
> assumption that clients will be reading this value more frequently than
> the wrap period on a given platform.
> 
> With the typical wrap-around period being ~90 minutes, even with the
> exception of Baytrail which wraps every 13 seconds, this sounds like a
> reasonable assumption.
> 
> Implementation works by storing a 64-bit software copy of a hardware RC6
> counter, along with the previous HW counter snapshot. This enables it to
> detect wrap is polled frequently enough and keep the software copy
> monotonically incrementing.
> 
> v2:
>  * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
>    indexing.
>  * Fixed off-by-one in wrap-around handling. (Chris Wilson)
> 
> v3:
>  * Simplify index checking by using unsigned int. (Chris Wilson)
>  * Expand the comment to explain why indexing works.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 ++
>  drivers/gpu/drm/i915/intel_pm.c | 62 +++++++++++++++++++++++++++++++++++------
>  2 files changed, 55 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ad1fc845cd1b..28a2671a26c7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -946,6 +946,8 @@ struct intel_rps {
>  
>  struct intel_rc6 {
>  	bool enabled;
> +	u64 prev_hw_residency[4];
> +	u64 cur_residency[4];
>  };
>  
>  struct intel_llc_pstate {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 41f26ab46501..063c885175e7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9417,15 +9417,16 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
>  			     const i915_reg_t reg)
>  {
>  	u32 lower, upper, tmp;
> -	unsigned long flags;
>  	int loop = 2;
>  
> -	/* The register accessed do not need forcewake. We borrow
> +	/*
> +	 * The register accessed do not need forcewake. We borrow
>  	 * uncore lock to prevent concurrent access to range reg.
>  	 */
> -	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> +	lockdep_assert_held(&dev_priv->uncore.lock);
>  
> -	/* vlv and chv residency counters are 40 bits in width.
> +	/*
> +	 * vlv and chv residency counters are 40 bits in width.
>  	 * With a control bit, we can choose between upper or lower
>  	 * 32bit window into this counter.
>  	 *
> @@ -9449,29 +9450,49 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
>  		upper = I915_READ_FW(reg);
>  	} while (upper != tmp && --loop);
>  
> -	/* Everywhere else we always use VLV_COUNTER_CONTROL with the
> +	/*
> +	 * Everywhere else we always use VLV_COUNTER_CONTROL with the
>  	 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
>  	 * now.
>  	 */
>  
> -	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> -
>  	return lower | (u64)upper << 8;
>  }
>  
>  u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
>  			   const i915_reg_t reg)
>  {
> -	u64 time_hw;
> +	u64 time_hw, prev_hw, overflow_hw;
> +	unsigned int fw_domains;
> +	unsigned long flags;
> +	unsigned int i;
>  	u32 mul, div;
>  
>  	if (!HAS_RC6(dev_priv))
>  		return 0;
>  
> +	/*
> +	 * Store previous hw counter values for counter wrap-around handling.
> +	 *
> +	 * There are only four interesting registers and they live next to each
> +	 * other so we can use the relative address, compared to the smallest
> +	 * one as the index into driver storage.
> +	 */
> +	i = (i915_mmio_reg_offset(reg) -
> +	     i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
> +	if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
> +		return 0;
> +
> +	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
> +
> +	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> +	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> +
>  	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		mul = 1000000;
>  		div = dev_priv->czclk_freq;
> +		overflow_hw = BIT_ULL(40);
>  		time_hw = vlv_residency_raw(dev_priv, reg);
>  	} else {
>  		/* 833.33ns units on Gen9LP, 1.28us elsewhere. */
> @@ -9483,9 +9504,32 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
>  			div = 1;
>  		}
>  
> -		time_hw = I915_READ(reg);
> +		overflow_hw = BIT_ULL(32);
> +		time_hw = I915_READ_FW(reg);
>  	}
>  
> +	/*
> +	 * Counter wrap handling.
> +	 *
> +	 * But relying on a sufficient frequency of queries otherwise counters
> +	 * can still wrap.
> +	 */
> +	prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
> +	dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
> +
> +	/* RC6 delta from last sample. */
> +	if (time_hw >= prev_hw)
> +		time_hw -= prev_hw;
> +	else
> +		time_hw += overflow_hw - prev_hw;
> +
> +	/* Add delta to RC6 extended raw driver copy. */
> +	time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
> +	dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
> +
> +	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> +
>  	return DIV_ROUND_UP_ULL(time_hw * mul, div);

What happens when time_hw*mul+div-1 overflows?

>  }
>  
> -- 
> 2.14.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v3] drm/i915: Handle RC6 counter wrap

[Tvrtko Ursulin]

On 08/02/2018 14:06, Ville Syrjälä wrote:
> On Thu, Feb 08, 2018 at 08:18:42AM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> We can implement limited RC6 counter wrap-around protection under the
>> assumption that clients will be reading this value more frequently than
>> the wrap period on a given platform.
>>
>> With the typical wrap-around period being ~90 minutes, even with the
>> exception of Baytrail which wraps every 13 seconds, this sounds like a
>> reasonable assumption.
>>
>> Implementation works by storing a 64-bit software copy of a hardware RC6
>> counter, along with the previous HW counter snapshot. This enables it to
>> detect wrap is polled frequently enough and keep the software copy
>> monotonically incrementing.
>>
>> v2:
>>   * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
>>     indexing.
>>   * Fixed off-by-one in wrap-around handling. (Chris Wilson)
>>
>> v3:
>>   * Simplify index checking by using unsigned int. (Chris Wilson)
>>   * Expand the comment to explain why indexing works.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h |  2 ++
>>   drivers/gpu/drm/i915/intel_pm.c | 62 +++++++++++++++++++++++++++++++++++------
>>   2 files changed, 55 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index ad1fc845cd1b..28a2671a26c7 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -946,6 +946,8 @@ struct intel_rps {
>>   
>>   struct intel_rc6 {
>>   	bool enabled;
>> +	u64 prev_hw_residency[4];
>> +	u64 cur_residency[4];
>>   };
>>   
>>   struct intel_llc_pstate {
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 41f26ab46501..063c885175e7 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -9417,15 +9417,16 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
>>   			     const i915_reg_t reg)
>>   {
>>   	u32 lower, upper, tmp;
>> -	unsigned long flags;
>>   	int loop = 2;
>>   
>> -	/* The register accessed do not need forcewake. We borrow
>> +	/*
>> +	 * The register accessed do not need forcewake. We borrow
>>   	 * uncore lock to prevent concurrent access to range reg.
>>   	 */
>> -	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
>> +	lockdep_assert_held(&dev_priv->uncore.lock);
>>   
>> -	/* vlv and chv residency counters are 40 bits in width.
>> +	/*
>> +	 * vlv and chv residency counters are 40 bits in width.
>>   	 * With a control bit, we can choose between upper or lower
>>   	 * 32bit window into this counter.
>>   	 *
>> @@ -9449,29 +9450,49 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
>>   		upper = I915_READ_FW(reg);
>>   	} while (upper != tmp && --loop);
>>   
>> -	/* Everywhere else we always use VLV_COUNTER_CONTROL with the
>> +	/*
>> +	 * Everywhere else we always use VLV_COUNTER_CONTROL with the
>>   	 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
>>   	 * now.
>>   	 */
>>   
>> -	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
>> -
>>   	return lower | (u64)upper << 8;
>>   }
>>   
>>   u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
>>   			   const i915_reg_t reg)
>>   {
>> -	u64 time_hw;
>> +	u64 time_hw, prev_hw, overflow_hw;
>> +	unsigned int fw_domains;
>> +	unsigned long flags;
>> +	unsigned int i;
>>   	u32 mul, div;
>>   
>>   	if (!HAS_RC6(dev_priv))
>>   		return 0;
>>   
>> +	/*
>> +	 * Store previous hw counter values for counter wrap-around handling.
>> +	 *
>> +	 * There are only four interesting registers and they live next to each
>> +	 * other so we can use the relative address, compared to the smallest
>> +	 * one as the index into driver storage.
>> +	 */
>> +	i = (i915_mmio_reg_offset(reg) -
>> +	     i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
>> +	if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
>> +		return 0;
>> +
>> +	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
>> +
>> +	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
>> +	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>> +
>>   	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
>>   	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>>   		mul = 1000000;
>>   		div = dev_priv->czclk_freq;
>> +		overflow_hw = BIT_ULL(40);
>>   		time_hw = vlv_residency_raw(dev_priv, reg);
>>   	} else {
>>   		/* 833.33ns units on Gen9LP, 1.28us elsewhere. */
>> @@ -9483,9 +9504,32 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
>>   			div = 1;
>>   		}
>>   
>> -		time_hw = I915_READ(reg);
>> +		overflow_hw = BIT_ULL(32);
>> +		time_hw = I915_READ_FW(reg);
>>   	}
>>   
>> +	/*
>> +	 * Counter wrap handling.
>> +	 *
>> +	 * But relying on a sufficient frequency of queries otherwise counters
>> +	 * can still wrap.
>> +	 */
>> +	prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
>> +	dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
>> +
>> +	/* RC6 delta from last sample. */
>> +	if (time_hw >= prev_hw)
>> +		time_hw -= prev_hw;
>> +	else
>> +		time_hw += overflow_hw - prev_hw;
>> +
>> +	/* Add delta to RC6 extended raw driver copy. */
>> +	time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
>> +	dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
>> +
>> +	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
>> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
>> +
>>   	return DIV_ROUND_UP_ULL(time_hw * mul, div);
> 
> What happens when time_hw*mul+div-1 overflows?

It overflows. :I

Apart on Valleyview multipler is 14 bits max, so we still get 64 - 14 - 
1 = 49 bits of software stored RC6 before it happens. Given that the 
info if 32-bits is 50 minutes or so, 49 bits sounds good enough.

On Valleyview multiplier is 20 bits so 64 - 20 - 1 = 43 bits before 
overflow. A bit less than above, and I am not sure what the 40-bit hw 
counter overflow period is there to start with? Is 8 times that enough? 
Or not?

Suggestions?

Regards,

Tvrtko
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Re: [PATCH v3] drm/i915: Handle RC6 counter wrap

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-08 14:31:05)
> 
> On 08/02/2018 14:06, Ville Syrjälä wrote:
> > On Thu, Feb 08, 2018 at 08:18:42AM +0000, Tvrtko Ursulin wrote:
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> We can implement limited RC6 counter wrap-around protection under the
> >> assumption that clients will be reading this value more frequently than
> >> the wrap period on a given platform.
> >>
> >> With the typical wrap-around period being ~90 minutes, even with the
> >> exception of Baytrail which wraps every 13 seconds, this sounds like a
> >> reasonable assumption.
> >>
> >> Implementation works by storing a 64-bit software copy of a hardware RC6
> >> counter, along with the previous HW counter snapshot. This enables it to
> >> detect wrap is polled frequently enough and keep the software copy
> >> monotonically incrementing.
> >>
> >> v2:
> >>   * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
> >>     indexing.
> >>   * Fixed off-by-one in wrap-around handling. (Chris Wilson)
> >>
> >> v3:
> >>   * Simplify index checking by using unsigned int. (Chris Wilson)
> >>   * Expand the comment to explain why indexing works.
> >>
> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
> >> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> >> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> >> ---
> >>   drivers/gpu/drm/i915/i915_drv.h |  2 ++
> >>   drivers/gpu/drm/i915/intel_pm.c | 62 +++++++++++++++++++++++++++++++++++------
> >>   2 files changed, 55 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index ad1fc845cd1b..28a2671a26c7 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -946,6 +946,8 @@ struct intel_rps {
> >>   
> >>   struct intel_rc6 {
> >>      bool enabled;
> >> +    u64 prev_hw_residency[4];
> >> +    u64 cur_residency[4];
> >>   };
> >>   
> >>   struct intel_llc_pstate {
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> index 41f26ab46501..063c885175e7 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -9417,15 +9417,16 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
> >>                           const i915_reg_t reg)
> >>   {
> >>      u32 lower, upper, tmp;
> >> -    unsigned long flags;
> >>      int loop = 2;
> >>   
> >> -    /* The register accessed do not need forcewake. We borrow
> >> +    /*
> >> +     * The register accessed do not need forcewake. We borrow
> >>       * uncore lock to prevent concurrent access to range reg.
> >>       */
> >> -    spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> >> +    lockdep_assert_held(&dev_priv->uncore.lock);
> >>   
> >> -    /* vlv and chv residency counters are 40 bits in width.
> >> +    /*
> >> +     * vlv and chv residency counters are 40 bits in width.
> >>       * With a control bit, we can choose between upper or lower
> >>       * 32bit window into this counter.
> >>       *
> >> @@ -9449,29 +9450,49 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
> >>              upper = I915_READ_FW(reg);
> >>      } while (upper != tmp && --loop);
> >>   
> >> -    /* Everywhere else we always use VLV_COUNTER_CONTROL with the
> >> +    /*
> >> +     * Everywhere else we always use VLV_COUNTER_CONTROL with the
> >>       * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
> >>       * now.
> >>       */
> >>   
> >> -    spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> >> -
> >>      return lower | (u64)upper << 8;
> >>   }
> >>   
> >>   u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> >>                         const i915_reg_t reg)
> >>   {
> >> -    u64 time_hw;
> >> +    u64 time_hw, prev_hw, overflow_hw;
> >> +    unsigned int fw_domains;
> >> +    unsigned long flags;
> >> +    unsigned int i;
> >>      u32 mul, div;
> >>   
> >>      if (!HAS_RC6(dev_priv))
> >>              return 0;
> >>   
> >> +    /*
> >> +     * Store previous hw counter values for counter wrap-around handling.
> >> +     *
> >> +     * There are only four interesting registers and they live next to each
> >> +     * other so we can use the relative address, compared to the smallest
> >> +     * one as the index into driver storage.
> >> +     */
> >> +    i = (i915_mmio_reg_offset(reg) -
> >> +         i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
> >> +    if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
> >> +            return 0;
> >> +
> >> +    fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
> >> +
> >> +    spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> >> +    intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> >> +
> >>      /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
> >>      if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> >>              mul = 1000000;
> >>              div = dev_priv->czclk_freq;
> >> +            overflow_hw = BIT_ULL(40);
> >>              time_hw = vlv_residency_raw(dev_priv, reg);
> >>      } else {
> >>              /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
> >> @@ -9483,9 +9504,32 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> >>                      div = 1;
> >>              }
> >>   
> >> -            time_hw = I915_READ(reg);
> >> +            overflow_hw = BIT_ULL(32);
> >> +            time_hw = I915_READ_FW(reg);
> >>      }
> >>   
> >> +    /*
> >> +     * Counter wrap handling.
> >> +     *
> >> +     * But relying on a sufficient frequency of queries otherwise counters
> >> +     * can still wrap.
> >> +     */
> >> +    prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
> >> +    dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
> >> +
> >> +    /* RC6 delta from last sample. */
> >> +    if (time_hw >= prev_hw)
> >> +            time_hw -= prev_hw;
> >> +    else
> >> +            time_hw += overflow_hw - prev_hw;
> >> +
> >> +    /* Add delta to RC6 extended raw driver copy. */
> >> +    time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
> >> +    dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
> >> +
> >> +    intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> >> +    spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> >> +
> >>      return DIV_ROUND_UP_ULL(time_hw * mul, div);
> > 
> > What happens when time_hw*mul+div-1 overflows?
> 
> It overflows. :I
> 
> Apart on Valleyview multipler is 14 bits max, so we still get 64 - 14 - 
> 1 = 49 bits of software stored RC6 before it happens. Given that the 
> info if 32-bits is 50 minutes or so, 49 bits sounds good enough.
> 
> On Valleyview multiplier is 20 bits so 64 - 20 - 1 = 43 bits before 
> overflow. A bit less than above, and I am not sure what the 40-bit hw 
> counter overflow period is there to start with? Is 8 times that enough? 
> Or not?

Off the top of my head, 8 hours. Definitely within a timescale that
someone could be monitoring.
 
> Suggestions?

We can extend to uint128_t quite easily on 64b platforms (hmm, but how
much is allowed for freestanding?), otherwise time to whip up a 128b
math library ;)
https://cgit.freedesktop.org/cairo/tree/src/cairo-wideint.c

u64_mul_u64_u32_div_u32_roundup ?
-Chris
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[PATCH v4] drm/i915: Handle RC6 counter wrap

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

We can implement limited RC6 counter wrap-around protection under the
assumption that clients will be reading this value more frequently than
the wrap period on a given platform.

With the typical wrap-around period being ~90 minutes, even with the
exception of Baytrail which wraps every 13 seconds, this sounds like a
reasonable assumption.

Implementation works by storing a 64-bit software copy of a hardware RC6
counter, along with the previous HW counter snapshot. This enables it to
detect wrap is polled frequently enough and keep the software copy
monotonically incrementing.

v2:
 * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
   indexing.
 * Fixed off-by-one in wrap-around handling. (Chris Wilson)

v3:
 * Simplify index checking by using unsigned int. (Chris Wilson)
 * Expand the comment to explain why indexing works.

v4:
 * Use __int128 if supported.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v3
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c | 72 +++++++++++++++++++++++++++++++++++------
 2 files changed, 64 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ad1fc845cd1b..28a2671a26c7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -946,6 +946,8 @@ struct intel_rps {
 
 struct intel_rc6 {
 	bool enabled;
+	u64 prev_hw_residency[4];
+	u64 cur_residency[4];
 };
 
 struct intel_llc_pstate {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 41f26ab46501..24d9423c5f9e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9417,15 +9417,16 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
 			     const i915_reg_t reg)
 {
 	u32 lower, upper, tmp;
-	unsigned long flags;
 	int loop = 2;
 
-	/* The register accessed do not need forcewake. We borrow
+	/*
+	 * The register accessed do not need forcewake. We borrow
 	 * uncore lock to prevent concurrent access to range reg.
 	 */
-	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+	lockdep_assert_held(&dev_priv->uncore.lock);
 
-	/* vlv and chv residency counters are 40 bits in width.
+	/*
+	 * vlv and chv residency counters are 40 bits in width.
 	 * With a control bit, we can choose between upper or lower
 	 * 32bit window into this counter.
 	 *
@@ -9449,29 +9450,54 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
 		upper = I915_READ_FW(reg);
 	} while (upper != tmp && --loop);
 
-	/* Everywhere else we always use VLV_COUNTER_CONTROL with the
+	/*
+	 * Everywhere else we always use VLV_COUNTER_CONTROL with the
 	 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
 	 * now.
 	 */
 
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
-
 	return lower | (u64)upper << 8;
 }
 
 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
 			   const i915_reg_t reg)
 {
-	u64 time_hw;
+#if IS_ENABLED(CONFIG_ARCH_SUPPORTS_INT128)
+	unsigned __int128 acc;
+#else
+	u64 acc;
+#endif
+	u64 time_hw, prev_hw, overflow_hw;
+	unsigned int fw_domains;
+	unsigned long flags;
+	unsigned int i;
 	u32 mul, div;
 
 	if (!HAS_RC6(dev_priv))
 		return 0;
 
+	/*
+	 * Store previous hw counter values for counter wrap-around handling.
+	 *
+	 * There are only four interesting registers and they live next to each
+	 * other so we can use the relative address, compared to the smallest
+	 * one as the index into driver storage.
+	 */
+	i = (i915_mmio_reg_offset(reg) -
+	     i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
+	if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
+		return 0;
+
+	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
+
+	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
+
 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		mul = 1000000;
 		div = dev_priv->czclk_freq;
+		overflow_hw = BIT_ULL(40);
 		time_hw = vlv_residency_raw(dev_priv, reg);
 	} else {
 		/* 833.33ns units on Gen9LP, 1.28us elsewhere. */
@@ -9483,10 +9509,36 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
 			div = 1;
 		}
 
-		time_hw = I915_READ(reg);
+		overflow_hw = BIT_ULL(32);
+		time_hw = I915_READ_FW(reg);
 	}
 
-	return DIV_ROUND_UP_ULL(time_hw * mul, div);
+	/*
+	 * Counter wrap handling.
+	 *
+	 * But relying on a sufficient frequency of queries otherwise counters
+	 * can still wrap.
+	 */
+	prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
+	dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
+
+	/* RC6 delta from last sample. */
+	if (time_hw >= prev_hw)
+		time_hw -= prev_hw;
+	else
+		time_hw += overflow_hw - prev_hw;
+
+	/* Add delta to RC6 extended raw driver copy. */
+	time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
+	dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
+
+	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
+
+	acc = time_hw;
+	acc *= mul;
+
+	return DIV_ROUND_UP_ULL(acc, div);
 }
 
 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
-- 
2.14.1

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Re: [PATCH v4] drm/i915: Handle RC6 counter wrap

[Tvrtko Ursulin]

On 08/02/2018 15:46, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> We can implement limited RC6 counter wrap-around protection under the
> assumption that clients will be reading this value more frequently than
> the wrap period on a given platform.
> 
> With the typical wrap-around period being ~90 minutes, even with the
> exception of Baytrail which wraps every 13 seconds, this sounds like a
> reasonable assumption.
> 
> Implementation works by storing a 64-bit software copy of a hardware RC6
> counter, along with the previous HW counter snapshot. This enables it to
> detect wrap is polled frequently enough and keep the software copy
> monotonically incrementing.
> 
> v2:
>   * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
>     indexing.
>   * Fixed off-by-one in wrap-around handling. (Chris Wilson)
> 
> v3:
>   * Simplify index checking by using unsigned int. (Chris Wilson)
>   * Expand the comment to explain why indexing works.
> 
> v4:
>   * Use __int128 if supported.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v3
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h |  2 ++
>   drivers/gpu/drm/i915/intel_pm.c | 72 +++++++++++++++++++++++++++++++++++------
>   2 files changed, 64 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ad1fc845cd1b..28a2671a26c7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -946,6 +946,8 @@ struct intel_rps {
>   
>   struct intel_rc6 {
>   	bool enabled;
> +	u64 prev_hw_residency[4];
> +	u64 cur_residency[4];
>   };
>   
>   struct intel_llc_pstate {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 41f26ab46501..24d9423c5f9e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9417,15 +9417,16 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
>   			     const i915_reg_t reg)
>   {
>   	u32 lower, upper, tmp;
> -	unsigned long flags;
>   	int loop = 2;
>   
> -	/* The register accessed do not need forcewake. We borrow
> +	/*
> +	 * The register accessed do not need forcewake. We borrow
>   	 * uncore lock to prevent concurrent access to range reg.
>   	 */
> -	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> +	lockdep_assert_held(&dev_priv->uncore.lock);
>   
> -	/* vlv and chv residency counters are 40 bits in width.
> +	/*
> +	 * vlv and chv residency counters are 40 bits in width.
>   	 * With a control bit, we can choose between upper or lower
>   	 * 32bit window into this counter.
>   	 *
> @@ -9449,29 +9450,54 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
>   		upper = I915_READ_FW(reg);
>   	} while (upper != tmp && --loop);
>   
> -	/* Everywhere else we always use VLV_COUNTER_CONTROL with the
> +	/*
> +	 * Everywhere else we always use VLV_COUNTER_CONTROL with the
>   	 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
>   	 * now.
>   	 */
>   
> -	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> -
>   	return lower | (u64)upper << 8;
>   }
>   
>   u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
>   			   const i915_reg_t reg)
>   {
> -	u64 time_hw;
> +#if IS_ENABLED(CONFIG_ARCH_SUPPORTS_INT128)
> +	unsigned __int128 acc;
> +#else
> +	u64 acc;
> +#endif
> +	u64 time_hw, prev_hw, overflow_hw;
> +	unsigned int fw_domains;
> +	unsigned long flags;
> +	unsigned int i;
>   	u32 mul, div;
>   
>   	if (!HAS_RC6(dev_priv))
>   		return 0;
>   
> +	/*
> +	 * Store previous hw counter values for counter wrap-around handling.
> +	 *
> +	 * There are only four interesting registers and they live next to each
> +	 * other so we can use the relative address, compared to the smallest
> +	 * one as the index into driver storage.
> +	 */
> +	i = (i915_mmio_reg_offset(reg) -
> +	     i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
> +	if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
> +		return 0;
> +
> +	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
> +
> +	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> +	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> +
>   	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
>   	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>   		mul = 1000000;
>   		div = dev_priv->czclk_freq;
> +		overflow_hw = BIT_ULL(40);
>   		time_hw = vlv_residency_raw(dev_priv, reg);
>   	} else {
>   		/* 833.33ns units on Gen9LP, 1.28us elsewhere. */
> @@ -9483,10 +9509,36 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
>   			div = 1;
>   		}
>   
> -		time_hw = I915_READ(reg);
> +		overflow_hw = BIT_ULL(32);
> +		time_hw = I915_READ_FW(reg);
>   	}
>   
> -	return DIV_ROUND_UP_ULL(time_hw * mul, div);
> +	/*
> +	 * Counter wrap handling.
> +	 *
> +	 * But relying on a sufficient frequency of queries otherwise counters
> +	 * can still wrap.
> +	 */
> +	prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
> +	dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
> +
> +	/* RC6 delta from last sample. */
> +	if (time_hw >= prev_hw)
> +		time_hw -= prev_hw;
> +	else
> +		time_hw += overflow_hw - prev_hw;
> +
> +	/* Add delta to RC6 extended raw driver copy. */
> +	time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
> +	dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
> +
> +	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> +
> +	acc = time_hw;
> +	acc *= mul;
> +
> +	return DIV_ROUND_UP_ULL(acc, div);

Nope, this casts to 64-bit before division..

Regards,

Tvrtko

>   }
>   
>   u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
> 
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Re: [PATCH v4] drm/i915: Handle RC6 counter wrap

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-08 15:46:38)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> We can implement limited RC6 counter wrap-around protection under the
> assumption that clients will be reading this value more frequently than
> the wrap period on a given platform.
> 
> With the typical wrap-around period being ~90 minutes, even with the
> exception of Baytrail which wraps every 13 seconds, this sounds like a
> reasonable assumption.
> 
> Implementation works by storing a 64-bit software copy of a hardware RC6
> counter, along with the previous HW counter snapshot. This enables it to
> detect wrap is polled frequently enough and keep the software copy
> monotonically incrementing.
> 
> v2:
>  * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
>    indexing.
>  * Fixed off-by-one in wrap-around handling. (Chris Wilson)
> 
> v3:
>  * Simplify index checking by using unsigned int. (Chris Wilson)
>  * Expand the comment to explain why indexing works.
> 
> v4:
>  * Use __int128 if supported.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v3
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 ++
>  drivers/gpu/drm/i915/intel_pm.c | 72 +++++++++++++++++++++++++++++++++++------
>  2 files changed, 64 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ad1fc845cd1b..28a2671a26c7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -946,6 +946,8 @@ struct intel_rps {
>  
>  struct intel_rc6 {
>         bool enabled;
> +       u64 prev_hw_residency[4];
> +       u64 cur_residency[4];
>  };
>  
>  struct intel_llc_pstate {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 41f26ab46501..24d9423c5f9e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9417,15 +9417,16 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
>                              const i915_reg_t reg)
>  {
>         u32 lower, upper, tmp;
> -       unsigned long flags;
>         int loop = 2;
>  
> -       /* The register accessed do not need forcewake. We borrow
> +       /*
> +        * The register accessed do not need forcewake. We borrow
>          * uncore lock to prevent concurrent access to range reg.
>          */
> -       spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> +       lockdep_assert_held(&dev_priv->uncore.lock);
>  
> -       /* vlv and chv residency counters are 40 bits in width.
> +       /*
> +        * vlv and chv residency counters are 40 bits in width.
>          * With a control bit, we can choose between upper or lower
>          * 32bit window into this counter.
>          *
> @@ -9449,29 +9450,54 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
>                 upper = I915_READ_FW(reg);
>         } while (upper != tmp && --loop);
>  
> -       /* Everywhere else we always use VLV_COUNTER_CONTROL with the
> +       /*
> +        * Everywhere else we always use VLV_COUNTER_CONTROL with the
>          * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
>          * now.
>          */
>  
> -       spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> -
>         return lower | (u64)upper << 8;
>  }
>  
>  u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
>                            const i915_reg_t reg)
>  {
> -       u64 time_hw;
> +#if IS_ENABLED(CONFIG_ARCH_SUPPORTS_INT128)
> +       unsigned __int128 acc;
> +#else
> +       u64 acc;
> +#endif
> +       u64 time_hw, prev_hw, overflow_hw;
> +       unsigned int fw_domains;
> +       unsigned long flags;
> +       unsigned int i;
>         u32 mul, div;
>  
>         if (!HAS_RC6(dev_priv))
>                 return 0;
>  
> +       /*
> +        * Store previous hw counter values for counter wrap-around handling.
> +        *
> +        * There are only four interesting registers and they live next to each
> +        * other so we can use the relative address, compared to the smallest
> +        * one as the index into driver storage.
> +        */
> +       i = (i915_mmio_reg_offset(reg) -
> +            i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
> +       if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
> +               return 0;
> +
> +       fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
> +
> +       spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> +       intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> +
>         /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
>         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>                 mul = 1000000;
>                 div = dev_priv->czclk_freq;
> +               overflow_hw = BIT_ULL(40);
>                 time_hw = vlv_residency_raw(dev_priv, reg);
>         } else {
>                 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
> @@ -9483,10 +9509,36 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
>                         div = 1;
>                 }
>  
> -               time_hw = I915_READ(reg);
> +               overflow_hw = BIT_ULL(32);
> +               time_hw = I915_READ_FW(reg);
>         }
>  
> -       return DIV_ROUND_UP_ULL(time_hw * mul, div);
> +       /*
> +        * Counter wrap handling.
> +        *
> +        * But relying on a sufficient frequency of queries otherwise counters
> +        * can still wrap.
> +        */
> +       prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
> +       dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
> +
> +       /* RC6 delta from last sample. */
> +       if (time_hw >= prev_hw)
> +               time_hw -= prev_hw;
> +       else
> +               time_hw += overflow_hw - prev_hw;
> +
> +       /* Add delta to RC6 extended raw driver copy. */
> +       time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
> +       dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
> +
> +       intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> +       spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> +
> +       acc = time_hw;
> +       acc *= mul;
> +
> +       return DIV_ROUND_UP_ULL(acc, div);

return mul_u64_u32_div(time_hw, mul, div).

Loses roundup. But meh.
-Chris
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[PATCH v5] drm/i915: Handle RC6 counter wrap

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

We can implement limited RC6 counter wrap-around protection under the
assumption that clients will be reading this value more frequently than
the wrap period on a given platform.

With the typical wrap-around period being ~90 minutes, even with the
exception of Baytrail which wraps every 13 seconds, this sounds like a
reasonable assumption.

Implementation works by storing a 64-bit software copy of a hardware RC6
counter, along with the previous HW counter snapshot. This enables it to
detect wrap is polled frequently enough and keep the software copy
monotonically incrementing.

v2:
 * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
   indexing.
 * Fixed off-by-one in wrap-around handling. (Chris Wilson)

v3:
 * Simplify index checking by using unsigned int. (Chris Wilson)
 * Expand the comment to explain why indexing works.

v4:
 * Use __int128 if supported.

v5:
 * Use mul_u64_u32_div. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v3
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c | 64 ++++++++++++++++++++++++++++++++++-------
 2 files changed, 56 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ad1fc845cd1b..28a2671a26c7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -946,6 +946,8 @@ struct intel_rps {
 
 struct intel_rc6 {
 	bool enabled;
+	u64 prev_hw_residency[4];
+	u64 cur_residency[4];
 };
 
 struct intel_llc_pstate {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 41f26ab46501..b10f67338c0e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9417,15 +9417,16 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
 			     const i915_reg_t reg)
 {
 	u32 lower, upper, tmp;
-	unsigned long flags;
 	int loop = 2;
 
-	/* The register accessed do not need forcewake. We borrow
+	/*
+	 * The register accessed do not need forcewake. We borrow
 	 * uncore lock to prevent concurrent access to range reg.
 	 */
-	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+	lockdep_assert_held(&dev_priv->uncore.lock);
 
-	/* vlv and chv residency counters are 40 bits in width.
+	/*
+	 * vlv and chv residency counters are 40 bits in width.
 	 * With a control bit, we can choose between upper or lower
 	 * 32bit window into this counter.
 	 *
@@ -9449,29 +9450,49 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
 		upper = I915_READ_FW(reg);
 	} while (upper != tmp && --loop);
 
-	/* Everywhere else we always use VLV_COUNTER_CONTROL with the
+	/*
+	 * Everywhere else we always use VLV_COUNTER_CONTROL with the
 	 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
 	 * now.
 	 */
 
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
-
 	return lower | (u64)upper << 8;
 }
 
 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
 			   const i915_reg_t reg)
 {
-	u64 time_hw;
+	u64 time_hw, prev_hw, overflow_hw;
+	unsigned int fw_domains;
+	unsigned long flags;
+	unsigned int i;
 	u32 mul, div;
 
 	if (!HAS_RC6(dev_priv))
 		return 0;
 
+	/*
+	 * Store previous hw counter values for counter wrap-around handling.
+	 *
+	 * There are only four interesting registers and they live next to each
+	 * other so we can use the relative address, compared to the smallest
+	 * one as the index into driver storage.
+	 */
+	i = (i915_mmio_reg_offset(reg) -
+	     i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
+	if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
+		return 0;
+
+	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
+
+	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
+
 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		mul = 1000000;
 		div = dev_priv->czclk_freq;
+		overflow_hw = BIT_ULL(40);
 		time_hw = vlv_residency_raw(dev_priv, reg);
 	} else {
 		/* 833.33ns units on Gen9LP, 1.28us elsewhere. */
@@ -9483,10 +9504,33 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
 			div = 1;
 		}
 
-		time_hw = I915_READ(reg);
+		overflow_hw = BIT_ULL(32);
+		time_hw = I915_READ_FW(reg);
 	}
 
-	return DIV_ROUND_UP_ULL(time_hw * mul, div);
+	/*
+	 * Counter wrap handling.
+	 *
+	 * But relying on a sufficient frequency of queries otherwise counters
+	 * can still wrap.
+	 */
+	prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
+	dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
+
+	/* RC6 delta from last sample. */
+	if (time_hw >= prev_hw)
+		time_hw -= prev_hw;
+	else
+		time_hw += overflow_hw - prev_hw;
+
+	/* Add delta to RC6 extended raw driver copy. */
+	time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
+	dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
+
+	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
+
+	return mul_u64_u32_div(time_hw, mul, div);
 }
 
 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
-- 
2.14.1

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Re: [PATCH v5] drm/i915: Handle RC6 counter wrap

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-08 16:00:36)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> We can implement limited RC6 counter wrap-around protection under the
> assumption that clients will be reading this value more frequently than
> the wrap period on a given platform.
> 
> With the typical wrap-around period being ~90 minutes, even with the
> exception of Baytrail which wraps every 13 seconds, this sounds like a
> reasonable assumption.
> 
> Implementation works by storing a 64-bit software copy of a hardware RC6
> counter, along with the previous HW counter snapshot. This enables it to
> detect wrap is polled frequently enough and keep the software copy
> monotonically incrementing.
> 
> v2:
>  * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
>    indexing.
>  * Fixed off-by-one in wrap-around handling. (Chris Wilson)
> 
> v3:
>  * Simplify index checking by using unsigned int. (Chris Wilson)
>  * Expand the comment to explain why indexing works.
> 
> v4:
>  * Use __int128 if supported.
> 
> v5:
>  * Use mul_u64_u32_div. (Chris Wilson)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v3
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Ville better not complain he liked the round up behaviour :-p
-Chris
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Re: [PATCH v5] drm/i915: Handle RC6 counter wrap

[Tvrtko Ursulin]

On 08/02/2018 16:04, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-02-08 16:00:36)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> We can implement limited RC6 counter wrap-around protection under the
>> assumption that clients will be reading this value more frequently than
>> the wrap period on a given platform.
>>
>> With the typical wrap-around period being ~90 minutes, even with the
>> exception of Baytrail which wraps every 13 seconds, this sounds like a
>> reasonable assumption.
>>
>> Implementation works by storing a 64-bit software copy of a hardware RC6
>> counter, along with the previous HW counter snapshot. This enables it to
>> detect wrap is polled frequently enough and keep the software copy
>> monotonically incrementing.
>>
>> v2:
>>   * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
>>     indexing.
>>   * Fixed off-by-one in wrap-around handling. (Chris Wilson)
>>
>> v3:
>>   * Simplify index checking by using unsigned int. (Chris Wilson)
>>   * Expand the comment to explain why indexing works.
>>
>> v4:
>>   * Use __int128 if supported.
>>
>> v5:
>>   * Use mul_u64_u32_div. (Chris Wilson)
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v3
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> 
> Ville better not complain he liked the round up behaviour :-p

Ping Ville - ack?

Regards,

Tvrtko

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Re: [PATCH v5] drm/i915: Handle RC6 counter wrap

[Ville Syrjälä]

On Tue, Feb 13, 2018 at 02:09:51PM +0000, Tvrtko Ursulin wrote:
> 
> On 08/02/2018 16:04, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-02-08 16:00:36)
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> We can implement limited RC6 counter wrap-around protection under the
> >> assumption that clients will be reading this value more frequently than
> >> the wrap period on a given platform.
> >>
> >> With the typical wrap-around period being ~90 minutes, even with the
> >> exception of Baytrail which wraps every 13 seconds, this sounds like a
> >> reasonable assumption.
> >>
> >> Implementation works by storing a 64-bit software copy of a hardware RC6
> >> counter, along with the previous HW counter snapshot. This enables it to
> >> detect wrap is polled frequently enough and keep the software copy
> >> monotonically incrementing.
> >>
> >> v2:
> >>   * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and
> >>     indexing.
> >>   * Fixed off-by-one in wrap-around handling. (Chris Wilson)
> >>
> >> v3:
> >>   * Simplify index checking by using unsigned int. (Chris Wilson)
> >>   * Expand the comment to explain why indexing works.
> >>
> >> v4:
> >>   * Use __int128 if supported.
> >>
> >> v5:
> >>   * Use mul_u64_u32_div. (Chris Wilson)
> >>
> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852
> >> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> >> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v3
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> > 
> > Ville better not complain he liked the round up behaviour :-p
> 
> Ping Ville - ack?

ack

-- 
Ville Syrjälä
Intel OTC
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✓ Fi.CI.BAT: success for drm/i915: Handle RC6 counter wrap (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Handle RC6 counter wrap (rev3)
URL   : https://patchwork.freedesktop.org/series/37824/
State : success

== Summary ==

Series 37824v3 drm/i915: Handle RC6 counter wrap
https://patchwork.freedesktop.org/api/1.0/series/37824/revisions/3/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713 +1
Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:417s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:423s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:374s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:484s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:284s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:484s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:483s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:470s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:456s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:564s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:583s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:417s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:280s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:511s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:388s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:413s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:457s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:415s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:456s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:496s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:508s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:601s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:437s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:505s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:525s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:486s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:484s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:416s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:428s
fi-snb-2520m     total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:398s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:473s

ede4b1ac40b2c32511532ddb6849b11c0183020e drm-tip: 2018y-02m-08d-07h-43m-06s UTC integration manifest
918da7b9c87b drm/i915: Handle RC6 counter wrap

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7939/issues.html
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✓ Fi.CI.IGT: success for drm/i915: Handle RC6 counter wrap (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Handle RC6 counter wrap (rev3)
URL   : https://patchwork.freedesktop.org/series/37824/
State : success

== Summary ==

Test kms_cursor_legacy:
        Subgroup cursor-vs-flip-legacy:
                pass       -> FAIL       (shard-apl) fdo#103355
Test gem_eio:
        Subgroup in-flight-contexts:
                pass       -> FAIL       (shard-hsw) fdo#104676
Test drv_suspend:
        Subgroup debugfs-reader:
                pass       -> SKIP       (shard-snb) fdo#102365
Test kms_flip:
        Subgroup flip-vs-panning-vs-hang-interruptible:
                dmesg-warn -> PASS       (shard-snb) fdo#103821
        Subgroup plain-flip-fb-recreate-interruptible:
                fail       -> PASS       (shard-hsw) fdo#100368
Test kms_plane:
        Subgroup plane-panning-bottom-right-suspend-pipe-b-planes:
                pass       -> SKIP       (shard-hsw) fdo#103540
Test testdisplay:
                pass       -> DMESG-WARN (shard-apl) fdo#104727
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-offscren-pri-indfb-draw-blt:
                pass       -> FAIL       (shard-apl) fdo#101623
        Subgroup fbc-tilingchange:
                pass       -> FAIL       (shard-apl) fdo#103167

fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#104727 https://bugs.freedesktop.org/show_bug.cgi?id=104727
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167

shard-apl        total:3354 pass:1735 dwarn:2   dfail:0   fail:22  skip:1594 time:12408s
shard-hsw        total:3444 pass:1758 dwarn:1   dfail:0   fail:12  skip:1672 time:11835s
shard-snb        total:3444 pass:1349 dwarn:1   dfail:0   fail:10  skip:2084 time:6533s
Blacklisted hosts:
shard-kbl        total:3380 pass:1871 dwarn:8   dfail:3   fail:19  skip:1478 time:9415s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7939/shards.html
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✓ Fi.CI.BAT: success for drm/i915: Handle RC6 counter wrap (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Handle RC6 counter wrap (rev4)
URL   : https://patchwork.freedesktop.org/series/37824/
State : success

== Summary ==

Series 37824v4 drm/i915: Handle RC6 counter wrap
https://patchwork.freedesktop.org/api/1.0/series/37824/revisions/4/mbox/

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> INCOMPLETE (fi-bdw-5557u) fdo#104944

fdo#104944 https://bugs.freedesktop.org/show_bug.cgi?id=104944

fi-bdw-5557u     total:244  pass:226  dwarn:0   dfail:0   fail:0   skip:17 
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:422s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:375s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:492s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:286s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:485s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:484s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:466s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:455s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:569s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:575s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:414s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:285s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:509s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:388s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:412s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:461s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:419s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:456s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:497s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:454s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:503s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:601s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:428s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:506s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:523s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:488s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:481s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:412s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:427s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:528s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:393s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:471s

ead13f6504ef40dfb905830e57360f461f6803c3 drm-tip: 2018y-02m-08d-13h-43m-51s UTC integration manifest
58fbc88124eb drm/i915: Handle RC6 counter wrap

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7955/issues.html
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✓ Fi.CI.BAT: success for drm/i915: Handle RC6 counter wrap (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Handle RC6 counter wrap (rev5)
URL   : https://patchwork.freedesktop.org/series/37824/
State : success

== Summary ==

Series 37824v5 drm/i915: Handle RC6 counter wrap
https://patchwork.freedesktop.org/api/1.0/series/37824/revisions/5/mbox/

Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> INCOMPLETE (fi-bdw-5557u) fdo#104162
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> INCOMPLETE (fi-hsw-4770) fdo#103375
        Subgroup suspend-read-crc-pipe-c:
                pass       -> DMESG-WARN (fi-cnl-y3) fdo#104951

fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951

fi-bdw-5557u     total:109  pass:105  dwarn:0   dfail:0   fail:0   skip:3  
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:422s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:381s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:488s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:286s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:482s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:488s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:471s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:456s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:558s
fi-cnl-y3        total:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  time:571s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:416s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:285s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:510s
fi-hsw-4770      total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:413s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:458s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:413s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:457s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:493s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:460s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:499s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:596s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:424s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:506s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:525s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:482s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:480s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:414s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:430s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:529s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:399s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:468s

ead13f6504ef40dfb905830e57360f461f6803c3 drm-tip: 2018y-02m-08d-13h-43m-51s UTC integration manifest
a540ad853d1e drm/i915: Handle RC6 counter wrap

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7956/issues.html
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Re: ✓ Fi.CI.BAT: success for drm/i915: Handle RC6 counter wrap (rev5)

[Tvrtko Ursulin]

On 08/02/2018 16:23, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Handle RC6 counter wrap (rev5)
> URL   : https://patchwork.freedesktop.org/series/37824/
> State : success
> 
> == Summary ==
> 
> Series 37824v5 drm/i915: Handle RC6 counter wrap
> https://patchwork.freedesktop.org/api/1.0/series/37824/revisions/5/mbox/
> 
> Test gem_exec_suspend:
>          Subgroup basic-s4-devices:
>                  pass       -> INCOMPLETE (fi-bdw-5557u) fdo#104162
> Test kms_pipe_crc_basic:
>          Subgroup suspend-read-crc-pipe-a:
>                  pass       -> INCOMPLETE (fi-hsw-4770) fdo#103375
>          Subgroup suspend-read-crc-pipe-c:
>                  pass       -> DMESG-WARN (fi-cnl-y3) fdo#104951
> 
> fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162
> fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
> fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
> 
> fi-bdw-5557u     total:109  pass:105  dwarn:0   dfail:0   fail:0   skip:3
> fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:422s
> fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:381s
> fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:488s
> fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:286s
> fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:482s
> fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:488s
> fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:471s
> fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:456s
> fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:558s
> fi-cnl-y3        total:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  time:571s
> fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:416s
> fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:285s
> fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:510s
> fi-hsw-4770      total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:23
> fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:413s
> fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:458s
> fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:413s
> fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:457s
> fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:493s
> fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:460s
> fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:499s
> fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:596s
> fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:424s
> fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:506s
> fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:525s
> fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:482s
> fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:480s
> fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:414s
> fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:430s
> fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:529s
> fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:399s
> Blacklisted hosts:
> fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:468s
> 
> ead13f6504ef40dfb905830e57360f461f6803c3 drm-tip: 2018y-02m-08d-13h-43m-51s UTC integration manifest
> a540ad853d1e drm/i915: Handle RC6 counter wrap

Pushed, thanks for the review!

Regards,

Tvrtko
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✓ Fi.CI.IGT: success for drm/i915: Handle RC6 counter wrap (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Handle RC6 counter wrap (rev5)
URL   : https://patchwork.freedesktop.org/series/37824/
State : success

== Summary ==

Test gem_eio:
        Subgroup in-flight-contexts:
                pass       -> FAIL       (shard-hsw) fdo#104676 +1
Test kms_cursor_crc:
        Subgroup cursor-64x64-suspend:
                pass       -> FAIL       (shard-snb) fdo#102365 +1
Test kms_cursor_legacy:
        Subgroup cursor-vs-flip-legacy:
                fail       -> PASS       (shard-apl) fdo#103355
Test gem_exec_suspend:
        Subgroup basic-s4:
                fail       -> SKIP       (shard-snb) fdo#103375

fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-apl        total:3354 pass:1738 dwarn:1   dfail:0   fail:20  skip:1594 time:12346s
shard-hsw        total:3444 pass:1760 dwarn:1   dfail:0   fail:11  skip:1671 time:11820s
shard-snb        total:3444 pass:1350 dwarn:1   dfail:0   fail:10  skip:2083 time:6528s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7956/shards.html
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