* [PATCH 0/3] CNL port refactoring
@ 2018-02-15 9:56 Mahesh Kumar
2018-02-15 9:56 ` [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address Mahesh Kumar
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Mahesh Kumar @ 2018-02-15 9:56 UTC (permalink / raw)
To: intel-gfx
This series fixes CNL PORT_TX_DW5/7_LNO_D register address.
This series also introduces macros to get register address of
CNL_PORT_TX registers instead of defining for each DW instance.
Mahesh Kumar (3):
drm/i915/cnl: Fix PORT_TX_DW5/7 register address
drm/i915/cnl; Add macro to get PORT_TX register
drm/i915/cnl: Replace PORT_TX register macros with new ones
drivers/gpu/drm/i915/i915_reg.h | 135 ++++++++++++----------------------------
1 file changed, 39 insertions(+), 96 deletions(-)
--
2.14.1
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^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address 2018-02-15 9:56 [PATCH 0/3] CNL port refactoring Mahesh Kumar @ 2018-02-15 9:56 ` Mahesh Kumar 2018-02-15 14:02 ` Jani Nikula 2018-02-15 9:56 ` [PATCH 2/3] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar ` (3 subsequent siblings) 4 siblings, 1 reply; 9+ messages in thread From: Mahesh Kumar @ 2018-02-15 9:56 UTC (permalink / raw) To: intel-gfx Register Address for CNL_PORT_DW5_LN0_D is 0x162E54, but current code is defining it as 0x162ED4. Similarly for CNL_PORT_DW7_LN0_D register address is defined 0x162EDC instead of 0x162E5C, fix it. Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f6afa5e5e7c1..1412abcb27d4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2034,7 +2034,7 @@ enum i915_power_well_id { #define _CNL_PORT_TX_DW5_LN0_AE 0x162454 #define _CNL_PORT_TX_DW5_LN0_B 0x162654 #define _CNL_PORT_TX_DW5_LN0_C 0x162C54 -#define _CNL_PORT_TX_DW5_LN0_D 0x162ED4 +#define _CNL_PORT_TX_DW5_LN0_D 0x162E54 #define _CNL_PORT_TX_DW5_LN0_F 0x162854 #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \ _CNL_PORT_TX_DW5_GRP_AE, \ @@ -2065,7 +2065,7 @@ enum i915_power_well_id { #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C #define _CNL_PORT_TX_DW7_LN0_B 0x16265C #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C -#define _CNL_PORT_TX_DW7_LN0_D 0x162EDC +#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C #define _CNL_PORT_TX_DW7_LN0_F 0x16285C #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \ _CNL_PORT_TX_DW7_GRP_AE, \ -- 2.14.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address 2018-02-15 9:56 ` [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address Mahesh Kumar @ 2018-02-15 14:02 ` Jani Nikula 2018-02-15 23:43 ` Rodrigo Vivi 0 siblings, 1 reply; 9+ messages in thread From: Jani Nikula @ 2018-02-15 14:02 UTC (permalink / raw) To: Mahesh Kumar, intel-gfx On Thu, 15 Feb 2018, Mahesh Kumar <mahesh1.kumar@intel.com> wrote: > Register Address for CNL_PORT_DW5_LN0_D is 0x162E54, but current code is > defining it as 0x162ED4. Similarly for CNL_PORT_DW7_LN0_D register address > is defined 0x162EDC instead of 0x162E5C, fix it. Which commit introduced the bug? Please add Fixes: annotation for it. We want this backported. BR, Jani. > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index f6afa5e5e7c1..1412abcb27d4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2034,7 +2034,7 @@ enum i915_power_well_id { > #define _CNL_PORT_TX_DW5_LN0_AE 0x162454 > #define _CNL_PORT_TX_DW5_LN0_B 0x162654 > #define _CNL_PORT_TX_DW5_LN0_C 0x162C54 > -#define _CNL_PORT_TX_DW5_LN0_D 0x162ED4 > +#define _CNL_PORT_TX_DW5_LN0_D 0x162E54 > #define _CNL_PORT_TX_DW5_LN0_F 0x162854 > #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \ > _CNL_PORT_TX_DW5_GRP_AE, \ > @@ -2065,7 +2065,7 @@ enum i915_power_well_id { > #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C > #define _CNL_PORT_TX_DW7_LN0_B 0x16265C > #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C > -#define _CNL_PORT_TX_DW7_LN0_D 0x162EDC > +#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C > #define _CNL_PORT_TX_DW7_LN0_F 0x16285C > #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \ > _CNL_PORT_TX_DW7_GRP_AE, \ -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address 2018-02-15 14:02 ` Jani Nikula @ 2018-02-15 23:43 ` Rodrigo Vivi 2018-02-16 17:57 ` Rodrigo Vivi 0 siblings, 1 reply; 9+ messages in thread From: Rodrigo Vivi @ 2018-02-15 23:43 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Thu, Feb 15, 2018 at 04:02:46PM +0200, Jani Nikula wrote: > On Thu, 15 Feb 2018, Mahesh Kumar <mahesh1.kumar@intel.com> wrote: > > Register Address for CNL_PORT_DW5_LN0_D is 0x162E54, but current code is > > defining it as 0x162ED4. Similarly for CNL_PORT_DW7_LN0_D register address > > is defined 0x162EDC instead of 0x162E5C, fix it. > > Which commit introduced the bug? Please add Fixes: annotation for it. We > want this backported. > > BR, > Jani. > > > > Fixes: 04416108ccea ("drm/i915/cnl: Add registers related to voltage swing sequences.") Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index f6afa5e5e7c1..1412abcb27d4 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -2034,7 +2034,7 @@ enum i915_power_well_id { > > #define _CNL_PORT_TX_DW5_LN0_AE 0x162454 > > #define _CNL_PORT_TX_DW5_LN0_B 0x162654 > > #define _CNL_PORT_TX_DW5_LN0_C 0x162C54 > > -#define _CNL_PORT_TX_DW5_LN0_D 0x162ED4 > > +#define _CNL_PORT_TX_DW5_LN0_D 0x162E54 > > #define _CNL_PORT_TX_DW5_LN0_F 0x162854 > > #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \ > > _CNL_PORT_TX_DW5_GRP_AE, \ > > @@ -2065,7 +2065,7 @@ enum i915_power_well_id { > > #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C > > #define _CNL_PORT_TX_DW7_LN0_B 0x16265C > > #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C > > -#define _CNL_PORT_TX_DW7_LN0_D 0x162EDC > > +#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C > > #define _CNL_PORT_TX_DW7_LN0_F 0x16285C > > #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \ > > _CNL_PORT_TX_DW7_GRP_AE, \ > > -- > Jani Nikula, Intel Open Source Technology Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address 2018-02-15 23:43 ` Rodrigo Vivi @ 2018-02-16 17:57 ` Rodrigo Vivi 0 siblings, 0 replies; 9+ messages in thread From: Rodrigo Vivi @ 2018-02-16 17:57 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Thu, Feb 15, 2018 at 03:43:46PM -0800, Rodrigo Vivi wrote: > On Thu, Feb 15, 2018 at 04:02:46PM +0200, Jani Nikula wrote: > > On Thu, 15 Feb 2018, Mahesh Kumar <mahesh1.kumar@intel.com> wrote: > > > Register Address for CNL_PORT_DW5_LN0_D is 0x162E54, but current code is > > > defining it as 0x162ED4. Similarly for CNL_PORT_DW7_LN0_D register address > > > is defined 0x162EDC instead of 0x162E5C, fix it. > > > > Which commit introduced the bug? Please add Fixes: annotation for it. We > > want this backported. > > > > BR, > > Jani. > > > > > > > > > Fixes: 04416108ccea ("drm/i915/cnl: Add registers related to voltage swing sequences.") > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> btw I merged this patch yesterday. Thanks for finding and fixing it. > > > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index f6afa5e5e7c1..1412abcb27d4 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -2034,7 +2034,7 @@ enum i915_power_well_id { > > > #define _CNL_PORT_TX_DW5_LN0_AE 0x162454 > > > #define _CNL_PORT_TX_DW5_LN0_B 0x162654 > > > #define _CNL_PORT_TX_DW5_LN0_C 0x162C54 > > > -#define _CNL_PORT_TX_DW5_LN0_D 0x162ED4 > > > +#define _CNL_PORT_TX_DW5_LN0_D 0x162E54 > > > #define _CNL_PORT_TX_DW5_LN0_F 0x162854 > > > #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \ > > > _CNL_PORT_TX_DW5_GRP_AE, \ > > > @@ -2065,7 +2065,7 @@ enum i915_power_well_id { > > > #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C > > > #define _CNL_PORT_TX_DW7_LN0_B 0x16265C > > > #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C > > > -#define _CNL_PORT_TX_DW7_LN0_D 0x162EDC > > > +#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C > > > #define _CNL_PORT_TX_DW7_LN0_F 0x16285C > > > #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \ > > > _CNL_PORT_TX_DW7_GRP_AE, \ > > > > -- > > Jani Nikula, Intel Open Source Technology Center > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] drm/i915/cnl; Add macro to get PORT_TX register 2018-02-15 9:56 [PATCH 0/3] CNL port refactoring Mahesh Kumar 2018-02-15 9:56 ` [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address Mahesh Kumar @ 2018-02-15 9:56 ` Mahesh Kumar 2018-02-15 9:56 ` [PATCH 3/3] drm/i915/cnl: Replace PORT_TX register macros with new ones Mahesh Kumar ` (2 subsequent siblings) 4 siblings, 0 replies; 9+ messages in thread From: Mahesh Kumar @ 2018-02-15 9:56 UTC (permalink / raw) To: intel-gfx This patch creates a new macro to get PORT_TX register for any given DW. This will remove the need of defining register address for each port & DW. Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1412abcb27d4..ef339f21f2a3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1961,6 +1961,34 @@ enum i915_power_well_id { _CNL_PORT_PCS_DW1_LN0_F) #define COMMON_KEEPER_EN (1 << 26) +/* CNL Port TX registers */ +#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340 +#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0 +#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40 +#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0 +#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40 +#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440 +#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640 +#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40 +#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40 +#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840 +#define CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \ + _CNL_PORT_TX_AE_GRP_OFFSET, \ + _CNL_PORT_TX_B_GRP_OFFSET, \ + _CNL_PORT_TX_B_GRP_OFFSET, \ + _CNL_PORT_TX_D_GRP_OFFSET, \ + _CNL_PORT_TX_AE_GRP_OFFSET, \ + _CNL_PORT_TX_F_GRP_OFFSET) + \ + 4*(dw)) +#define CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \ + _CNL_PORT_TX_AE_LN0_OFFSET, \ + _CNL_PORT_TX_B_LN0_OFFSET, \ + _CNL_PORT_TX_B_LN0_OFFSET, \ + _CNL_PORT_TX_D_LN0_OFFSET, \ + _CNL_PORT_TX_AE_LN0_OFFSET, \ + _CNL_PORT_TX_F_LN0_OFFSET) + \ + 4*(dw)) + #define _CNL_PORT_TX_DW2_GRP_AE 0x162348 #define _CNL_PORT_TX_DW2_GRP_B 0x1623C8 #define _CNL_PORT_TX_DW2_GRP_C 0x162B48 -- 2.14.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] drm/i915/cnl: Replace PORT_TX register macros with new ones 2018-02-15 9:56 [PATCH 0/3] CNL port refactoring Mahesh Kumar 2018-02-15 9:56 ` [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address Mahesh Kumar 2018-02-15 9:56 ` [PATCH 2/3] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar @ 2018-02-15 9:56 ` Mahesh Kumar 2018-02-15 10:01 ` ✗ Fi.CI.CHECKPATCH: warning for CNL port refactoring Patchwork 2018-02-15 10:16 ` ✓ Fi.CI.BAT: success " Patchwork 4 siblings, 0 replies; 9+ messages in thread From: Mahesh Kumar @ 2018-02-15 9:56 UTC (permalink / raw) To: intel-gfx This patch replaces CNL_PORT_TX register macros with new macros defined in previous patch. Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 107 +++++----------------------------------- 1 file changed, 11 insertions(+), 96 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ef339f21f2a3..25e81f4a5c7a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1989,30 +1989,8 @@ enum i915_power_well_id { _CNL_PORT_TX_F_LN0_OFFSET) + \ 4*(dw)) -#define _CNL_PORT_TX_DW2_GRP_AE 0x162348 -#define _CNL_PORT_TX_DW2_GRP_B 0x1623C8 -#define _CNL_PORT_TX_DW2_GRP_C 0x162B48 -#define _CNL_PORT_TX_DW2_GRP_D 0x162BC8 -#define _CNL_PORT_TX_DW2_GRP_F 0x162A48 -#define _CNL_PORT_TX_DW2_LN0_AE 0x162448 -#define _CNL_PORT_TX_DW2_LN0_B 0x162648 -#define _CNL_PORT_TX_DW2_LN0_C 0x162C48 -#define _CNL_PORT_TX_DW2_LN0_D 0x162E48 -#define _CNL_PORT_TX_DW2_LN0_F 0x162848 -#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW2_GRP_AE, \ - _CNL_PORT_TX_DW2_GRP_B, \ - _CNL_PORT_TX_DW2_GRP_C, \ - _CNL_PORT_TX_DW2_GRP_D, \ - _CNL_PORT_TX_DW2_GRP_AE, \ - _CNL_PORT_TX_DW2_GRP_F) -#define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW2_LN0_AE, \ - _CNL_PORT_TX_DW2_LN0_B, \ - _CNL_PORT_TX_DW2_LN0_C, \ - _CNL_PORT_TX_DW2_LN0_D, \ - _CNL_PORT_TX_DW2_LN0_AE, \ - _CNL_PORT_TX_DW2_LN0_F) +#define CNL_PORT_TX_DW2_GRP(port) _MMIO(CNL_PORT_TX_DW_GRP((port), 2)) +#define CNL_PORT_TX_DW2_LN0(port) _MMIO(CNL_PORT_TX_DW_LN0((port), 2)) #define SWING_SEL_UPPER(x) ((x >> 3) << 15) #define SWING_SEL_UPPER_MASK (1 << 15) #define SWING_SEL_LOWER(x) ((x & 0x7) << 11) @@ -2020,32 +1998,13 @@ enum i915_power_well_id { #define RCOMP_SCALAR(x) ((x) << 0) #define RCOMP_SCALAR_MASK (0xFF << 0) -#define _CNL_PORT_TX_DW4_GRP_AE 0x162350 -#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0 -#define _CNL_PORT_TX_DW4_GRP_C 0x162B50 -#define _CNL_PORT_TX_DW4_GRP_D 0x162BD0 -#define _CNL_PORT_TX_DW4_GRP_F 0x162A50 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 -#define _CNL_PORT_TX_DW4_LN0_B 0x162650 -#define _CNL_PORT_TX_DW4_LN0_C 0x162C50 -#define _CNL_PORT_TX_DW4_LN0_D 0x162E50 -#define _CNL_PORT_TX_DW4_LN0_F 0x162850 -#define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW4_GRP_AE, \ - _CNL_PORT_TX_DW4_GRP_B, \ - _CNL_PORT_TX_DW4_GRP_C, \ - _CNL_PORT_TX_DW4_GRP_D, \ - _CNL_PORT_TX_DW4_GRP_AE, \ - _CNL_PORT_TX_DW4_GRP_F) -#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \ - _CNL_PORT_TX_DW4_LN0_AE, \ - _CNL_PORT_TX_DW4_LN1_AE, \ - _CNL_PORT_TX_DW4_LN0_B, \ - _CNL_PORT_TX_DW4_LN0_C, \ - _CNL_PORT_TX_DW4_LN0_D, \ - _CNL_PORT_TX_DW4_LN0_AE, \ - _CNL_PORT_TX_DW4_LN0_F) +#define CNL_PORT_TX_DW4_GRP(port) _MMIO(CNL_PORT_TX_DW_GRP((port), 4)) +#define CNL_PORT_TX_DW4_LN0(port) _MMIO(CNL_PORT_TX_DW_LN0((port), 4)) +#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(CNL_PORT_TX_DW_LN0((port), 4) + \ + (ln * (_CNL_PORT_TX_DW4_LN1_AE - \ + _CNL_PORT_TX_DW4_LN0_AE))) #define LOADGEN_SELECT (1 << 31) #define POST_CURSOR_1(x) ((x) << 12) #define POST_CURSOR_1_MASK (0x3F << 12) @@ -2054,30 +2013,8 @@ enum i915_power_well_id { #define CURSOR_COEFF(x) ((x) << 0) #define CURSOR_COEFF_MASK (0x3F << 0) -#define _CNL_PORT_TX_DW5_GRP_AE 0x162354 -#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4 -#define _CNL_PORT_TX_DW5_GRP_C 0x162B54 -#define _CNL_PORT_TX_DW5_GRP_D 0x162BD4 -#define _CNL_PORT_TX_DW5_GRP_F 0x162A54 -#define _CNL_PORT_TX_DW5_LN0_AE 0x162454 -#define _CNL_PORT_TX_DW5_LN0_B 0x162654 -#define _CNL_PORT_TX_DW5_LN0_C 0x162C54 -#define _CNL_PORT_TX_DW5_LN0_D 0x162E54 -#define _CNL_PORT_TX_DW5_LN0_F 0x162854 -#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW5_GRP_AE, \ - _CNL_PORT_TX_DW5_GRP_B, \ - _CNL_PORT_TX_DW5_GRP_C, \ - _CNL_PORT_TX_DW5_GRP_D, \ - _CNL_PORT_TX_DW5_GRP_AE, \ - _CNL_PORT_TX_DW5_GRP_F) -#define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW5_LN0_AE, \ - _CNL_PORT_TX_DW5_LN0_B, \ - _CNL_PORT_TX_DW5_LN0_C, \ - _CNL_PORT_TX_DW5_LN0_D, \ - _CNL_PORT_TX_DW5_LN0_AE, \ - _CNL_PORT_TX_DW5_LN0_F) +#define CNL_PORT_TX_DW5_GRP(port) _MMIO(CNL_PORT_TX_DW_GRP((port), 5)) +#define CNL_PORT_TX_DW5_LN0(port) _MMIO(CNL_PORT_TX_DW_LN0((port), 5)) #define TX_TRAINING_EN (1 << 31) #define TAP3_DISABLE (1 << 29) #define SCALING_MODE_SEL(x) ((x) << 18) @@ -2085,30 +2022,8 @@ enum i915_power_well_id { #define RTERM_SELECT(x) ((x) << 3) #define RTERM_SELECT_MASK (0x7 << 3) -#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C -#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC -#define _CNL_PORT_TX_DW7_GRP_C 0x162B5C -#define _CNL_PORT_TX_DW7_GRP_D 0x162BDC -#define _CNL_PORT_TX_DW7_GRP_F 0x162A5C -#define _CNL_PORT_TX_DW7_LN0_AE 0x16245C -#define _CNL_PORT_TX_DW7_LN0_B 0x16265C -#define _CNL_PORT_TX_DW7_LN0_C 0x162C5C -#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C -#define _CNL_PORT_TX_DW7_LN0_F 0x16285C -#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW7_GRP_AE, \ - _CNL_PORT_TX_DW7_GRP_B, \ - _CNL_PORT_TX_DW7_GRP_C, \ - _CNL_PORT_TX_DW7_GRP_D, \ - _CNL_PORT_TX_DW7_GRP_AE, \ - _CNL_PORT_TX_DW7_GRP_F) -#define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW7_LN0_AE, \ - _CNL_PORT_TX_DW7_LN0_B, \ - _CNL_PORT_TX_DW7_LN0_C, \ - _CNL_PORT_TX_DW7_LN0_D, \ - _CNL_PORT_TX_DW7_LN0_AE, \ - _CNL_PORT_TX_DW7_LN0_F) +#define CNL_PORT_TX_DW7_GRP(port) _MMIO(CNL_PORT_TX_DW_GRP((port), 7)) +#define CNL_PORT_TX_DW7_LN0(port) _MMIO(CNL_PORT_TX_DW_LN0((port), 7)) #define N_SCALAR(x) ((x) << 24) #define N_SCALAR_MASK (0x7F << 24) -- 2.14.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for CNL port refactoring 2018-02-15 9:56 [PATCH 0/3] CNL port refactoring Mahesh Kumar ` (2 preceding siblings ...) 2018-02-15 9:56 ` [PATCH 3/3] drm/i915/cnl: Replace PORT_TX register macros with new ones Mahesh Kumar @ 2018-02-15 10:01 ` Patchwork 2018-02-15 10:16 ` ✓ Fi.CI.BAT: success " Patchwork 4 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2018-02-15 10:01 UTC (permalink / raw) To: Mahesh Kumar; +Cc: intel-gfx == Series Details == Series: CNL port refactoring URL : https://patchwork.freedesktop.org/series/38334/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7464b147c8e2 drm/i915/cnl: Fix PORT_TX_DW5/7 register address 55e9964aae48 drm/i915/cnl; Add macro to get PORT_TX register -:37: CHECK: spaces preferred around that '*' (ctx:VxV) #37: FILE: drivers/gpu/drm/i915/i915_reg.h:1982: + 4*(dw)) ^ -:45: CHECK: spaces preferred around that '*' (ctx:VxV) #45: FILE: drivers/gpu/drm/i915/i915_reg.h:1990: + 4*(dw)) ^ total: 0 errors, 0 warnings, 2 checks, 34 lines checked 29ca14f7c194 drm/i915/cnl: Replace PORT_TX register macros with new ones _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for CNL port refactoring 2018-02-15 9:56 [PATCH 0/3] CNL port refactoring Mahesh Kumar ` (3 preceding siblings ...) 2018-02-15 10:01 ` ✗ Fi.CI.CHECKPATCH: warning for CNL port refactoring Patchwork @ 2018-02-15 10:16 ` Patchwork 4 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2018-02-15 10:16 UTC (permalink / raw) To: Mahesh Kumar; +Cc: intel-gfx == Series Details == Series: CNL port refactoring URL : https://patchwork.freedesktop.org/series/38334/ State : success == Summary == Series 38334v1 CNL port refactoring https://patchwork.freedesktop.org/api/1.0/series/38334/revisions/1/mbox/ Test debugfs_test: Subgroup read_all_entries: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:425s fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:422s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:375s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:483s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:286s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:481s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:487s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:468s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:458s fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:571s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:416s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:283s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:509s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:396s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:410s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:461s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:459s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:499s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:586s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:429s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:501s fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:525s fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:490s fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:474s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:417s fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:397s Blacklisted hosts: fi-glk-dsi total:118 pass:105 dwarn:0 dfail:0 fail:0 skip:12 fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:453s bd16af128e78b302b3034fa85626cd15dcf5f038 drm-tip: 2018y-02m-15d-00h-22m-40s UTC integration manifest 29ca14f7c194 drm/i915/cnl: Replace PORT_TX register macros with new ones 55e9964aae48 drm/i915/cnl; Add macro to get PORT_TX register 7464b147c8e2 drm/i915/cnl: Fix PORT_TX_DW5/7 register address == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8043/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-02-16 17:57 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-02-15 9:56 [PATCH 0/3] CNL port refactoring Mahesh Kumar 2018-02-15 9:56 ` [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address Mahesh Kumar 2018-02-15 14:02 ` Jani Nikula 2018-02-15 23:43 ` Rodrigo Vivi 2018-02-16 17:57 ` Rodrigo Vivi 2018-02-15 9:56 ` [PATCH 2/3] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar 2018-02-15 9:56 ` [PATCH 3/3] drm/i915/cnl: Replace PORT_TX register macros with new ones Mahesh Kumar 2018-02-15 10:01 ` ✗ Fi.CI.CHECKPATCH: warning for CNL port refactoring Patchwork 2018-02-15 10:16 ` ✓ Fi.CI.BAT: success " Patchwork
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