[RFC v4 00/31] Implicit dev_priv removal and GT compartmentalization

[RFC v4 00/31] Implicit dev_priv removal and GT compartmentalization

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Most of v3 review feedback plus more of:
""""
Also, while nosing around in the code I have spotted more opportunities to
compartmentalize, either using intel_gt, or some other object as appropriate.
"""

This time even smoke tested.

Tvrtko Ursulin (31):
  drm/i915: Convert intel_vgt_(de)balloon to uncore
  drm/i915: Introduce struct intel_gt as replacement for anonymous
    i915->gt
  drm/i915: Move intel_gt initialization to a separate file
  drm/i915: Store some backpointers in struct intel_gt
  drm/i915: Make i915_check_and_clear_faults take intel_gt
  drm/i915: Convert i915_gem_init_swizzling to intel_gt
  drm/i915: Convert init_unused_rings to intel_gt
  drm/i915: Convert gt workarounds to intel_gt
  drm/i915: Store backpointer to intel_gt in the engine
  drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt
  drm/i915: Convert i915_ppgtt_init_hw to intel_gt
  drm/i915: Consolidate some open coded mmio rmw
  drm/i915: Convert i915_gem_init_hw to intel_gt
  drm/i915: Move intel_engines_resume into common init
  drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw
  drm/i915: Compartmentalize i915_ggtt_probe_hw
  drm/i915: Compartmentalize i915_ggtt_init_hw
  drm/i915: Make ggtt invalidation work on ggtt
  drm/i915: Store intel_gt backpointer in vm
  drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings
  drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt
  drm/i915: Move i915_gem_chipset_flush to intel_gt
  drm/i915: Compartmentalize timeline_init/park/fini
  drm/i915: Compartmentalize i915_ggtt_cleanup_hw
  drm/i915: Compartmentalize i915_gem_init_ggtt
  drm/i915: Store ggtt pointer in intel_gt
  drm/i915: Compartmentalize ring buffer creation
  drm/i915: Save trip via top-level i915 in a few more places
  drm/i915: Make timelines gt centric
  drm/i915: Rename i915_timeline to intel_timeline and move under gt
  drm/i915: Eliminate dual personality of i915_scratch_offset

 drivers/gpu/drm/i915/Makefile                 |   3 +-
 drivers/gpu/drm/i915/Makefile.header-test     |   1 -
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |  10 +-
 .../gpu/drm/i915/gem/i915_gem_context_types.h |   4 +-
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |   5 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c    |   5 +-
 drivers/gpu/drm/i915/gem/i915_gem_phys.c      |   3 +-
 drivers/gpu/drm/i915/gem/i915_gem_pm.c        |   2 +-
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |   7 +-
 .../drm/i915/gem/selftests/i915_gem_context.c |   3 +-
 .../drm/i915/gem/selftests/i915_gem_mman.c    |   3 +-
 drivers/gpu/drm/i915/gt/intel_engine.h        |   4 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  33 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h  |   8 +-
 drivers/gpu/drm/i915/gt/intel_gt.c            | 195 ++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h            |  35 ++
 drivers/gpu/drm/i915/gt/intel_gt_types.h      |  61 +++
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  32 +-
 drivers/gpu/drm/i915/gt/intel_mocs.c          |  52 ++-
 drivers/gpu/drm/i915/gt/intel_mocs.h          |   3 +-
 drivers/gpu/drm/i915/gt/intel_reset.c         | 128 +-----
 drivers/gpu/drm/i915/gt/intel_reset.h         |   2 -
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c    |  68 ++--
 .../{i915_timeline.c => gt/intel_timeline.c}  | 204 +++++-----
 .../{i915_timeline.h => gt/intel_timeline.h}  |  71 ++--
 .../intel_timeline_types.h}                   |   8 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  12 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.h   |   6 +-
 drivers/gpu/drm/i915/gt/mock_engine.c         |  18 +-
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c  |  20 +-
 .../selftest_timeline.c}                      | 124 +++---
 .../gpu/drm/i915/gt/selftest_workarounds.c    |   7 +-
 .../i915/{ => gt}/selftests/mock_timeline.c   |   8 +-
 .../i915/{ => gt}/selftests/mock_timeline.h   |   6 +-
 drivers/gpu/drm/i915/i915_drv.c               |   9 +-
 drivers/gpu/drm/i915/i915_drv.h               |  52 +--
 drivers/gpu/drm/i915/i915_gem.c               | 227 +++++------
 drivers/gpu/drm/i915/i915_gem_fence_reg.c     |  37 ++
 drivers/gpu/drm/i915/i915_gem_fence_reg.h     |   3 +
 drivers/gpu/drm/i915/i915_gem_gtt.c           | 367 +++++++++++-------
 drivers/gpu/drm/i915/i915_gem_gtt.h           |  10 +-
 drivers/gpu/drm/i915/i915_gem_render_state.c  |   2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c         |   4 +-
 drivers/gpu/drm/i915/i915_request.c           |  16 +-
 drivers/gpu/drm/i915/i915_request.h           |   8 +-
 drivers/gpu/drm/i915/i915_vgpu.c              |  24 +-
 drivers/gpu/drm/i915/i915_vgpu.h              |   4 +-
 drivers/gpu/drm/i915/i915_vma.c               |   3 +-
 drivers/gpu/drm/i915/intel_wopcm.c            |  31 +-
 drivers/gpu/drm/i915/intel_wopcm.h            |   4 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |   2 +-
 .../drm/i915/selftests/i915_live_selftests.h  |   2 +-
 .../drm/i915/selftests/i915_mock_selftests.h  |   2 +-
 drivers/gpu/drm/i915/selftests/i915_request.c |  10 +-
 drivers/gpu/drm/i915/selftests/igt_spinner.c  |   7 +-
 drivers/gpu/drm/i915/selftests/igt_spinner.h  |   3 +
 .../gpu/drm/i915/selftests/mock_gem_device.c  |  11 +-
 57 files changed, 1143 insertions(+), 846 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_types.h
 rename drivers/gpu/drm/i915/{i915_timeline.c => gt/intel_timeline.c} (72%)
 rename drivers/gpu/drm/i915/{i915_timeline.h => gt/intel_timeline.h} (53%)
 rename drivers/gpu/drm/i915/{i915_timeline_types.h => gt/intel_timeline_types.h} (92%)
 rename drivers/gpu/drm/i915/{selftests/i915_timeline.c => gt/selftest_timeline.c} (86%)
 rename drivers/gpu/drm/i915/{ => gt}/selftests/mock_timeline.c (70%)
 rename drivers/gpu/drm/i915/{ => gt}/selftests/mock_timeline.h (53%)

-- 
2.20.1

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[RFC 01/31] drm/i915: Convert intel_vgt_(de)balloon to uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Furthermore these calls really operate on ggtt so it logically makes sense
if they take it as parameter.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c |  4 ++--
 drivers/gpu/drm/i915/i915_vgpu.c    | 24 ++++++++++++++----------
 drivers/gpu/drm/i915/i915_vgpu.h    |  4 ++--
 3 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7be72388b052..90d9669ff313 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2859,7 +2859,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
 			       intel_wopcm_guc_size(&dev_priv->wopcm));
 
-	ret = intel_vgt_balloon(dev_priv);
+	ret = intel_vgt_balloon(ggtt);
 	if (ret)
 		return ret;
 
@@ -2930,7 +2930,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
 	ggtt_release_guc_top(ggtt);
 
 	if (drm_mm_initialized(&ggtt->vm.mm)) {
-		intel_vgt_deballoon(dev_priv);
+		intel_vgt_deballoon(ggtt);
 		i915_address_space_fini(&ggtt->vm);
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 94d3992b599d..41ed9a3f52b4 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -117,17 +117,17 @@ static void vgt_deballoon_space(struct i915_ggtt *ggtt,
  * This function is called to deallocate the ballooned-out graphic memory, when
  * driver is unloaded or when ballooning fails.
  */
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
+void intel_vgt_deballoon(struct i915_ggtt *ggtt)
 {
 	int i;
 
-	if (!intel_vgpu_active(dev_priv))
+	if (!intel_vgpu_active(ggtt->vm.i915))
 		return;
 
 	DRM_DEBUG("VGT deballoon.\n");
 
 	for (i = 0; i < 4; i++)
-		vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
+		vgt_deballoon_space(ggtt, &bl_info.space[i]);
 }
 
 static int vgt_balloon_space(struct i915_ggtt *ggtt,
@@ -195,22 +195,26 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt,
  * Returns:
  * zero on success, non-zero if configuration invalid or ballooning failed
  */
-int intel_vgt_balloon(struct drm_i915_private *dev_priv)
+int intel_vgt_balloon(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
+	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
 	unsigned long ggtt_end = ggtt->vm.total;
 
 	unsigned long mappable_base, mappable_size, mappable_end;
 	unsigned long unmappable_base, unmappable_size, unmappable_end;
 	int ret;
 
-	if (!intel_vgpu_active(dev_priv))
+	if (!intel_vgpu_active(ggtt->vm.i915))
 		return 0;
 
-	mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
-	mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
-	unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
-	unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
+	mappable_base =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
+	mappable_size =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
+	unmappable_base =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base));
+	unmappable_size =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size));
 
 	mappable_end = mappable_base + mappable_size;
 	unmappable_end = unmappable_base + unmappable_size;
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index ebe1b7bced98..e918f418503f 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -42,7 +42,7 @@ intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
 	return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
 }
 
-int intel_vgt_balloon(struct drm_i915_private *dev_priv);
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
+int intel_vgt_balloon(struct i915_ggtt *ggtt);
+void intel_vgt_deballoon(struct i915_ggtt *ggtt);
 
 #endif /* _I915_VGPU_H_ */
-- 
2.20.1

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[RFC 02/31] drm/i915: Introduce struct intel_gt as replacement for anonymous i915->gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

We have long been slighlty annoyed by the anonymous i915->gt.

Promote it to a separate structure and give it its own header.

This is a first step towards cleaning up the separation between i915 and gt.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h | 53 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h          | 34 +--------------
 2 files changed, 55 insertions(+), 32 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_types.h

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
new file mode 100644
index 000000000000..dcdb18e0dd84
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -0,0 +1,53 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __INTEL_GT_TYPES__
+#define __INTEL_GT_TYPES__
+
+#include <linux/ktime.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/notifier.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include "i915_vma.h"
+#include "intel_wakeref.h"
+
+struct intel_gt {
+	struct i915_gt_timelines {
+		struct mutex mutex; /* protects list, tainted by GPU */
+		struct list_head active_list;
+
+		/* Pack multiple timelines' seqnos into the same page */
+		spinlock_t hwsp_lock;
+		struct list_head hwsp_free_list;
+	} timelines;
+
+	struct list_head active_rings;
+
+	struct intel_wakeref wakeref;
+
+	struct list_head closed_vma;
+	spinlock_t closed_lock; /* guards the list of closed_vma */
+
+	/**
+	 * Is the GPU currently considered idle, or busy executing
+	 * userspace requests? Whilst idle, we allow runtime power
+	 * management to power down the hardware and display clocks.
+	 * In order to reduce the effect on performance, there
+	 * is a slight delay before we do so.
+	 */
+	intel_wakeref_t awake;
+
+	struct blocking_notifier_head pm_notifications;
+
+	ktime_t last_init_time;
+
+	struct i915_vma *scratch;
+};
+
+#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3683ef6d4c28..e2c8813c9355 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -65,6 +65,7 @@
 
 #include "gt/intel_lrc.h"
 #include "gt/intel_engine.h"
+#include "gt/intel_gt_types.h"
 #include "gt/intel_workarounds.h"
 
 #include "intel_bios.h"
@@ -1870,38 +1871,7 @@ struct drm_i915_private {
 	} perf;
 
 	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
-	struct {
-		struct i915_gt_timelines {
-			struct mutex mutex; /* protects list, tainted by GPU */
-			struct list_head active_list;
-
-			/* Pack multiple timelines' seqnos into the same page */
-			spinlock_t hwsp_lock;
-			struct list_head hwsp_free_list;
-		} timelines;
-
-		struct list_head active_rings;
-
-		struct intel_wakeref wakeref;
-
-		struct list_head closed_vma;
-		spinlock_t closed_lock; /* guards the list of closed_vma */
-
-		/**
-		 * Is the GPU currently considered idle, or busy executing
-		 * userspace requests? Whilst idle, we allow runtime power
-		 * management to power down the hardware and display clocks.
-		 * In order to reduce the effect on performance, there
-		 * is a slight delay before we do so.
-		 */
-		intel_wakeref_t awake;
-
-		struct blocking_notifier_head pm_notifications;
-
-		ktime_t last_init_time;
-
-		struct i915_vma *scratch;
-	} gt;
+	struct intel_gt gt;
 
 	struct {
 		struct notifier_block pm_notifier;
-- 
2.20.1

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[RFC 03/31] drm/i915: Move intel_gt initialization to a separate file

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

As it will grow in a following patch make a new home for it.

v2:
 * Convert mock_gem_device as well. (Chris)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Makefile                    |  1 +
 drivers/gpu/drm/i915/gt/intel_gt.c               | 15 +++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h               | 14 ++++++++++++++
 drivers/gpu/drm/i915/i915_gem.c                  |  6 ++----
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  5 ++---
 5 files changed, 34 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c0a7b2994077..8df1bf2855d0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -73,6 +73,7 @@ gt-y += \
 	gt/intel_context.o \
 	gt/intel_engine_cs.o \
 	gt/intel_engine_pm.o \
+	gt/intel_gt.o \
 	gt/intel_gt_pm.o \
 	gt/intel_hangcheck.o \
 	gt/intel_lrc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
new file mode 100644
index 000000000000..807c5f746110
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_gt.h"
+
+void intel_gt_init(struct intel_gt *gt)
+{
+	INIT_LIST_HEAD(&gt->active_rings);
+	INIT_LIST_HEAD(&gt->closed_vma);
+
+	spin_lock_init(&gt->closed_lock);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
new file mode 100644
index 000000000000..d0b599dd6d0f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -0,0 +1,14 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __INTEL_GT__
+#define __INTEL_GT__
+
+#include "gt/intel_gt_types.h"
+
+void intel_gt_init(struct intel_gt *gt);
+
+#endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7232361973fd..d5897e13897b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -44,6 +44,7 @@
 #include "gem/i915_gem_pm.h"
 #include "gem/i915_gemfs.h"
 #include "gt/intel_engine_pm.h"
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_mocs.h"
 #include "gt/intel_reset.h"
@@ -1748,12 +1749,9 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
 {
 	int err;
 
+	intel_gt_init(&dev_priv->gt);
 	intel_gt_pm_init(dev_priv);
 
-	INIT_LIST_HEAD(&dev_priv->gt.active_rings);
-	INIT_LIST_HEAD(&dev_priv->gt.closed_vma);
-	spin_lock_init(&dev_priv->gt.closed_lock);
-
 	i915_gem_init__mm(dev_priv);
 	i915_gem_init__pm(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index b7f3fbb4ae89..fbcccc3cf85a 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -25,6 +25,7 @@
 #include <linux/pm_domain.h>
 #include <linux/pm_runtime.h>
 
+#include "gt/intel_gt.h"
 #include "gt/mock_engine.h"
 
 #include "mock_request.h"
@@ -201,9 +202,7 @@ struct drm_i915_private *mock_gem_device(void)
 
 	i915_timelines_init(i915);
 
-	INIT_LIST_HEAD(&i915->gt.active_rings);
-	INIT_LIST_HEAD(&i915->gt.closed_vma);
-	spin_lock_init(&i915->gt.closed_lock);
+	intel_gt_init(&i915->gt);
 
 	mutex_lock(&i915->drm.struct_mutex);
 
-- 
2.20.1

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[RFC 04/31] drm/i915: Store some backpointers in struct intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

We need an easy way to get back to i915 and uncore.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_gt.c               | 7 ++++++-
 drivers/gpu/drm/i915/gt/intel_gt.h               | 4 +++-
 drivers/gpu/drm/i915/gt/intel_gt_types.h         | 6 ++++++
 drivers/gpu/drm/i915/i915_gem.c                  | 2 +-
 drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
 5 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 807c5f746110..e8d72570a5bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -4,10 +4,15 @@
  * Copyright © 2019 Intel Corporation
  */
 
+#include "i915_drv.h"
+
 #include "intel_gt.h"
 
-void intel_gt_init(struct intel_gt *gt)
+void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915)
 {
+	gt->i915 = i915;
+	gt->uncore = &i915->uncore;
+
 	INIT_LIST_HEAD(&gt->active_rings);
 	INIT_LIST_HEAD(&gt->closed_vma);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index d0b599dd6d0f..f57ff3758f54 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -9,6 +9,8 @@
 
 #include "gt/intel_gt_types.h"
 
-void intel_gt_init(struct intel_gt *gt);
+struct drm_i915_private;
+
+void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915);
 
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index dcdb18e0dd84..d96df4f68741 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -17,7 +17,13 @@
 #include "i915_vma.h"
 #include "intel_wakeref.h"
 
+struct drm_i915_private;
+struct intel_uncore;
+
 struct intel_gt {
+	struct drm_i915_private *i915;
+	struct intel_uncore *uncore;
+
 	struct i915_gt_timelines {
 		struct mutex mutex; /* protects list, tainted by GPU */
 		struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d5897e13897b..7fdf252f9322 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1749,7 +1749,7 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
 {
 	int err;
 
-	intel_gt_init(&dev_priv->gt);
+	intel_gt_init(&dev_priv->gt, dev_priv);
 	intel_gt_pm_init(dev_priv);
 
 	i915_gem_init__mm(dev_priv);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index fbcccc3cf85a..413aaff1534b 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -202,7 +202,7 @@ struct drm_i915_private *mock_gem_device(void)
 
 	i915_timelines_init(i915);
 
-	intel_gt_init(&i915->gt);
+	intel_gt_init(&i915->gt, i915);
 
 	mutex_lock(&i915->drm.struct_mutex);
 
-- 
2.20.1

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[RFC 05/31] drm/i915: Make i915_check_and_clear_faults take intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing the conversion and elimination of implicit dev_priv.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |   4 +-
 drivers/gpu/drm/i915/gt/intel_gt.c        | 129 ++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h        |   5 +
 drivers/gpu/drm/i915/gt/intel_reset.c     | 126 +--------------------
 drivers/gpu/drm/i915/gt/intel_reset.h     |   2 -
 drivers/gpu/drm/i915/i915_drv.c           |   3 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c       |   6 +-
 7 files changed, 145 insertions(+), 130 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c0d986db5a75..35a9f754bcb9 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -28,6 +28,8 @@
 
 #include "i915_drv.h"
 
+#include "gt/intel_gt.h"
+
 #include "intel_engine.h"
 #include "intel_engine_pm.h"
 #include "intel_context.h"
@@ -453,7 +455,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
 
 	RUNTIME_INFO(i915)->num_engines = hweight32(mask);
 
-	i915_check_and_clear_faults(i915);
+	intel_gt_check_and_clear_faults(&i915->gt);
 
 	intel_setup_engine_capabilities(i915);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index e8d72570a5bf..d5ee3487e180 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -7,6 +7,7 @@
 #include "i915_drv.h"
 
 #include "intel_gt.h"
+#include "intel_uncore.h"
 
 void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915)
 {
@@ -18,3 +19,131 @@ void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915)
 
 	spin_lock_init(&gt->closed_lock);
 }
+
+static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
+{
+	intel_uncore_rmw(uncore, reg, 0, set);
+}
+
+static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
+{
+	intel_uncore_rmw(uncore, reg, clr, 0);
+}
+
+static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
+{
+	intel_uncore_rmw(uncore, reg, 0, 0);
+}
+
+static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
+{
+	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
+	GEN6_RING_FAULT_REG_POSTING_READ(engine);
+}
+
+void
+intel_gt_clear_error_registers(struct intel_gt *gt,
+			       intel_engine_mask_t engine_mask)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
+	u32 eir;
+
+	if (!IS_GEN(i915, 2))
+		clear_register(uncore, PGTBL_ER);
+
+	if (INTEL_GEN(i915) < 4)
+		clear_register(uncore, IPEIR(RENDER_RING_BASE));
+	else
+		clear_register(uncore, IPEIR_I965);
+
+	clear_register(uncore, EIR);
+	eir = intel_uncore_read(uncore, EIR);
+	if (eir) {
+		/*
+		 * some errors might have become stuck,
+		 * mask them.
+		 */
+		DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
+		rmw_set(uncore, EMR, eir);
+		intel_uncore_write(uncore, GEN2_IIR,
+				   I915_MASTER_ERROR_INTERRUPT);
+	}
+
+	if (INTEL_GEN(i915) >= 8) {
+		rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
+		intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
+	} else if (INTEL_GEN(i915) >= 6) {
+		struct intel_engine_cs *engine;
+		enum intel_engine_id id;
+
+		for_each_engine_masked(engine, i915, engine_mask, id)
+			gen8_clear_engine_error_register(engine);
+	}
+}
+
+static void gen6_check_faults(struct intel_gt *gt)
+{
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	u32 fault;
+
+	for_each_engine(engine, gt->i915, id) {
+		fault = GEN6_RING_FAULT_REG_READ(engine);
+		if (fault & RING_FAULT_VALID) {
+			DRM_DEBUG_DRIVER("Unexpected fault\n"
+					 "\tAddr: 0x%08lx\n"
+					 "\tAddress space: %s\n"
+					 "\tSource ID: %d\n"
+					 "\tType: %d\n",
+					 fault & PAGE_MASK,
+					 fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
+					 RING_FAULT_SRCID(fault),
+					 RING_FAULT_FAULT_TYPE(fault));
+		}
+	}
+}
+
+static void gen8_check_faults(struct intel_gt *gt)
+{
+	struct intel_uncore *uncore = gt->uncore;
+	u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
+
+	if (fault & RING_FAULT_VALID) {
+		u32 fault_data0, fault_data1;
+		u64 fault_addr;
+
+		fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0);
+		fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1);
+		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
+			     ((u64)fault_data0 << 12);
+
+		DRM_DEBUG_DRIVER("Unexpected fault\n"
+				 "\tAddr: 0x%08x_%08x\n"
+				 "\tAddress space: %s\n"
+				 "\tEngine ID: %d\n"
+				 "\tSource ID: %d\n"
+				 "\tType: %d\n",
+				 upper_32_bits(fault_addr),
+				 lower_32_bits(fault_addr),
+				 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+				 GEN8_RING_FAULT_ENGINE_ID(fault),
+				 RING_FAULT_SRCID(fault),
+				 RING_FAULT_FAULT_TYPE(fault));
+	}
+}
+
+void intel_gt_check_and_clear_faults(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+
+	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
+	if (INTEL_GEN(i915) >= 8)
+		gen8_check_faults(gt);
+	else if (INTEL_GEN(i915) >= 6)
+		gen6_check_faults(gt);
+	else
+		return;
+
+	intel_gt_clear_error_registers(gt, ALL_ENGINES);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index f57ff3758f54..d4f585151527 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -7,10 +7,15 @@
 #ifndef __INTEL_GT__
 #define __INTEL_GT__
 
+#include "gt/intel_engine_types.h"
 #include "gt/intel_gt_types.h"
 
 struct drm_i915_private;
 
 void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915);
 
+void intel_gt_check_and_clear_faults(struct intel_gt *gt);
+void intel_gt_clear_error_registers(struct intel_gt *gt,
+				    intel_engine_mask_t engine_mask);
+
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 41a294f5cc19..a837f30350d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -13,6 +13,7 @@
 #include "i915_gpu_error.h"
 #include "i915_irq.h"
 #include "intel_engine_pm.h"
+#include "intel_gt.h"
 #include "intel_gt_pm.h"
 #include "intel_reset.h"
 
@@ -24,16 +25,6 @@
 /* XXX How to handle concurrent GGTT updates using tiling registers? */
 #define RESET_UNDER_STOP_MACHINE 0
 
-static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
-{
-	intel_uncore_rmw(uncore, reg, 0, set);
-}
-
-static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
-{
-	intel_uncore_rmw(uncore, reg, clr, 0);
-}
-
 static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 {
 	intel_uncore_rmw_fw(uncore, reg, 0, set);
@@ -1156,119 +1147,6 @@ static void i915_reset_device(struct drm_i915_private *i915,
 		kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
 }
 
-static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
-{
-	intel_uncore_rmw(uncore, reg, 0, 0);
-}
-
-static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
-{
-	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
-	GEN6_RING_FAULT_REG_POSTING_READ(engine);
-}
-
-static void clear_error_registers(struct drm_i915_private *i915,
-				  intel_engine_mask_t engine_mask)
-{
-	struct intel_uncore *uncore = &i915->uncore;
-	u32 eir;
-
-	if (!IS_GEN(i915, 2))
-		clear_register(uncore, PGTBL_ER);
-
-	if (INTEL_GEN(i915) < 4)
-		clear_register(uncore, IPEIR(RENDER_RING_BASE));
-	else
-		clear_register(uncore, IPEIR_I965);
-
-	clear_register(uncore, EIR);
-	eir = intel_uncore_read(uncore, EIR);
-	if (eir) {
-		/*
-		 * some errors might have become stuck,
-		 * mask them.
-		 */
-		DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
-		rmw_set(uncore, EMR, eir);
-		intel_uncore_write(uncore, GEN2_IIR,
-				   I915_MASTER_ERROR_INTERRUPT);
-	}
-
-	if (INTEL_GEN(i915) >= 8) {
-		rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
-		intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
-	} else if (INTEL_GEN(i915) >= 6) {
-		struct intel_engine_cs *engine;
-		enum intel_engine_id id;
-
-		for_each_engine_masked(engine, i915, engine_mask, id)
-			gen8_clear_engine_error_register(engine);
-	}
-}
-
-static void gen6_check_faults(struct drm_i915_private *dev_priv)
-{
-	struct intel_engine_cs *engine;
-	enum intel_engine_id id;
-	u32 fault;
-
-	for_each_engine(engine, dev_priv, id) {
-		fault = GEN6_RING_FAULT_REG_READ(engine);
-		if (fault & RING_FAULT_VALID) {
-			DRM_DEBUG_DRIVER("Unexpected fault\n"
-					 "\tAddr: 0x%08lx\n"
-					 "\tAddress space: %s\n"
-					 "\tSource ID: %d\n"
-					 "\tType: %d\n",
-					 fault & PAGE_MASK,
-					 fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
-					 RING_FAULT_SRCID(fault),
-					 RING_FAULT_FAULT_TYPE(fault));
-		}
-	}
-}
-
-static void gen8_check_faults(struct drm_i915_private *dev_priv)
-{
-	u32 fault = I915_READ(GEN8_RING_FAULT_REG);
-
-	if (fault & RING_FAULT_VALID) {
-		u32 fault_data0, fault_data1;
-		u64 fault_addr;
-
-		fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
-		fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
-		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
-			     ((u64)fault_data0 << 12);
-
-		DRM_DEBUG_DRIVER("Unexpected fault\n"
-				 "\tAddr: 0x%08x_%08x\n"
-				 "\tAddress space: %s\n"
-				 "\tEngine ID: %d\n"
-				 "\tSource ID: %d\n"
-				 "\tType: %d\n",
-				 upper_32_bits(fault_addr),
-				 lower_32_bits(fault_addr),
-				 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
-				 GEN8_RING_FAULT_ENGINE_ID(fault),
-				 RING_FAULT_SRCID(fault),
-				 RING_FAULT_FAULT_TYPE(fault));
-	}
-}
-
-void i915_check_and_clear_faults(struct drm_i915_private *i915)
-{
-	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
-	if (INTEL_GEN(i915) >= 8)
-		gen8_check_faults(i915);
-	else if (INTEL_GEN(i915) >= 6)
-		gen6_check_faults(i915);
-	else
-		return;
-
-	clear_error_registers(i915, ALL_ENGINES);
-}
-
 /**
  * i915_handle_error - handle a gpu error
  * @i915: i915 device private
@@ -1317,7 +1195,7 @@ void i915_handle_error(struct drm_i915_private *i915,
 
 	if (flags & I915_ERROR_CAPTURE) {
 		i915_capture_error_state(i915, engine_mask, msg);
-		clear_error_registers(i915, engine_mask);
+		intel_gt_clear_error_registers(&i915->gt, engine_mask);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index 580ebdb59eca..03fba0ab3868 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -25,8 +25,6 @@ void i915_handle_error(struct drm_i915_private *i915,
 		       const char *fmt, ...);
 #define I915_ERROR_CAPTURE BIT(0)
 
-void i915_check_and_clear_faults(struct drm_i915_private *i915);
-
 void i915_reset(struct drm_i915_private *i915,
 		intel_engine_mask_t stalled_mask,
 		const char *reason);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 254f7b7df306..97155c5eb7e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
 
 #include "gem/i915_gem_context.h"
 #include "gem/i915_gem_ioctls.h"
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_reset.h"
 #include "gt/intel_workarounds.h"
@@ -2339,7 +2340,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	intel_uncore_resume_early(&dev_priv->uncore);
 
-	i915_check_and_clear_faults(dev_priv);
+	intel_gt_check_and_clear_faults(&dev_priv->gt);
 
 	if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
 		gen9_sanitize_dc_state(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 90d9669ff313..ac6ed459720e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -35,6 +35,8 @@
 
 #include <drm/i915_drm.h>
 
+#include "gt/intel_gt.h"
+
 #include "i915_drv.h"
 #include "i915_scatterlist.h"
 #include "i915_trace.h"
@@ -2311,7 +2313,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) < 6)
 		return;
 
-	i915_check_and_clear_faults(dev_priv);
+	intel_gt_check_and_clear_faults(&dev_priv->gt);
 
 	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
 
@@ -3620,7 +3622,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 	struct i915_vma *vma, *vn;
 
-	i915_check_and_clear_faults(dev_priv);
+	intel_gt_check_and_clear_faults(&dev_priv->gt);
 
 	mutex_lock(&ggtt->vm.mutex);
 
-- 
2.20.1

_______________________________________________
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[RFC 06/31] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Start using the newly introduced struct intel_gt to fuse together correct
logical init flow with uncore for more removal of implicit dev_priv in
mmio access.

v2:
 * Move code to i915_gem_fence_reg. (Chris)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c           |  4 +--
 drivers/gpu/drm/i915/i915_drv.h           |  1 -
 drivers/gpu/drm/i915/i915_gem.c           | 25 +--------------
 drivers/gpu/drm/i915/i915_gem_fence_reg.c | 37 +++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_gem_fence_reg.h |  3 ++
 5 files changed, 43 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 97155c5eb7e1..1df76f7c717e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2935,7 +2935,7 @@ static int intel_runtime_suspend(struct device *kdev)
 
 		intel_uc_resume(dev_priv);
 
-		i915_gem_init_swizzling(dev_priv);
+		intel_gt_init_swizzling(&dev_priv->gt);
 		i915_gem_restore_fences(dev_priv);
 
 		enable_rpm_wakeref_asserts(dev_priv);
@@ -3036,7 +3036,7 @@ static int intel_runtime_resume(struct device *kdev)
 	 * No point of rolling back things in case of an error, as the best
 	 * we can do is to hope that things will still work (and disable RPM).
 	 */
-	i915_gem_init_swizzling(dev_priv);
+	intel_gt_init_swizzling(&dev_priv->gt);
 	i915_gem_restore_fences(dev_priv);
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e2c8813c9355..1eb203fdee60 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2586,7 +2586,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
 void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
 void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
 void i915_gem_fini(struct drm_i915_private *dev_priv);
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7fdf252f9322..5c0db934315b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1205,29 +1205,6 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 	mutex_unlock(&i915->drm.struct_mutex);
 }
 
-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
-{
-	if (INTEL_GEN(dev_priv) < 5 ||
-	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
-		return;
-
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
-				 DISP_TILE_SURFACE_SWIZZLING);
-
-	if (IS_GEN(dev_priv, 5))
-		return;
-
-	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
-	if (IS_GEN(dev_priv, 6))
-		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
-	else if (IS_GEN(dev_priv, 7))
-		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
-	else if (IS_GEN(dev_priv, 8))
-		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
-	else
-		BUG();
-}
-
 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
 {
 	I915_WRITE(RING_CTL(base), 0);
@@ -1274,7 +1251,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	/* ...and determine whether they are sticking. */
 	intel_gt_verify_workarounds(dev_priv, "init");
 
-	i915_gem_init_swizzling(dev_priv);
+	intel_gt_init_swizzling(&dev_priv->gt);
 
 	/*
 	 * At least 830 can leave some of the unused rings
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 1c9466676caf..fc268599a0c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -834,3 +834,40 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
 
 	i915_gem_restore_fences(i915);
 }
+
+void intel_gt_init_swizzling(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
+
+	if (INTEL_GEN(i915) < 5 ||
+	    i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+		return;
+
+	intel_uncore_write(uncore,
+			   DISP_ARB_CTL,
+			   intel_uncore_read(uncore, DISP_ARB_CTL) |
+			   DISP_TILE_SURFACE_SWIZZLING);
+
+	if (IS_GEN(i915, 5))
+		return;
+
+	intel_uncore_write(uncore,
+			   TILECTL,
+			   intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL);
+
+	if (IS_GEN(i915, 6))
+		intel_uncore_write(uncore,
+				   ARB_MODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
+	else if (IS_GEN(i915, 7))
+		intel_uncore_write(uncore,
+				   ARB_MODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
+	else if (IS_GEN(i915, 8))
+		intel_uncore_write(uncore,
+				   GAMTARBMODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
+	else
+		MISSING_CASE(INTEL_GEN(i915));
+}
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
index d2da98828179..37e4f104f7c0 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.h
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
@@ -32,6 +32,7 @@ struct drm_i915_gem_object;
 struct drm_i915_private;
 struct i915_ggtt;
 struct i915_vma;
+struct intel_gt;
 struct sg_table;
 
 #define I965_FENCE_PAGE 4096UL
@@ -66,4 +67,6 @@ void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
 
 void i915_ggtt_init_fences(struct i915_ggtt *ggtt);
 
+void intel_gt_init_swizzling(struct intel_gt *gt);
+
 #endif
-- 
2.20.1

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[RFC 07/31] drm/i915: Convert init_unused_rings to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem.c | 42 ++++++++++++++++++---------------
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5c0db934315b..50be1d1d6f34 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1205,28 +1205,32 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 	mutex_unlock(&i915->drm.struct_mutex);
 }
 
-static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
+static void init_unused_ring(struct intel_gt *gt, u32 base)
 {
-	I915_WRITE(RING_CTL(base), 0);
-	I915_WRITE(RING_HEAD(base), 0);
-	I915_WRITE(RING_TAIL(base), 0);
-	I915_WRITE(RING_START(base), 0);
+	struct intel_uncore *uncore = gt->uncore;
+
+	intel_uncore_write(uncore, RING_CTL(base), 0);
+	intel_uncore_write(uncore, RING_HEAD(base), 0);
+	intel_uncore_write(uncore, RING_TAIL(base), 0);
+	intel_uncore_write(uncore, RING_START(base), 0);
 }
 
-static void init_unused_rings(struct drm_i915_private *dev_priv)
+static void init_unused_rings(struct intel_gt *gt)
 {
-	if (IS_I830(dev_priv)) {
-		init_unused_ring(dev_priv, PRB1_BASE);
-		init_unused_ring(dev_priv, SRB0_BASE);
-		init_unused_ring(dev_priv, SRB1_BASE);
-		init_unused_ring(dev_priv, SRB2_BASE);
-		init_unused_ring(dev_priv, SRB3_BASE);
-	} else if (IS_GEN(dev_priv, 2)) {
-		init_unused_ring(dev_priv, SRB0_BASE);
-		init_unused_ring(dev_priv, SRB1_BASE);
-	} else if (IS_GEN(dev_priv, 3)) {
-		init_unused_ring(dev_priv, PRB1_BASE);
-		init_unused_ring(dev_priv, PRB2_BASE);
+	struct drm_i915_private *i915 = gt->i915;
+
+	if (IS_I830(i915)) {
+		init_unused_ring(gt, PRB1_BASE);
+		init_unused_ring(gt, SRB0_BASE);
+		init_unused_ring(gt, SRB1_BASE);
+		init_unused_ring(gt, SRB2_BASE);
+		init_unused_ring(gt, SRB3_BASE);
+	} else if (IS_GEN(i915, 2)) {
+		init_unused_ring(gt, SRB0_BASE);
+		init_unused_ring(gt, SRB1_BASE);
+	} else if (IS_GEN(i915, 3)) {
+		init_unused_ring(gt, PRB1_BASE);
+		init_unused_ring(gt, PRB2_BASE);
 	}
 }
 
@@ -1259,7 +1263,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	 * will prevent c3 entry. Makes sure all unused rings
 	 * are totally idle.
 	 */
-	init_unused_rings(dev_priv);
+	init_unused_rings(&dev_priv->gt);
 
 	BUG_ON(!dev_priv->kernel_context);
 	ret = i915_terminally_wedged(dev_priv);
-- 
2.20.1

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[RFC 08/31] drm/i915: Convert gt workarounds to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More conversion of i915_gem_init_hw to uncore.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++-----
 drivers/gpu/drm/i915/gt/intel_workarounds.h |  6 +++---
 drivers/gpu/drm/i915/i915_gem.c             |  4 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 165b0a45e009..0b3308e39a17 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -6,6 +6,7 @@
 
 #include "i915_drv.h"
 #include "intel_context.h"
+#include "intel_gt.h"
 #include "intel_workarounds.h"
 
 /**
@@ -984,9 +985,9 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
 	spin_unlock_irqrestore(&uncore->lock, flags);
 }
 
-void intel_gt_apply_workarounds(struct drm_i915_private *i915)
+void intel_gt_apply_workarounds(struct intel_gt *gt)
 {
-	wa_list_apply(&i915->uncore, &i915->gt_wa_list);
+	wa_list_apply(gt->uncore, &gt->i915->gt_wa_list);
 }
 
 static bool wa_list_verify(struct intel_uncore *uncore,
@@ -1005,10 +1006,9 @@ static bool wa_list_verify(struct intel_uncore *uncore,
 	return ok;
 }
 
-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
-				 const char *from)
+bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
 {
-	return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);
+	return wa_list_verify(gt->uncore, &gt->i915->gt_wa_list, from);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.h b/drivers/gpu/drm/i915/gt/intel_workarounds.h
index 3761a6ee58bb..8c9c769c2204 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.h
@@ -14,6 +14,7 @@
 struct drm_i915_private;
 struct i915_request;
 struct intel_engine_cs;
+struct intel_gt;
 
 static inline void intel_wa_list_free(struct i915_wa_list *wal)
 {
@@ -25,9 +26,8 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine);
 int intel_engine_emit_ctx_wa(struct i915_request *rq);
 
 void intel_gt_init_workarounds(struct drm_i915_private *i915);
-void intel_gt_apply_workarounds(struct drm_i915_private *i915);
-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
-				 const char *from);
+void intel_gt_apply_workarounds(struct intel_gt *gt);
+bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from);
 
 void intel_engine_init_whitelist(struct intel_engine_cs *engine);
 void intel_engine_apply_whitelist(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 50be1d1d6f34..27d93fc8d20b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1251,9 +1251,9 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
 	/* Apply the GT workarounds... */
-	intel_gt_apply_workarounds(dev_priv);
+	intel_gt_apply_workarounds(&dev_priv->gt);
 	/* ...and determine whether they are sticking. */
-	intel_gt_verify_workarounds(dev_priv, "init");
+	intel_gt_verify_workarounds(&dev_priv->gt, "init");
 
 	intel_gt_init_swizzling(&dev_priv->gt);
 
-- 
2.20.1

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[RFC 09/31] drm/i915: Store backpointer to intel_gt in the engine

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

It will come useful in the next patch.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 1 +
 drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 35a9f754bcb9..c2d87c50dd6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -316,6 +316,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
 	engine->id = id;
 	engine->mask = BIT(id);
 	engine->i915 = dev_priv;
+	engine->gt = &dev_priv->gt;
 	engine->uncore = &dev_priv->uncore;
 	__sprint_engine_name(engine->name, info);
 	engine->hw_id = engine->guc_id = info->hw_id;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 01223864237a..343c4459e8a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -34,6 +34,7 @@ struct drm_i915_reg_table;
 struct i915_gem_context;
 struct i915_request;
 struct i915_sched_attr;
+struct intel_gt;
 struct intel_uncore;
 
 typedef u8 intel_engine_mask_t;
@@ -266,6 +267,7 @@ struct intel_engine_execlists {
 
 struct intel_engine_cs {
 	struct drm_i915_private *i915;
+	struct intel_gt *gt;
 	struct intel_uncore *uncore;
 	char name[INTEL_ENGINE_CS_MAX_NAME];
 
-- 
2.20.1

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[RFC 10/31] drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 52 +++++++++++++++++-----------
 drivers/gpu/drm/i915/gt/intel_mocs.h |  3 +-
 drivers/gpu/drm/i915/i915_gem.c      |  2 +-
 3 files changed, 35 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 79df66022d3a..aef8aa5b0b4d 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -23,6 +23,7 @@
 #include "i915_drv.h"
 
 #include "intel_engine.h"
+#include "intel_gt.h"
 #include "intel_mocs.h"
 #include "intel_lrc.h"
 
@@ -239,7 +240,7 @@ static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
 
 /**
  * get_mocs_settings()
- * @dev_priv:	i915 device.
+ * @gt:		gt device
  * @table:      Output table that will be made to point at appropriate
  *	      MOCS values for the device.
  *
@@ -249,33 +250,34 @@ static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
  *
  * Return: true if there are applicable MOCS settings for the device.
  */
-static bool get_mocs_settings(struct drm_i915_private *dev_priv,
+static bool get_mocs_settings(struct intel_gt *gt,
 			      struct drm_i915_mocs_table *table)
 {
+	struct drm_i915_private *i915 = gt->i915;
 	bool result = false;
 
-	if (INTEL_GEN(dev_priv) >= 11) {
+	if (INTEL_GEN(i915) >= 11) {
 		table->size  = ARRAY_SIZE(icelake_mocs_table);
 		table->table = icelake_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
 		result = true;
-	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+	} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = skylake_mocs_table;
 		result = true;
-	} else if (IS_GEN9_LP(dev_priv)) {
+	} else if (IS_GEN9_LP(i915)) {
 		table->size  = ARRAY_SIZE(broxton_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = broxton_mocs_table;
 		result = true;
 	} else {
-		WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
+		WARN_ONCE(INTEL_GEN(i915) >= 9,
 			  "Platform that should have a MOCS table does not.\n");
 	}
 
 	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
-	if (IS_GEN(dev_priv, 9)) {
+	if (IS_GEN(i915, 9)) {
 		int i;
 
 		for (i = 0; i < table->size; i++)
@@ -330,12 +332,13 @@ static u32 get_entry_control(const struct drm_i915_mocs_table *table,
  */
 void intel_mocs_init_engine(struct intel_engine_cs *engine)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
+	struct intel_gt *gt = engine->gt;
+	struct intel_uncore *uncore = gt->uncore;
 	struct drm_i915_mocs_table table;
 	unsigned int index;
 	u32 unused_value;
 
-	if (!get_mocs_settings(dev_priv, &table))
+	if (!get_mocs_settings(gt, &table))
 		return;
 
 	/* Set unused values to PTE */
@@ -344,12 +347,16 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
 	for (index = 0; index < table.size; index++) {
 		u32 value = get_entry_control(&table, index);
 
-		I915_WRITE(mocs_register(engine->id, index), value);
+		intel_uncore_write(uncore,
+				   mocs_register(engine->id, index),
+				   value);
 	}
 
 	/* All remaining entries are also unused */
 	for (; index < table.n_entries; index++)
-		I915_WRITE(mocs_register(engine->id, index), unused_value);
+		intel_uncore_write(uncore,
+				   mocs_register(engine->id, index),
+				   unused_value);
 }
 
 /**
@@ -494,13 +501,14 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
  *
  * Return: Nothing.
  */
-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
+void intel_mocs_init_l3cc_table(struct intel_gt *gt)
 {
+	struct intel_uncore *uncore = gt->uncore;
 	struct drm_i915_mocs_table table;
 	unsigned int i;
 	u16 unused_value;
 
-	if (!get_mocs_settings(dev_priv, &table))
+	if (!get_mocs_settings(gt, &table))
 		return;
 
 	/* Set unused values to PTE */
@@ -510,23 +518,27 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
 		u16 low = get_entry_l3cc(&table, 2 * i);
 		u16 high = get_entry_l3cc(&table, 2 * i + 1);
 
-		I915_WRITE(GEN9_LNCFCMOCS(i),
-			   l3cc_combine(&table, low, high));
+		intel_uncore_write(uncore,
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, low, high));
 	}
 
 	/* Odd table size - 1 left over */
 	if (table.size & 0x01) {
 		u16 low = get_entry_l3cc(&table, 2 * i);
 
-		I915_WRITE(GEN9_LNCFCMOCS(i),
-			   l3cc_combine(&table, low, unused_value));
+		intel_uncore_write(uncore,
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, low, unused_value));
 		i++;
 	}
 
 	/* All remaining entries are also unused */
 	for (; i < table.n_entries / 2; i++)
-		I915_WRITE(GEN9_LNCFCMOCS(i),
-			   l3cc_combine(&table, unused_value, unused_value));
+		intel_uncore_write(uncore,
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, unused_value,
+						unused_value));
 }
 
 /**
@@ -550,7 +562,7 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
 	struct drm_i915_mocs_table t;
 	int ret;
 
-	if (get_mocs_settings(rq->i915, &t)) {
+	if (get_mocs_settings(rq->engine->gt, &t)) {
 		/* Program the RCS control registers */
 		ret = emit_mocs_control_table(rq, &t);
 		if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index 0913704a1af2..8b9813e6f9ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -52,9 +52,10 @@
 struct drm_i915_private;
 struct i915_request;
 struct intel_engine_cs;
+struct intel_gt;
 
 int intel_rcs_context_init_mocs(struct i915_request *rq);
-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv);
+void intel_mocs_init_l3cc_table(struct intel_gt *gt);
 void intel_mocs_init_engine(struct intel_engine_cs *engine);
 
 #endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 27d93fc8d20b..49c7c7b87bdc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1289,7 +1289,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 		goto out;
 	}
 
-	intel_mocs_init_l3cc_table(dev_priv);
+	intel_mocs_init_l3cc_table(&dev_priv->gt);
 
 	/* Only when the HW is re-initialised, can we replay the requests */
 	ret = intel_engines_resume(dev_priv);
-- 
2.20.1

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[RFC 11/31] drm/i915: Convert i915_ppgtt_init_hw to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem.c     |   2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c | 102 ++++++++++++++++++----------
 drivers/gpu/drm/i915/i915_gem_gtt.h |   3 +-
 3 files changed, 68 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 49c7c7b87bdc..e54cd30534dc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1270,7 +1270,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	if (ret)
 		goto out;
 
-	ret = i915_ppgtt_init_hw(dev_priv);
+	ret = i915_ppgtt_init_hw(&dev_priv->gt);
 	if (ret) {
 		DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 		goto out;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ac6ed459720e..651ca5ed08a1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -43,6 +43,7 @@
 #include "i915_vgpu.h"
 #include "intel_drv.h"
 #include "intel_frontbuffer.h"
+#include "gt/intel_gt.h"
 
 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
 
@@ -1694,25 +1695,29 @@ static inline void gen6_write_pde(const struct gen6_ppgtt *ppgtt,
 		  ppgtt->pd_addr + pde);
 }
 
-static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
+static void gen7_ppgtt_enable(struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
 	struct intel_engine_cs *engine;
 	u32 ecochk, ecobits;
 	enum intel_engine_id id;
 
-	ecobits = I915_READ(GAC_ECO_BITS);
-	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
+	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
+	intel_uncore_write(uncore,
+			   GAC_ECO_BITS,
+			   ecobits | ECOBITS_PPGTT_CACHE64B);
 
-	ecochk = I915_READ(GAM_ECOCHK);
-	if (IS_HASWELL(dev_priv)) {
+	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
+	if (IS_HASWELL(i915)) {
 		ecochk |= ECOCHK_PPGTT_WB_HSW;
 	} else {
 		ecochk |= ECOCHK_PPGTT_LLC_IVB;
 		ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 	}
-	I915_WRITE(GAM_ECOCHK, ecochk);
+	intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
 
-	for_each_engine(engine, dev_priv, id) {
+	for_each_engine(engine, i915, id) {
 		/* GFX_MODE is per-ring on gen7+ */
 		ENGINE_WRITE(engine,
 			     RING_MODE_GEN7,
@@ -1720,22 +1725,30 @@ static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
+static void gen6_ppgtt_enable(struct intel_gt *gt)
 {
+	struct intel_uncore *uncore = gt->uncore;
 	u32 ecochk, gab_ctl, ecobits;
 
-	ecobits = I915_READ(GAC_ECO_BITS);
-	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
-		   ECOBITS_PPGTT_CACHE64B);
+	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
+	intel_uncore_write(uncore,
+			   GAC_ECO_BITS,
+			   ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
 
-	gab_ctl = I915_READ(GAB_CTL);
-	I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
+	gab_ctl = intel_uncore_read(uncore, GAB_CTL);
+	intel_uncore_write(uncore,
+			   GAB_CTL,
+			   gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 
-	ecochk = I915_READ(GAM_ECOCHK);
-	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
+	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
+	intel_uncore_write(uncore,
+			   GAM_ECOCHK,
+			   ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 
-	if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
-		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+	if (HAS_PPGTT(uncore_to_i915(uncore))) /* may be disabled for VT-d */
+		intel_uncore_write(uncore,
+				   GFX_MODE,
+				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 }
 
 /* PPGTT support for Sandybdrige/Gen6 and later */
@@ -2187,21 +2200,32 @@ static struct i915_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
 	return ERR_PTR(err);
 }
 
-static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
+static void gtt_write_workarounds(struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
+
 	/* This function is for gtt related workarounds. This function is
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
 	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
-	if (IS_BROADWELL(dev_priv))
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
-	else if (IS_CHERRYVIEW(dev_priv))
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-	else if (IS_GEN9_LP(dev_priv))
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
-	else if (INTEL_GEN(dev_priv) >= 9)
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
+	if (IS_BROADWELL(i915))
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
+	else if (IS_CHERRYVIEW(i915))
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
+	else if (IS_GEN9_LP(i915))
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
+	else if (INTEL_GEN(i915) >= 9)
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
 
 	/*
 	 * To support 64K PTEs we need to first enable the use of the
@@ -2214,21 +2238,25 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * 32K pages, but we don't currently have any support for it in our
 	 * driver.
 	 */
-	if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
-	    INTEL_GEN(dev_priv) <= 10)
-		I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
-			   I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
-			   GAMW_ECO_ENABLE_64K_IPS_FIELD);
+	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
+	    INTEL_GEN(i915) <= 10)
+		intel_uncore_write(uncore,
+				   GEN8_GAMW_ECO_DEV_RW_IA,
+				   intel_uncore_read(uncore,
+						     GEN8_GAMW_ECO_DEV_RW_IA) |
+				   GAMW_ECO_ENABLE_64K_IPS_FIELD);
 }
 
-int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
+int i915_ppgtt_init_hw(struct intel_gt *gt)
 {
-	gtt_write_workarounds(dev_priv);
+	struct drm_i915_private *i915 = gt->i915;
+
+	gtt_write_workarounds(gt);
 
-	if (IS_GEN(dev_priv, 6))
-		gen6_ppgtt_enable(dev_priv);
-	else if (IS_GEN(dev_priv, 7))
-		gen7_ppgtt_enable(dev_priv);
+	if (IS_GEN(i915, 6))
+		gen6_ppgtt_enable(gt);
+	else if (IS_GEN(i915, 7))
+		gen7_ppgtt_enable(gt);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 63fa357c69de..f8c06288be65 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -64,6 +64,7 @@
 struct drm_i915_file_private;
 struct drm_i915_gem_object;
 struct i915_vma;
+struct intel_gt;
 
 typedef u32 gen6_pte_t;
 typedef u64 gen8_pte_t;
@@ -647,7 +648,7 @@ void i915_ggtt_disable_guc(struct drm_i915_private *i915);
 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
 
-int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv);
+int i915_ppgtt_init_hw(struct intel_gt *gt);
 
 struct i915_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv);
 
-- 
2.20.1

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[RFC 12/31] drm/i915: Consolidate some open coded mmio rmw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Replace some gen6/7 open coded rmw with intel_uncore_rmw.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 41 +++++++++++++----------------
 1 file changed, 18 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 651ca5ed08a1..0810c1655224 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1700,13 +1700,10 @@ static void gen7_ppgtt_enable(struct intel_gt *gt)
 	struct drm_i915_private *i915 = gt->i915;
 	struct intel_uncore *uncore = gt->uncore;
 	struct intel_engine_cs *engine;
-	u32 ecochk, ecobits;
 	enum intel_engine_id id;
+	u32 ecochk;
 
-	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
-	intel_uncore_write(uncore,
-			   GAC_ECO_BITS,
-			   ecobits | ECOBITS_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
 
 	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
 	if (IS_HASWELL(i915)) {
@@ -1728,22 +1725,21 @@ static void gen7_ppgtt_enable(struct intel_gt *gt)
 static void gen6_ppgtt_enable(struct intel_gt *gt)
 {
 	struct intel_uncore *uncore = gt->uncore;
-	u32 ecochk, gab_ctl, ecobits;
 
-	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
-	intel_uncore_write(uncore,
-			   GAC_ECO_BITS,
-			   ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore,
+			 GAC_ECO_BITS,
+			 0,
+			 ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
 
-	gab_ctl = intel_uncore_read(uncore, GAB_CTL);
-	intel_uncore_write(uncore,
-			   GAB_CTL,
-			   gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
+	intel_uncore_rmw(uncore,
+			 GAB_CTL,
+			 0,
+			 GAB_CTL_CONT_AFTER_PAGEFAULT);
 
-	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
-	intel_uncore_write(uncore,
-			   GAM_ECOCHK,
-			   ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore,
+			 GAM_ECOCHK,
+			 0,
+			 ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 
 	if (HAS_PPGTT(uncore_to_i915(uncore))) /* may be disabled for VT-d */
 		intel_uncore_write(uncore,
@@ -2240,11 +2236,10 @@ static void gtt_write_workarounds(struct intel_gt *gt)
 	 */
 	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
 	    INTEL_GEN(i915) <= 10)
-		intel_uncore_write(uncore,
-				   GEN8_GAMW_ECO_DEV_RW_IA,
-				   intel_uncore_read(uncore,
-						     GEN8_GAMW_ECO_DEV_RW_IA) |
-				   GAMW_ECO_ENABLE_64K_IPS_FIELD);
+		intel_uncore_rmw(uncore,
+				 GEN8_GAMW_ECO_DEV_RW_IA,
+				 0,
+				 GAMW_ECO_ENABLE_64K_IPS_FIELD);
 }
 
 int i915_ppgtt_init_hw(struct intel_gt *gt)
-- 
2.20.1

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[RFC 13/31] drm/i915: Convert i915_gem_init_hw to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Actually the top level function remains but is split into a part which
writes to i915 and part which operates on intel_gt in order to initialize
the hardware.

GuC and engines are the only odd ones out remaining.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 66 ++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e54cd30534dc..b6f450e782e7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1234,28 +1234,32 @@ static void init_unused_rings(struct intel_gt *gt)
 	}
 }
 
-int i915_gem_init_hw(struct drm_i915_private *dev_priv)
+static int init_hw(struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
 	int ret;
 
-	dev_priv->gt.last_init_time = ktime_get();
+	gt->last_init_time = ktime_get();
 
 	/* Double layer security blanket, see i915_gem_init() */
-	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 
-	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
-		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
+	if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
+		intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 
-	if (IS_HASWELL(dev_priv))
-		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
-			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
+	if (IS_HASWELL(i915))
+		intel_uncore_write(uncore,
+				   MI_PREDICATE_RESULT_2,
+				   IS_HSW_GT3(i915) ?
+				   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
 	/* Apply the GT workarounds... */
-	intel_gt_apply_workarounds(&dev_priv->gt);
+	intel_gt_apply_workarounds(gt);
 	/* ...and determine whether they are sticking. */
-	intel_gt_verify_workarounds(&dev_priv->gt, "init");
+	intel_gt_verify_workarounds(gt, "init");
 
-	intel_gt_init_swizzling(&dev_priv->gt);
+	intel_gt_init_swizzling(gt);
 
 	/*
 	 * At least 830 can leave some of the unused rings
@@ -1263,48 +1267,58 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	 * will prevent c3 entry. Makes sure all unused rings
 	 * are totally idle.
 	 */
-	init_unused_rings(&dev_priv->gt);
-
-	BUG_ON(!dev_priv->kernel_context);
-	ret = i915_terminally_wedged(dev_priv);
-	if (ret)
-		goto out;
+	init_unused_rings(gt);
 
-	ret = i915_ppgtt_init_hw(&dev_priv->gt);
+	ret = i915_ppgtt_init_hw(gt);
 	if (ret) {
 		DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 		goto out;
 	}
 
-	ret = intel_wopcm_init_hw(&dev_priv->wopcm);
+	ret = intel_wopcm_init_hw(&i915->wopcm);
 	if (ret) {
 		DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
 		goto out;
 	}
 
 	/* We can't enable contexts until all firmware is loaded */
-	ret = intel_uc_init_hw(dev_priv);
+	ret = intel_uc_init_hw(i915);
 	if (ret) {
 		DRM_ERROR("Enabling uc failed (%d)\n", ret);
 		goto out;
 	}
 
-	intel_mocs_init_l3cc_table(&dev_priv->gt);
+	intel_mocs_init_l3cc_table(gt);
 
 	/* Only when the HW is re-initialised, can we replay the requests */
-	ret = intel_engines_resume(dev_priv);
+	ret = intel_engines_resume(i915);
 	if (ret)
 		goto cleanup_uc;
 
-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
-	intel_engines_set_scheduler_caps(dev_priv);
 	return 0;
 
 cleanup_uc:
-	intel_uc_fini_hw(dev_priv);
+	intel_uc_fini_hw(i915);
 out:
-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
+
+	return ret;
+}
+
+int i915_gem_init_hw(struct drm_i915_private *i915)
+{
+	int ret;
+
+	BUG_ON(!i915->kernel_context);
+	ret = i915_terminally_wedged(i915);
+	if (ret)
+		return ret;
+
+	ret = init_hw(&i915->gt);
+
+	intel_engines_set_scheduler_caps(i915);
 
 	return ret;
 }
-- 
2.20.1

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[RFC 14/31] drm/i915: Move intel_engines_resume into common init

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Since this part still operates on i915 and not intel_gt, move it to the
common (top-level) function.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem.c | 29 ++++++++++++++++++++++-------
 1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b6f450e782e7..77d9d092b2f4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1290,17 +1290,10 @@ static int init_hw(struct intel_gt *gt)
 
 	intel_mocs_init_l3cc_table(gt);
 
-	/* Only when the HW is re-initialised, can we replay the requests */
-	ret = intel_engines_resume(i915);
-	if (ret)
-		goto cleanup_uc;
-
 	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
 	return 0;
 
-cleanup_uc:
-	intel_uc_fini_hw(i915);
 out:
 	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
@@ -1309,6 +1302,7 @@ static int init_hw(struct intel_gt *gt)
 
 int i915_gem_init_hw(struct drm_i915_private *i915)
 {
+	struct intel_uncore *uncore = &i915->uncore;
 	int ret;
 
 	BUG_ON(!i915->kernel_context);
@@ -1316,7 +1310,28 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
 	if (ret)
 		return ret;
 
+	/* Double layer security blanket, see i915_gem_init() */
+	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
+
 	ret = init_hw(&i915->gt);
+	if (ret)
+		goto err_init;
+
+	/* Only when the HW is re-initialised, can we replay the requests */
+	ret = intel_engines_resume(i915);
+	if (ret)
+		goto err_engines;
+
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
+
+	intel_engines_set_scheduler_caps(i915);
+
+	return 0;
+
+err_engines:
+	intel_uc_fini_hw(i915);
+err_init:
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
 	intel_engines_set_scheduler_caps(i915);
 
-- 
2.20.1

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[RFC 15/31] drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More legacy mmio accessor removal. We pass in intel_gt explicitly allowing
code to use new intel_uncore_read/write helpers.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c    |  2 +-
 drivers/gpu/drm/i915/intel_wopcm.c | 31 ++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_wopcm.h |  4 +++-
 3 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 77d9d092b2f4..b7f88e2bd7df 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1275,7 +1275,7 @@ static int init_hw(struct intel_gt *gt)
 		goto out;
 	}
 
-	ret = intel_wopcm_init_hw(&i915->wopcm);
+	ret = intel_wopcm_init_hw(&i915->wopcm, gt);
 	if (ret) {
 		DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
 		goto out;
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index 7b4ba84b9fb8..931987e37241 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -225,17 +225,18 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
 	return 0;
 }
 
-static inline int write_and_verify(struct drm_i915_private *dev_priv,
-				   i915_reg_t reg, u32 val, u32 mask,
-				   u32 locked_bit)
+static int
+write_and_verify(struct intel_gt *gt,
+		 i915_reg_t reg, u32 val, u32 mask, u32 locked_bit)
 {
+	struct intel_uncore *uncore = gt->uncore;
 	u32 reg_val;
 
 	GEM_BUG_ON(val & ~mask);
 
-	I915_WRITE(reg, val);
+	intel_uncore_write(uncore, reg, val);
 
-	reg_val = I915_READ(reg);
+	reg_val = intel_uncore_read(uncore, reg);
 
 	return (reg_val & mask) != (val | locked_bit) ? -EIO : 0;
 }
@@ -250,29 +251,30 @@ static inline int write_and_verify(struct drm_i915_private *dev_priv,
  *
  * Return: 0 on success. -EIO if registers were locked with incorrect values.
  */
-int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
+int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt)
 {
-	struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
+	struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
+	struct intel_uncore *uncore = gt->uncore;
 	u32 huc_agent;
 	u32 mask;
 	int err;
 
-	if (!USES_GUC(dev_priv))
+	if (!USES_GUC(i915))
 		return 0;
 
-	GEM_BUG_ON(!HAS_GUC(dev_priv));
+	GEM_BUG_ON(!HAS_GUC(i915));
 	GEM_BUG_ON(!wopcm->guc.size);
 	GEM_BUG_ON(!wopcm->guc.base);
 
-	err = write_and_verify(dev_priv, GUC_WOPCM_SIZE, wopcm->guc.size,
+	err = write_and_verify(gt, GUC_WOPCM_SIZE, wopcm->guc.size,
 			       GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED,
 			       GUC_WOPCM_SIZE_LOCKED);
 	if (err)
 		goto err_out;
 
-	huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
+	huc_agent = USES_HUC(i915) ? HUC_LOADING_AGENT_GUC : 0;
 	mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
-	err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
+	err = write_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
 			       wopcm->guc.base | huc_agent, mask,
 			       GUC_WOPCM_OFFSET_VALID);
 	if (err)
@@ -283,8 +285,9 @@ int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
 err_out:
 	DRM_ERROR("Failed to init WOPCM registers:\n");
 	DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
-		  I915_READ(DMA_GUC_WOPCM_OFFSET));
-	DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));
+		  intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
+	DRM_ERROR("GUC_WOPCM_SIZE=%#x\n",
+		  intel_uncore_read(uncore, GUC_WOPCM_SIZE));
 
 	return err;
 }
diff --git a/drivers/gpu/drm/i915/intel_wopcm.h b/drivers/gpu/drm/i915/intel_wopcm.h
index 114401971520..56aaed4d64ff 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_wopcm.h
@@ -9,6 +9,8 @@
 
 #include <linux/types.h>
 
+struct intel_gt;
+
 /**
  * struct intel_wopcm - Overall WOPCM info and WOPCM regions.
  * @size: Size of overall WOPCM.
@@ -41,6 +43,6 @@ static inline u32 intel_wopcm_guc_size(struct intel_wopcm *wopcm)
 
 void intel_wopcm_init_early(struct intel_wopcm *wopcm);
 int intel_wopcm_init(struct intel_wopcm *wopcm);
-int intel_wopcm_init_hw(struct intel_wopcm *wopcm);
+int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt);
 
 #endif
-- 
2.20.1

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[RFC 16/31] drm/i915: Compartmentalize i915_ggtt_probe_hw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Having made start to better code compartmentalization by introducing
struct intel_gt, continue the theme elsewhere in code by making functions
take parameters take what logically makes most sense for them instead of
the global struct drm_i915_private.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 31 +++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0810c1655224..c88213fa18af 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3507,21 +3507,16 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
 	return 0;
 }
 
-/**
- * i915_ggtt_probe_hw - Probe GGTT hardware location
- * @dev_priv: i915 device
- */
-int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
+static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct drm_i915_private *i915)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 	int ret;
 
-	ggtt->vm.i915 = dev_priv;
-	ggtt->vm.dma = &dev_priv->drm.pdev->dev;
+	ggtt->vm.i915 = i915;
+	ggtt->vm.dma = &i915->drm.pdev->dev;
 
-	if (INTEL_GEN(dev_priv) <= 5)
+	if (INTEL_GEN(i915) <= 5)
 		ret = i915_gmch_probe(ggtt);
-	else if (INTEL_GEN(dev_priv) < 8)
+	else if (INTEL_GEN(i915) < 8)
 		ret = gen6_gmch_probe(ggtt);
 	else
 		ret = gen8_gmch_probe(ggtt);
@@ -3549,6 +3544,22 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
 	DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20);
 	DRM_DEBUG_DRIVER("DSM size = %lluM\n",
 			 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
+
+	return 0;
+}
+
+/**
+ * i915_ggtt_probe_hw - Probe GGTT hardware location
+ * @dev_priv: i915 device
+ */
+int i915_ggtt_probe_hw(struct drm_i915_private *i915)
+{
+	int ret;
+
+	ret = ggtt_probe_hw(&i915->ggtt, i915);
+	if (ret)
+		return ret;
+
 	if (intel_vtd_active())
 		DRM_INFO("VT-d active for gfx access\n");
 
-- 
2.20.1

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[RFC 17/31] drm/i915: Compartmentalize i915_ggtt_init_hw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Having made start to better code compartmentalization by introducing
struct intel_gt, continue the theme elsewhere in code by making functions
take parameters take what logically makes most sense for them instead of
the global struct drm_i915_private.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 64 +++++++++++++++++++----------
 1 file changed, 42 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c88213fa18af..2232bd56e912 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3566,45 +3566,65 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 	return 0;
 }
 
-/**
- * i915_ggtt_init_hw - Initialize GGTT hardware
- * @dev_priv: i915 device
- */
-int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
+static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
-	int ret;
+	ggtt->vm.cleanup(&ggtt->vm);
+}
 
-	stash_init(&dev_priv->mm.wc_stash);
+static int ggtt_init_hw(struct i915_ggtt *ggtt)
+{
+	struct drm_i915_private *i915 = ggtt->vm.i915;
+	int ret = 0;
+
+	mutex_lock(&i915->drm.struct_mutex);
 
-	/* Note that we use page colouring to enforce a guard page at the
-	 * end of the address space. This is required as the CS may prefetch
-	 * beyond the end of the batch buffer, across the page boundary,
-	 * and beyond the end of the GTT if we do not provide a guard.
-	 */
-	mutex_lock(&dev_priv->drm.struct_mutex);
 	i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
 
 	ggtt->vm.is_ggtt = true;
 
 	/* Only VLV supports read-only GGTT mappings */
-	ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
+	ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
 
-	if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
+	if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
 		ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
-	mutex_unlock(&dev_priv->drm.struct_mutex);
 
-	if (!io_mapping_init_wc(&dev_priv->ggtt.iomap,
-				dev_priv->ggtt.gmadr.start,
-				dev_priv->ggtt.mappable_end)) {
+	if (!io_mapping_init_wc(&ggtt->iomap,
+				ggtt->gmadr.start,
+				ggtt->mappable_end)) {
+		ggtt_cleanup_hw(ggtt);
 		ret = -EIO;
-		goto out_gtt_cleanup;
+		goto out;
 	}
 
 	ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
 
 	i915_ggtt_init_fences(ggtt);
 
+out:
+	mutex_unlock(&i915->drm.struct_mutex);
+
+	return ret;
+}
+
+/**
+ * i915_ggtt_init_hw - Initialize GGTT hardware
+ * @dev_priv: i915 device
+ */
+int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
+{
+	int ret;
+
+	stash_init(&dev_priv->mm.wc_stash);
+
+	/* Note that we use page colouring to enforce a guard page at the
+	 * end of the address space. This is required as the CS may prefetch
+	 * beyond the end of the batch buffer, across the page boundary,
+	 * and beyond the end of the GTT if we do not provide a guard.
+	 */
+	ret = ggtt_init_hw(&dev_priv->ggtt);
+	if (ret)
+		return ret;
+
 	/*
 	 * Initialise stolen early so that we may reserve preallocated
 	 * objects for the BIOS to KMS transition.
@@ -3616,7 +3636,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
 	return 0;
 
 out_gtt_cleanup:
-	ggtt->vm.cleanup(&ggtt->vm);
+	ggtt_cleanup_hw(&dev_priv->ggtt);
 	return ret;
 }
 
-- 
2.20.1

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[RFC 18/31] drm/i915: Make ggtt invalidation work on ggtt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

It is more logical for ggtt invalidation to take ggtt as input parameter.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 51 ++++++++++++++---------------
 drivers/gpu/drm/i915/i915_gem_gtt.h |  2 +-
 2 files changed, 26 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2232bd56e912..95af45156cc2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -111,9 +111,9 @@
 static int
 i915_get_ggtt_vma_pages(struct i915_vma *vma);
 
-static void gen6_ggtt_invalidate(struct drm_i915_private *i915)
+static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
-	struct intel_uncore *uncore = &i915->uncore;
+	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
 
 	/*
 	 * Note that as an uncached mmio write, this will flush the
@@ -122,24 +122,19 @@ static void gen6_ggtt_invalidate(struct drm_i915_private *i915)
 	intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 }
 
-static void guc_ggtt_invalidate(struct drm_i915_private *i915)
+static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
-	struct intel_uncore *uncore = &i915->uncore;
+	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
 
-	gen6_ggtt_invalidate(i915);
+	gen6_ggtt_invalidate(ggtt);
 	intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 }
 
-static void gmch_ggtt_invalidate(struct drm_i915_private *i915)
+static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
 	intel_gtt_chipset_flush();
 }
 
-static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
-{
-	i915->ggtt.invalidate(i915);
-}
-
 static int ppgtt_bind_vma(struct i915_vma *vma,
 			  enum i915_cache_level cache_level,
 			  u32 unused)
@@ -1876,7 +1871,7 @@ static int gen6_alloc_va_range(struct i915_address_space *vm,
 
 	if (flush) {
 		mark_tlbs_dirty(&ppgtt->base);
-		gen6_ggtt_invalidate(vm->i915);
+		gen6_ggtt_invalidate(&vm->i915->ggtt);
 	}
 
 	intel_runtime_pm_put(vm->i915, wakeref);
@@ -2025,7 +2020,7 @@ static int pd_vma_bind(struct i915_vma *vma,
 		gen6_write_pde(ppgtt, pde, pt);
 
 	mark_tlbs_dirty(&ppgtt->base);
-	gen6_ggtt_invalidate(ppgtt->base.vm.i915);
+	gen6_ggtt_invalidate(ggtt);
 
 	return 0;
 }
@@ -2340,7 +2335,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
 
 	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
 
-	i915_ggtt_invalidate(dev_priv);
+	ggtt->invalidate(ggtt);
 }
 
 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
@@ -2386,7 +2381,7 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm,
 
 	gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
 
-	ggtt->invalidate(vm->i915);
+	ggtt->invalidate(ggtt);
 }
 
 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
@@ -2414,7 +2409,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 	 * We want to flush the TLBs only after we're certain all the PTE
 	 * updates have finished.
 	 */
-	ggtt->invalidate(vm->i915);
+	ggtt->invalidate(ggtt);
 }
 
 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
@@ -2429,7 +2424,7 @@ static void gen6_ggtt_insert_page(struct i915_address_space *vm,
 
 	iowrite32(vm->pte_encode(addr, level, flags), pte);
 
-	ggtt->invalidate(vm->i915);
+	ggtt->invalidate(ggtt);
 }
 
 /*
@@ -2455,7 +2450,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 	 * We want to flush the TLBs only after we're certain all the PTE
 	 * updates have finished.
 	 */
-	ggtt->invalidate(vm->i915);
+	ggtt->invalidate(ggtt);
 }
 
 static void nop_clear_range(struct i915_address_space *vm,
@@ -3650,25 +3645,29 @@ int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
 
 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 {
-	GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
+	struct i915_ggtt *ggtt = &i915->ggtt;
 
-	i915->ggtt.invalidate = guc_ggtt_invalidate;
+	GEM_BUG_ON(ggtt->invalidate != gen6_ggtt_invalidate);
 
-	i915_ggtt_invalidate(i915);
+	ggtt->invalidate = guc_ggtt_invalidate;
+
+	ggtt->invalidate(ggtt);
 }
 
 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 {
+	struct i915_ggtt *ggtt = &i915->ggtt;
+
 	/* XXX Temporary pardon for error unload */
-	if (i915->ggtt.invalidate == gen6_ggtt_invalidate)
+	if (ggtt->invalidate == gen6_ggtt_invalidate)
 		return;
 
 	/* We should only be called after i915_ggtt_enable_guc() */
-	GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
+	GEM_BUG_ON(ggtt->invalidate != guc_ggtt_invalidate);
 
-	i915->ggtt.invalidate = gen6_ggtt_invalidate;
+	ggtt->invalidate = gen6_ggtt_invalidate;
 
-	i915_ggtt_invalidate(i915);
+	ggtt->invalidate(ggtt);
 }
 
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
@@ -3710,7 +3709,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 	}
 
 	ggtt->vm.closed = false;
-	i915_ggtt_invalidate(dev_priv);
+	ggtt->invalidate(ggtt);
 
 	mutex_unlock(&ggtt->vm.mutex);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f8c06288be65..b541190db6e8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -401,7 +401,7 @@ struct i915_ggtt {
 
 	/** "Graphics Stolen Memory" holds the global PTEs */
 	void __iomem *gsm;
-	void (*invalidate)(struct drm_i915_private *dev_priv);
+	void (*invalidate)(struct i915_ggtt *ggtt);
 
 	bool do_idle_maps;
 
-- 
2.20.1

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[RFC 19/31] drm/i915: Store intel_gt backpointer in vm

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This will come useful in the following patch.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 16 ++++++++++------
 drivers/gpu/drm/i915/i915_gem_gtt.h |  1 +
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 95af45156cc2..0bc75c963955 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1587,9 +1587,11 @@ static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
 	return -ENOMEM;
 }
 
-static void ppgtt_init(struct drm_i915_private *i915,
-		       struct i915_ppgtt *ppgtt)
+static void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
+
+	ppgtt->vm.gt = gt;
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 	ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
@@ -1618,7 +1620,7 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	if (!ppgtt)
 		return ERR_PTR(-ENOMEM);
 
-	ppgtt_init(i915, ppgtt);
+	ppgtt_init(ppgtt, &i915->gt);
 
 	/*
 	 * From bdw, there is hw support for read-only pages in the PPGTT.
@@ -2155,7 +2157,7 @@ static struct i915_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
 	if (!ppgtt)
 		return ERR_PTR(-ENOMEM);
 
-	ppgtt_init(i915, &ppgtt->base);
+	ppgtt_init(&ppgtt->base, &i915->gt);
 
 	ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
 	ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
@@ -3502,10 +3504,12 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
 	return 0;
 }
 
-static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct drm_i915_private *i915)
+static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
 	int ret;
 
+	ggtt->vm.gt = gt;
 	ggtt->vm.i915 = i915;
 	ggtt->vm.dma = &i915->drm.pdev->dev;
 
@@ -3551,7 +3555,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 {
 	int ret;
 
-	ret = ggtt_probe_hw(&i915->ggtt, i915);
+	ret = ggtt_probe_hw(&i915->ggtt, &i915->gt);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index b541190db6e8..9a3d96370f07 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -297,6 +297,7 @@ struct i915_address_space {
 	struct kref ref;
 
 	struct drm_mm mm;
+	struct intel_gt *gt;
 	struct drm_i915_private *i915;
 	struct device *dma;
 	/* Every address space belongs to a struct file - except for the global
-- 
2.20.1

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[RFC 20/31] drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Having made start to better code compartmentalization by introducing
struct intel_gt, continue the theme elsewhere in code by making functions
take parameters take what logically makes most sense for them instead of
the global struct drm_i915_private.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0bc75c963955..516ffc4a521a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2323,23 +2323,28 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
 	return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
 }
 
-void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
+static void ggtt_suspend_mappings(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
+	struct drm_i915_private *i915 = ggtt->vm.i915;
 
 	/* Don't bother messing with faults pre GEN6 as we have little
 	 * documentation supporting that it's a good idea.
 	 */
-	if (INTEL_GEN(dev_priv) < 6)
+	if (INTEL_GEN(i915) < 6)
 		return;
 
-	intel_gt_check_and_clear_faults(&dev_priv->gt);
+	intel_gt_check_and_clear_faults(ggtt->vm.gt);
 
 	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
 
 	ggtt->invalidate(ggtt);
 }
 
+void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
+{
+	ggtt_suspend_mappings(&dev_priv->ggtt);
+}
+
 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
 			       struct sg_table *pages)
 {
@@ -3674,12 +3679,11 @@ void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 	ggtt->invalidate(ggtt);
 }
 
-void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
+static void ggtt_restore_mappings(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 	struct i915_vma *vma, *vn;
 
-	intel_gt_check_and_clear_faults(&dev_priv->gt);
+	intel_gt_check_and_clear_faults(ggtt->vm.gt);
 
 	mutex_lock(&ggtt->vm.mutex);
 
@@ -3716,6 +3720,11 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 	ggtt->invalidate(ggtt);
 
 	mutex_unlock(&ggtt->vm.mutex);
+}
+
+void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
+{
+	ggtt_restore_mappings(&dev_priv->ggtt);
 
 	if (INTEL_GEN(dev_priv) >= 8) {
 		struct intel_ppat *ppat = &dev_priv->ppat;
-- 
2.20.1

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[RFC 21/31] drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Having introduced struct intel_gt (named the anonymous structure in i915)
we can start using it to compartmentalize our code better. It makes more
sense logically to have the code internally like this and it will also
help with future split between gt and display in i915.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c    |  5 +--
 .../drm/i915/gem/selftests/i915_gem_mman.c    |  3 +-
 drivers/gpu/drm/i915/gt/intel_gt.c            | 41 +++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h            |  2 +
 drivers/gpu/drm/i915/i915_drv.h               |  2 -
 drivers/gpu/drm/i915/i915_gem.c               | 40 ------------------
 drivers/gpu/drm/i915/i915_vma.c               |  3 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  2 +-
 8 files changed, 50 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 36b76c6a0a9d..a3d8bfb01eb8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -22,6 +22,7 @@
  *
  */
 
+#include "gt/intel_gt.h"
 #include "i915_drv.h"
 #include "i915_gem_clflush.h"
 #include "i915_gem_context.h"
@@ -367,7 +368,6 @@ void
 i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 				   unsigned int flush_domains)
 {
-	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 	struct i915_vma *vma;
 
 	assert_object_held(obj);
@@ -377,8 +377,6 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 
 	switch (obj->write_domain) {
 	case I915_GEM_DOMAIN_GTT:
-		i915_gem_flush_ggtt_writes(dev_priv);
-
 		intel_fb_obj_flush(obj,
 				   fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
 
@@ -386,6 +384,7 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 			if (vma->iomap)
 				continue;
 
+			intel_gt_flush_ggtt_writes(vma->vm->gt);
 			i915_vma_unset_ggtt_write(vma);
 		}
 		break;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index b92809418729..b46d57967bfa 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -6,6 +6,7 @@
 
 #include <linux/prime_numbers.h>
 
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "huge_gem_object.h"
 #include "i915_selftest.h"
@@ -143,7 +144,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj,
 		if (offset >= obj->base.size)
 			continue;
 
-		i915_gem_flush_ggtt_writes(to_i915(obj->base.dev));
+		intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt);
 
 		p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
 		cpu = kmap(p) + offset_in_page(offset);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d5ee3487e180..955503504944 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -147,3 +147,44 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 
 	intel_gt_clear_error_registers(gt, ALL_ENGINES);
 }
+
+void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	intel_wakeref_t wakeref;
+
+	/*
+	 * No actual flushing is required for the GTT write domain for reads
+	 * from the GTT domain. Writes to it "immediately" go to main memory
+	 * as far as we know, so there's no chipset flush. It also doesn't
+	 * land in the GPU render cache.
+	 *
+	 * However, we do have to enforce the order so that all writes through
+	 * the GTT land before any writes to the device, such as updates to
+	 * the GATT itself.
+	 *
+	 * We also have to wait a bit for the writes to land from the GTT.
+	 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
+	 * timing. This issue has only been observed when switching quickly
+	 * between GTT writes and CPU reads from inside the kernel on recent hw,
+	 * and it appears to only affect discrete GTT blocks (i.e. on LLC
+	 * system agents we cannot reproduce this behaviour, until Cannonlake
+	 * that was!).
+	 */
+
+	wmb();
+
+	if (INTEL_INFO(i915)->has_coherent_ggtt)
+		return;
+
+	i915_gem_chipset_flush(i915);
+
+	with_intel_runtime_pm(i915, wakeref) {
+		struct intel_uncore *uncore = gt->uncore;
+
+		spin_lock_irq(&uncore->lock);
+		intel_uncore_posting_read_fw(uncore,
+					     RING_HEAD(RENDER_RING_BASE));
+		spin_unlock_irq(&uncore->lock);
+	}
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index d4f585151527..051d7069db55 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -18,4 +18,6 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt);
 void intel_gt_clear_error_registers(struct intel_gt *gt,
 				    intel_engine_mask_t engine_mask);
 
+void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
+
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1eb203fdee60..4987a048b3d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2648,8 +2648,6 @@ int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
 					 unsigned int flags);
 int i915_gem_evict_vm(struct i915_address_space *vm);
 
-void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
-
 /* belongs in i915_gem_gtt.h */
 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b7f88e2bd7df..4f9aac62a8a4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -233,46 +233,6 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
 			       &args->size, &args->handle);
 }
 
-void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv)
-{
-	intel_wakeref_t wakeref;
-
-	/*
-	 * No actual flushing is required for the GTT write domain for reads
-	 * from the GTT domain. Writes to it "immediately" go to main memory
-	 * as far as we know, so there's no chipset flush. It also doesn't
-	 * land in the GPU render cache.
-	 *
-	 * However, we do have to enforce the order so that all writes through
-	 * the GTT land before any writes to the device, such as updates to
-	 * the GATT itself.
-	 *
-	 * We also have to wait a bit for the writes to land from the GTT.
-	 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
-	 * timing. This issue has only been observed when switching quickly
-	 * between GTT writes and CPU reads from inside the kernel on recent hw,
-	 * and it appears to only affect discrete GTT blocks (i.e. on LLC
-	 * system agents we cannot reproduce this behaviour, until Cannonlake
-	 * that was!).
-	 */
-
-	wmb();
-
-	if (INTEL_INFO(dev_priv)->has_coherent_ggtt)
-		return;
-
-	i915_gem_chipset_flush(dev_priv);
-
-	with_intel_runtime_pm(dev_priv, wakeref) {
-		struct intel_uncore *uncore = &dev_priv->uncore;
-
-		spin_lock_irq(&uncore->lock);
-		intel_uncore_posting_read_fw(uncore,
-					     RING_HEAD(RENDER_RING_BASE));
-		spin_unlock_irq(&uncore->lock);
-	}
-}
-
 static int
 shmem_pread(struct page *page, int offset, int len, char __user *user_data,
 	    bool needs_clflush)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index cb341e4acf99..4f4695c351af 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -23,6 +23,7 @@
  */
 
 #include "gt/intel_engine.h"
+#include "gt/intel_gt.h"
 
 #include "i915_vma.h"
 
@@ -408,7 +409,7 @@ void i915_vma_flush_writes(struct i915_vma *vma)
 	if (!i915_vma_has_ggtt_write(vma))
 		return;
 
-	i915_gem_flush_ggtt_writes(vma->vm->i915);
+	intel_gt_flush_ggtt_writes(vma->vm->gt);
 
 	i915_vma_unset_ggtt_write(vma);
 }
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 2093d08a7569..a67f0e9b4d5f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1195,7 +1195,7 @@ static int igt_ggtt_page(void *arg)
 		iowrite32(n, vaddr + n);
 		io_mapping_unmap_atomic(vaddr);
 	}
-	i915_gem_flush_ggtt_writes(i915);
+	intel_gt_flush_ggtt_writes(ggtt->vm.gt);
 
 	i915_random_reorder(order, count, &prng);
 	for (n = 0; n < count; n++) {
-- 
2.20.1

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[RFC 22/31] drm/i915: Move i915_gem_chipset_flush to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This aligns better with the rest of restructuring.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c  |  5 +++--
 drivers/gpu/drm/i915/gem/i915_gem_phys.c        |  3 ++-
 drivers/gpu/drm/i915/gem/selftests/huge_pages.c |  4 +++-
 drivers/gpu/drm/i915/gt/intel_gt.c              |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.h              | 10 ++++++++--
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c    | 12 ++++++++----
 drivers/gpu/drm/i915/gt/selftest_workarounds.c  |  5 +++--
 drivers/gpu/drm/i915/i915_drv.h                 |  8 --------
 drivers/gpu/drm/i915/i915_gem.c                 |  2 +-
 drivers/gpu/drm/i915/selftests/i915_request.c   | 10 ++++++----
 drivers/gpu/drm/i915/selftests/igt_spinner.c    |  7 +++++--
 drivers/gpu/drm/i915/selftests/igt_spinner.h    |  3 +++
 12 files changed, 43 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 528eea44dccf..4ae25515e63c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -14,6 +14,7 @@
 
 #include "gem/i915_gem_ioctls.h"
 #include "gt/intel_context.h"
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 
 #include "i915_gem_ioctls.h"
@@ -993,7 +994,7 @@ static void reloc_gpu_flush(struct reloc_cache *cache)
 	__i915_gem_object_flush_map(cache->rq->batch->obj, 0, cache->rq_size);
 	i915_gem_object_unpin_map(cache->rq->batch->obj);
 
-	i915_gem_chipset_flush(cache->rq->i915);
+	intel_gt_chipset_flush(cache->rq->engine->gt);
 
 	i915_request_add(cache->rq);
 	cache->rq = NULL;
@@ -1953,7 +1954,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
 	eb->exec = NULL;
 
 	/* Unconditionally flush any chipset caches (for streaming writes). */
-	i915_gem_chipset_flush(eb->i915);
+	intel_gt_chipset_flush(eb->engine->gt);
 	return 0;
 
 err_skip:
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 2deac933cf59..7b900ee4ed8d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -13,6 +13,7 @@
 #include <drm/drm_legacy.h> /* for drm_pci.h! */
 #include <drm/drm_pci.h>
 
+#include "gt/intel_gt.h"
 #include "i915_drv.h"
 #include "i915_gem_object.h"
 #include "i915_scatterlist.h"
@@ -60,7 +61,7 @@ static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 		vaddr += PAGE_SIZE;
 	}
 
-	i915_gem_chipset_flush(to_i915(obj->base.dev));
+	intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
 
 	st = kmalloc(sizeof(*st), GFP_KERNEL);
 	if (!st) {
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 73e667b31cc4..5aa52ed514b7 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -10,6 +10,8 @@
 
 #include "gem/i915_gem_pm.h"
 
+#include "gt/intel_gt.h"
+
 #include "igt_gem_utils.h"
 #include "mock_context.h"
 
@@ -926,7 +928,7 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
 	}
 
 	*cmd = MI_BATCH_BUFFER_END;
-	i915_gem_chipset_flush(i915);
+	intel_gt_chipset_flush(vma->vm->gt);
 
 	i915_gem_object_unpin_map(obj);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 955503504944..5bc460d68c8b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -177,7 +177,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 	if (INTEL_INFO(i915)->has_coherent_ggtt)
 		return;
 
-	i915_gem_chipset_flush(i915);
+	intel_gt_chipset_flush(gt);
 
 	with_intel_runtime_pm(i915, wakeref) {
 		struct intel_uncore *uncore = gt->uncore;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 051d7069db55..8d84716c3b3b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -9,8 +9,7 @@
 
 #include "gt/intel_engine_types.h"
 #include "gt/intel_gt_types.h"
-
-struct drm_i915_private;
+#include "i915_drv.h"
 
 void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915);
 
@@ -20,4 +19,11 @@ void intel_gt_clear_error_registers(struct intel_gt *gt,
 
 void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
 
+static inline void intel_gt_chipset_flush(struct intel_gt *gt)
+{
+	wmb();
+	if (INTEL_GEN(gt->i915) < 6)
+		intel_gtt_chipset_flush();
+}
+
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 45379a63e013..e5edad74257e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -25,6 +25,7 @@
 #include <linux/kthread.h>
 
 #include "gem/i915_gem_context.h"
+#include "gt/intel_gt.h"
 #include "intel_engine_pm.h"
 
 #include "i915_selftest.h"
@@ -43,6 +44,7 @@
 
 struct hang {
 	struct drm_i915_private *i915;
+	struct intel_gt *gt;
 	struct drm_i915_gem_object *hws;
 	struct drm_i915_gem_object *obj;
 	struct i915_gem_context *ctx;
@@ -135,6 +137,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
 	u32 *batch;
 	int err;
 
+	h->gt = engine->gt;
+
 	if (i915_gem_object_is_active(h->obj)) {
 		struct drm_i915_gem_object *obj;
 		void *vaddr;
@@ -242,7 +246,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
 		*batch++ = lower_32_bits(vma->node.start);
 	}
 	*batch++ = MI_BATCH_BUFFER_END; /* not reached */
-	i915_gem_chipset_flush(h->i915);
+	intel_gt_chipset_flush(engine->gt);
 
 	if (rq->engine->emit_init_breadcrumb) {
 		err = rq->engine->emit_init_breadcrumb(rq);
@@ -276,7 +280,7 @@ static u32 hws_seqno(const struct hang *h, const struct i915_request *rq)
 static void hang_fini(struct hang *h)
 {
 	*h->batch = MI_BATCH_BUFFER_END;
-	i915_gem_chipset_flush(h->i915);
+	intel_gt_chipset_flush(h->gt);
 
 	i915_gem_object_unpin_map(h->obj);
 	i915_gem_object_put(h->obj);
@@ -333,7 +337,7 @@ static int igt_hang_sanitycheck(void *arg)
 		i915_request_get(rq);
 
 		*h.batch = MI_BATCH_BUFFER_END;
-		i915_gem_chipset_flush(i915);
+		intel_gt_chipset_flush(engine->gt);
 
 		i915_request_add(rq);
 
@@ -1510,7 +1514,7 @@ static int igt_reset_queue(void *arg)
 		pr_info("%s: Completed %d resets\n", engine->name, count);
 
 		*h.batch = MI_BATCH_BUFFER_END;
-		i915_gem_chipset_flush(i915);
+		intel_gt_chipset_flush(engine->gt);
 
 		i915_request_put(prev);
 
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 93e9579b8a4f..f9813d21fe9d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -5,6 +5,7 @@
  */
 
 #include "gem/i915_gem_pm.h"
+#include "gt/intel_gt.h"
 #include "i915_selftest.h"
 #include "intel_reset.h"
 
@@ -516,7 +517,7 @@ static int check_dirty_whitelist(struct i915_gem_context *ctx,
 
 		i915_gem_object_flush_map(batch->obj);
 		i915_gem_object_unpin_map(batch->obj);
-		i915_gem_chipset_flush(ctx->i915);
+		intel_gt_chipset_flush(engine->gt);
 
 		rq = igt_request_alloc(ctx, engine);
 		if (IS_ERR(rq)) {
@@ -771,7 +772,7 @@ static int scrub_whitelisted_registers(struct i915_gem_context *ctx,
 	*cs++ = MI_BATCH_BUFFER_END;
 
 	i915_gem_object_flush_map(batch->obj);
-	i915_gem_chipset_flush(ctx->i915);
+	intel_gt_chipset_flush(engine->gt);
 
 	rq = igt_request_alloc(ctx, engine);
 	if (IS_ERR(rq)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4987a048b3d3..cd5f7ba28f87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2648,14 +2648,6 @@ int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
 					 unsigned int flags);
 int i915_gem_evict_vm(struct i915_address_space *vm);
 
-/* belongs in i915_gem_gtt.h */
-static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
-{
-	wmb();
-	if (INTEL_GEN(dev_priv) < 6)
-		intel_gtt_chipset_flush();
-}
-
 /* i915_gem_stolen.c */
 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
 				struct drm_mm_node *node, u64 size,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4f9aac62a8a4..b0cfcda67984 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -142,7 +142,7 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 		return -EFAULT;
 
 	drm_clflush_virt_range(vaddr, args->size);
-	i915_gem_chipset_flush(to_i915(obj->base.dev));
+	intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
 
 	intel_fb_obj_flush(obj, ORIGIN_CPU);
 	return 0;
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index 11278bac3a24..158e927a8fce 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -27,6 +27,8 @@
 #include "gem/i915_gem_pm.h"
 #include "gem/selftests/mock_context.h"
 
+#include "gt/intel_gt.h"
+
 #include "i915_random.h"
 #include "i915_selftest.h"
 #include "igt_live_test.h"
@@ -624,7 +626,7 @@ static struct i915_vma *empty_batch(struct drm_i915_private *i915)
 	__i915_gem_object_flush_map(obj, 0, 64);
 	i915_gem_object_unpin_map(obj);
 
-	i915_gem_chipset_flush(i915);
+	intel_gt_chipset_flush(&i915->gt);
 
 	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
 	if (IS_ERR(vma)) {
@@ -797,7 +799,7 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
 	__i915_gem_object_flush_map(obj, 0, 64);
 	i915_gem_object_unpin_map(obj);
 
-	i915_gem_chipset_flush(i915);
+	intel_gt_chipset_flush(&i915->gt);
 
 	return vma;
 
@@ -815,7 +817,7 @@ static int recursive_batch_resolve(struct i915_vma *batch)
 		return PTR_ERR(cmd);
 
 	*cmd = MI_BATCH_BUFFER_END;
-	i915_gem_chipset_flush(batch->vm->i915);
+	intel_gt_chipset_flush(batch->vm->gt);
 
 	i915_gem_object_unpin_map(batch->obj);
 
@@ -1039,7 +1041,7 @@ static int live_sequential_engines(void *arg)
 					      I915_MAP_WC);
 		if (!IS_ERR(cmd)) {
 			*cmd = MI_BATCH_BUFFER_END;
-			i915_gem_chipset_flush(i915);
+			intel_gt_chipset_flush(engine->gt);
 
 			i915_gem_object_unpin_map(request[id]->batch->obj);
 		}
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 1e59b543cf27..0c1f65262a63 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -3,6 +3,7 @@
  *
  * Copyright © 2018 Intel Corporation
  */
+#include "gt/intel_gt.h"
 
 #include "gem/selftests/igt_gem_utils.h"
 
@@ -94,6 +95,8 @@ igt_spinner_create_request(struct igt_spinner *spin,
 	u32 *batch;
 	int err;
 
+	spin->gt = engine->gt;
+
 	vma = i915_vma_instance(spin->obj, ctx->vm, NULL);
 	if (IS_ERR(vma))
 		return ERR_CAST(vma);
@@ -138,7 +141,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
 	*batch++ = upper_32_bits(vma->node.start);
 	*batch++ = MI_BATCH_BUFFER_END; /* not reached */
 
-	i915_gem_chipset_flush(spin->i915);
+	intel_gt_chipset_flush(engine->gt);
 
 	if (engine->emit_init_breadcrumb &&
 	    rq->timeline->has_initial_breadcrumb) {
@@ -172,7 +175,7 @@ hws_seqno(const struct igt_spinner *spin, const struct i915_request *rq)
 void igt_spinner_end(struct igt_spinner *spin)
 {
 	*spin->batch = MI_BATCH_BUFFER_END;
-	i915_gem_chipset_flush(spin->i915);
+	intel_gt_chipset_flush(spin->gt);
 }
 
 void igt_spinner_fini(struct igt_spinner *spin)
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.h b/drivers/gpu/drm/i915/selftests/igt_spinner.h
index 34a88ac9b47a..1bfc39efa773 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.h
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.h
@@ -14,8 +14,11 @@
 #include "i915_request.h"
 #include "i915_selftest.h"
 
+struct intel_gt;
+
 struct igt_spinner {
 	struct drm_i915_private *i915;
+	struct intel_gt *gt;
 	struct drm_i915_gem_object *hws;
 	struct drm_i915_gem_object *obj;
 	u32 *batch;
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[RFC 23/31] drm/i915: Compartmentalize timeline_init/park/fini

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing on the theme of better logical organization of our code, make
the first step towards making the timeline code better isolated from wider
struct drm_i915_private.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_timeline.c | 67 +++++++++++++++++-----------
 1 file changed, 41 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_timeline.c b/drivers/gpu/drm/i915/i915_timeline.c
index 000e1a9b6750..4f1b696be42a 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -262,18 +262,23 @@ int i915_timeline_init(struct drm_i915_private *i915,
 	return 0;
 }
 
-void i915_timelines_init(struct drm_i915_private *i915)
+static void timelines_init(struct intel_gt *gt)
 {
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
+	struct i915_gt_timelines *timelines = &gt->timelines;
 
-	mutex_init(&gt->mutex);
-	INIT_LIST_HEAD(&gt->active_list);
+	mutex_init(&timelines->mutex);
+	INIT_LIST_HEAD(&timelines->active_list);
 
-	spin_lock_init(&gt->hwsp_lock);
-	INIT_LIST_HEAD(&gt->hwsp_free_list);
+	spin_lock_init(&timelines->hwsp_lock);
+	INIT_LIST_HEAD(&timelines->hwsp_free_list);
 
 	/* via i915_gem_wait_for_idle() */
-	i915_gem_shrinker_taints_mutex(i915, &gt->mutex);
+	i915_gem_shrinker_taints_mutex(gt->i915, &timelines->mutex);
+}
+
+void i915_timelines_init(struct drm_i915_private *i915)
+{
+	timelines_init(&i915->gt);
 }
 
 static void timeline_add_to_active(struct i915_timeline *tl)
@@ -294,6 +299,24 @@ static void timeline_remove_from_active(struct i915_timeline *tl)
 	mutex_unlock(&gt->mutex);
 }
 
+static void timelines_park(struct intel_gt *gt)
+{
+	struct i915_gt_timelines *timelines = &gt->timelines;
+	struct i915_timeline *timeline;
+
+	mutex_lock(&timelines->mutex);
+	list_for_each_entry(timeline, &timelines->active_list, link) {
+		/*
+		 * All known fences are completed so we can scrap
+		 * the current sync point tracking and start afresh,
+		 * any attempt to wait upon a previous sync point
+		 * will be skipped as the fence was signaled.
+		 */
+		i915_syncmap_free(&timeline->sync);
+	}
+	mutex_unlock(&timelines->mutex);
+}
+
 /**
  * i915_timelines_park - called when the driver idles
  * @i915: the drm_i915_private device
@@ -306,20 +329,7 @@ static void timeline_remove_from_active(struct i915_timeline *tl)
  */
 void i915_timelines_park(struct drm_i915_private *i915)
 {
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
-	struct i915_timeline *timeline;
-
-	mutex_lock(&gt->mutex);
-	list_for_each_entry(timeline, &gt->active_list, link) {
-		/*
-		 * All known fences are completed so we can scrap
-		 * the current sync point tracking and start afresh,
-		 * any attempt to wait upon a previous sync point
-		 * will be skipped as the fence was signaled.
-		 */
-		i915_syncmap_free(&timeline->sync);
-	}
-	mutex_unlock(&gt->mutex);
+	timelines_park(&i915->gt);
 }
 
 void i915_timeline_fini(struct i915_timeline *timeline)
@@ -564,14 +574,19 @@ void __i915_timeline_free(struct kref *kref)
 	kfree(timeline);
 }
 
-void i915_timelines_fini(struct drm_i915_private *i915)
+static void timelines_fini(struct intel_gt *gt)
 {
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
+	struct i915_gt_timelines *timelines = &gt->timelines;
 
-	GEM_BUG_ON(!list_empty(&gt->active_list));
-	GEM_BUG_ON(!list_empty(&gt->hwsp_free_list));
+	GEM_BUG_ON(!list_empty(&timelines->active_list));
+	GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
 
-	mutex_destroy(&gt->mutex);
+	mutex_destroy(&timelines->mutex);
+}
+
+void i915_timelines_fini(struct drm_i915_private *i915)
+{
+	timelines_fini(&i915->gt);
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
-- 
2.20.1

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[RFC 24/31] drm/i915: Compartmentalize i915_ggtt_cleanup_hw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing on the theme of better logical organization of our code, make
the first step towards making the ggtt code better isolated from wider
struct drm_i915_private.

v2:
 * Cleanup of mm.wc_stash does not need struct_mutex. (Chris)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 55 ++++++++++++++++-------------
 1 file changed, 31 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 516ffc4a521a..aa1e3a7f5a83 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2825,14 +2825,19 @@ static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
 	struct i915_ggtt *ggtt = &i915->ggtt;
 	struct i915_ppgtt *ppgtt;
 
+	mutex_lock(&i915->drm.struct_mutex);
+
 	ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt);
 	if (!ppgtt)
-		return;
+		goto out;
 
 	i915_vm_put(&ppgtt->vm);
 
 	ggtt->vm.vma_ops.bind_vma   = ggtt_bind_vma;
 	ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
+
+out:
+	mutex_unlock(&i915->drm.struct_mutex);
 }
 
 static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
@@ -2933,20 +2938,14 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
-/**
- * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
- * @dev_priv: i915 device
- */
-void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
+static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
+	struct drm_i915_private *i915 = ggtt->vm.i915;
 	struct i915_vma *vma, *vn;
-	struct pagevec *pvec;
 
 	ggtt->vm.closed = true;
 
-	mutex_lock(&dev_priv->drm.struct_mutex);
-	fini_aliasing_ppgtt(dev_priv);
+	mutex_lock(&i915->drm.struct_mutex);
 
 	list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
 		WARN_ON(i915_vma_unbind(vma));
@@ -2963,18 +2962,31 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
 
 	ggtt->vm.cleanup(&ggtt->vm);
 
-	pvec = &dev_priv->mm.wc_stash.pvec;
+	mutex_unlock(&i915->drm.struct_mutex);
+
+	arch_phys_wc_del(ggtt->mtrr);
+	io_mapping_fini(&ggtt->iomap);
+}
+
+/**
+ * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
+ * @dev_priv: i915 device
+ */
+void i915_ggtt_cleanup_hw(struct drm_i915_private *i915)
+{
+	struct pagevec *pvec;
+
+	fini_aliasing_ppgtt(i915);
+
+	ggtt_cleanup_hw(&i915->ggtt);
+
+	pvec = &i915->mm.wc_stash.pvec;
 	if (pvec->nr) {
 		set_pages_array_wb(pvec->pages, pvec->nr);
 		__pagevec_release(pvec);
 	}
 
-	mutex_unlock(&dev_priv->drm.struct_mutex);
-
-	arch_phys_wc_del(ggtt->mtrr);
-	io_mapping_fini(&ggtt->iomap);
-
-	i915_gem_cleanup_stolen(dev_priv);
+	i915_gem_cleanup_stolen(i915);
 }
 
 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3570,11 +3582,6 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 	return 0;
 }
 
-static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
-{
-	ggtt->vm.cleanup(&ggtt->vm);
-}
-
 static int ggtt_init_hw(struct i915_ggtt *ggtt)
 {
 	struct drm_i915_private *i915 = ggtt->vm.i915;
@@ -3595,7 +3602,7 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
 	if (!io_mapping_init_wc(&ggtt->iomap,
 				ggtt->gmadr.start,
 				ggtt->mappable_end)) {
-		ggtt_cleanup_hw(ggtt);
+		ggtt->vm.cleanup(&ggtt->vm);
 		ret = -EIO;
 		goto out;
 	}
@@ -3640,7 +3647,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
 	return 0;
 
 out_gtt_cleanup:
-	ggtt_cleanup_hw(&dev_priv->ggtt);
+	dev_priv->ggtt.vm.cleanup(&dev_priv->ggtt.vm);
 	return ret;
 }
 
-- 
2.20.1

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[RFC 25/31] drm/i915: Compartmentalize i915_gem_init_ggtt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing on the theme of better logical organization of our code, make
the first step towards making the ggtt code better isolated from wider
struct drm_i915_private.

v2:
 * Bring the ickle onion unwind back. (Chris)
 * Rename to i915_init_ggtt. (Chris)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c     |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++++----------
 drivers/gpu/drm/i915/i915_gem_gtt.h |  2 +-
 3 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b0cfcda67984..248b473c3bee 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1512,7 +1512,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
 
-	ret = i915_gem_init_ggtt(dev_priv);
+	ret = i915_init_ggtt(dev_priv);
 	if (ret) {
 		GEM_BUG_ON(ret == -EIO);
 		goto err_unlock;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index aa1e3a7f5a83..f97f30031d47 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2866,7 +2866,13 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
 		drm_mm_remove_node(&ggtt->uc_fw);
 }
 
-int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
+static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
+{
+	ggtt_release_guc_top(ggtt);
+	drm_mm_remove_node(&ggtt->error_capture);
+}
+
+static int init_ggtt(struct i915_ggtt *ggtt)
 {
 	/* Let GEM Manage all of the aperture.
 	 *
@@ -2877,7 +2883,6 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	 * aperture.  One page should be enough to keep any prefetching inside
 	 * of the aperture.
 	 */
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 	unsigned long hole_start, hole_end;
 	struct drm_mm_node *entry;
 	int ret;
@@ -2889,7 +2894,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	 * why.
 	 */
 	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
-			       intel_wopcm_guc_size(&dev_priv->wopcm));
+			       intel_wopcm_guc_size(&ggtt->vm.i915->wopcm));
 
 	ret = intel_vgt_balloon(ggtt);
 	if (ret)
@@ -2910,7 +2915,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	 */
 	ret = ggtt_reserve_guc_top(ggtt);
 	if (ret)
-		goto err_reserve;
+		goto err;
 
 	/* Clear any non-preallocated blocks */
 	drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
@@ -2923,19 +2928,28 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
-		ret = init_aliasing_ppgtt(dev_priv);
+	return 0;
+
+err:
+	cleanup_init_ggtt(ggtt);
+	return ret;
+}
+
+int i915_init_ggtt(struct drm_i915_private *i915)
+{
+	int ret;
+
+	ret = init_ggtt(&i915->ggtt);
+	if (ret)
+		return ret;
+
+	if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
+		ret = init_aliasing_ppgtt(i915);
 		if (ret)
-			goto err_appgtt;
+			cleanup_init_ggtt(&i915->ggtt);
 	}
 
 	return 0;
-
-err_appgtt:
-	ggtt_release_guc_top(ggtt);
-err_reserve:
-	drm_mm_remove_node(&ggtt->error_capture);
-	return ret;
 }
 
 static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 9a3d96370f07..827af6ba36c7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -646,7 +646,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
 void i915_ggtt_enable_guc(struct drm_i915_private *i915);
 void i915_ggtt_disable_guc(struct drm_i915_private *i915);
-int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
+int i915_init_ggtt(struct drm_i915_private *dev_priv);
 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
 
 int i915_ppgtt_init_hw(struct intel_gt *gt);
-- 
2.20.1

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[RFC 26/31] drm/i915: Store ggtt pointer in intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This will become useful in the following patch.

v2:
 * Assign the pointer through a helper on the top level to work around
   the layering violation. (Chris)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c       | 5 +++++
 drivers/gpu/drm/i915/gt/intel_gt.h       | 1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 ++
 drivers/gpu/drm/i915/i915_drv.c          | 2 ++
 4 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5bc460d68c8b..6746c40c2132 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -20,6 +20,11 @@ void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915)
 	spin_lock_init(&gt->closed_lock);
 }
 
+void intel_gt_init_hw(struct drm_i915_private *i915)
+{
+	i915->gt.ggtt = &i915->ggtt;
+}
+
 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 {
 	intel_uncore_rmw(uncore, reg, 0, set);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 8d84716c3b3b..53fcf4f276d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -12,6 +12,7 @@
 #include "i915_drv.h"
 
 void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915);
+void intel_gt_init_hw(struct drm_i915_private *i915);
 
 void intel_gt_check_and_clear_faults(struct intel_gt *gt);
 void intel_gt_clear_error_registers(struct intel_gt *gt,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index d96df4f68741..233f73316a43 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -18,11 +18,13 @@
 #include "intel_wakeref.h"
 
 struct drm_i915_private;
+struct i915_ggtt;
 struct intel_uncore;
 
 struct intel_gt {
 	struct drm_i915_private *i915;
 	struct intel_uncore *uncore;
+	struct i915_ggtt *ggtt;
 
 	struct i915_gt_timelines {
 		struct mutex mutex; /* protects list, tainted by GPU */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1df76f7c717e..783cbbda75fb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1584,6 +1584,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 	if (ret)
 		goto err_ggtt;
 
+	intel_gt_init_hw(dev_priv);
+
 	ret = i915_ggtt_enable_hw(dev_priv);
 	if (ret) {
 		DRM_ERROR("failed to enable GGTT\n");
-- 
2.20.1

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[RFC 27/31] drm/i915: Compartmentalize ring buffer creation

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing on the theme of compartmentalizing the code better to make
future split between gt and display in global i915 clearer.

v2:
 * Pass in ggtt instead of gt. (Chris)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index b3bf47e8162f..894122d23dda 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -1226,16 +1226,16 @@ void intel_ring_unpin(struct intel_ring *ring)
 	i915_timeline_unpin(ring->timeline);
 }
 
-static struct i915_vma *
-intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
+static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
 {
-	struct i915_address_space *vm = &dev_priv->ggtt.vm;
+	struct i915_address_space *vm = &ggtt->vm;
+	struct drm_i915_private *i915 = vm->i915;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 
-	obj = i915_gem_object_create_stolen(dev_priv, size);
+	obj = i915_gem_object_create_stolen(i915, size);
 	if (!obj)
-		obj = i915_gem_object_create_internal(dev_priv, size);
+		obj = i915_gem_object_create_internal(i915, size);
 	if (IS_ERR(obj))
 		return ERR_CAST(obj);
 
@@ -1262,13 +1262,14 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
 			 struct i915_timeline *timeline,
 			 int size)
 {
+	struct drm_i915_private *i915 = engine->i915;
 	struct intel_ring *ring;
 	struct i915_vma *vma;
 
 	GEM_BUG_ON(!is_power_of_2(size));
 	GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
 	GEM_BUG_ON(timeline == &engine->timeline);
-	lockdep_assert_held(&engine->i915->drm.struct_mutex);
+	lockdep_assert_held(&i915->drm.struct_mutex);
 
 	ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 	if (!ring)
@@ -1284,12 +1285,12 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
 	 * of the buffer.
 	 */
 	ring->effective_size = size;
-	if (IS_I830(engine->i915) || IS_I845G(engine->i915))
+	if (IS_I830(i915) || IS_I845G(i915))
 		ring->effective_size -= 2 * CACHELINE_BYTES;
 
 	intel_ring_update_space(ring);
 
-	vma = intel_ring_create_vma(engine->i915, size);
+	vma = create_ring_vma(engine->gt->ggtt, size);
 	if (IS_ERR(vma)) {
 		kfree(ring);
 		return ERR_CAST(vma);
-- 
2.20.1

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[RFC 28/31] drm/i915: Save trip via top-level i915 in a few more places

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

For gt related operations it makes more logical sense to stay in the realm
of gt instead of dereferencing via driver i915.

This patch handles a few of the easy ones with work requiring more
refactoring still outstanding.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gem/selftests/huge_pages.c       | 3 +--
 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 3 +--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c             | 2 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c                   | 4 ++--
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c            | 2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c           | 2 +-
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c          | 8 ++++----
 drivers/gpu/drm/i915/gt/selftest_workarounds.c        | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c                   | 4 ++--
 drivers/gpu/drm/i915/i915_gem_render_state.c          | 2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c                 | 2 +-
 11 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 5aa52ed514b7..f197a55dd32a 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1039,8 +1039,7 @@ static int __igt_write_huge(struct i915_gem_context *ctx,
 			    u64 size, u64 offset,
 			    u32 dword, u32 val)
 {
-	struct drm_i915_private *i915 = to_i915(obj->base.dev);
-	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
+	struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
 	unsigned int flags = PIN_USER | PIN_OFFSET_FIXED;
 	struct i915_vma *vma;
 	int err;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 9e2878a59023..496c9c353aee 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -241,8 +241,7 @@ static int gpu_fill(struct drm_i915_gem_object *obj,
 		    struct intel_engine_cs *engine,
 		    unsigned int dw)
 {
-	struct drm_i915_private *i915 = to_i915(obj->base.dev);
-	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
+	struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
 	struct i915_request *rq;
 	struct i915_vma *vma;
 	struct i915_vma *batch;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c2d87c50dd6f..ab9c5141ee0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -580,7 +580,7 @@ static int init_status_page(struct intel_engine_cs *engine)
 
 	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
 
-	vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
+	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
 	if (IS_ERR(vma)) {
 		ret = PTR_ERR(vma);
 		goto err;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b8f5592da18f..68c6f11a03c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1926,7 +1926,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
 	if (IS_ERR(obj))
 		return PTR_ERR(obj);
 
-	vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
+	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
 	if (IS_ERR(vma)) {
 		err = PTR_ERR(vma);
 		goto err;
@@ -3017,7 +3017,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ce,
 	if (IS_ERR(ctx_obj))
 		return PTR_ERR(ctx_obj);
 
-	vma = i915_vma_instance(ctx_obj, &engine->i915->ggtt.vm, NULL);
+	vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
 	if (IS_ERR(vma)) {
 		ret = PTR_ERR(vma);
 		goto error_deref_obj;
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index 894122d23dda..f74872cca686 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -1444,7 +1444,7 @@ alloc_context_vma(struct intel_engine_cs *engine)
 		i915_gem_object_unpin_map(obj);
 	}
 
-	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
 	if (IS_ERR(vma)) {
 		err = PTR_ERR(vma);
 		goto err_obj;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0b3308e39a17..c9e929285bc8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1369,7 +1369,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
 	if (!wal->count)
 		return 0;
 
-	vma = create_scratch(&ce->engine->i915->ggtt.vm, wal->count);
+	vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
 	if (IS_ERR(vma))
 		return PTR_ERR(vma);
 
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index e5edad74257e..c6b2737cecca 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -130,7 +130,7 @@ static struct i915_request *
 hang_create_request(struct hang *h, struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *i915 = h->i915;
-	struct i915_address_space *vm = h->ctx->vm ?: &i915->ggtt.vm;
+	struct i915_address_space *vm = h->ctx->vm ?: &engine->gt->ggtt->vm;
 	struct i915_request *rq = NULL;
 	struct i915_vma *hws, *vma;
 	unsigned int flags;
@@ -143,12 +143,12 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
 		struct drm_i915_gem_object *obj;
 		void *vaddr;
 
-		obj = i915_gem_object_create_internal(h->i915, PAGE_SIZE);
+		obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
 		if (IS_ERR(obj))
 			return ERR_CAST(obj);
 
 		vaddr = i915_gem_object_pin_map(obj,
-						i915_coherent_map_type(h->i915));
+						i915_coherent_map_type(i915));
 		if (IS_ERR(vaddr)) {
 			i915_gem_object_put(obj);
 			return ERR_CAST(vaddr);
@@ -255,7 +255,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
 	}
 
 	flags = 0;
-	if (INTEL_GEN(vm->i915) <= 5)
+	if (INTEL_GEN(i915) <= 5)
 		flags |= I915_DISPATCH_SECURE;
 
 	err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index f9813d21fe9d..f9982da4a40f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -103,7 +103,7 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
 	i915_gem_object_flush_map(result);
 	i915_gem_object_unpin_map(result);
 
-	vma = i915_vma_instance(result, &engine->i915->ggtt.vm, NULL);
+	vma = i915_vma_instance(result, &engine->gt->ggtt->vm, NULL);
 	if (IS_ERR(vma)) {
 		err = PTR_ERR(vma);
 		goto err_obj;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f97f30031d47..35be61aad1e5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1873,7 +1873,7 @@ static int gen6_alloc_va_range(struct i915_address_space *vm,
 
 	if (flush) {
 		mark_tlbs_dirty(&ppgtt->base);
-		gen6_ggtt_invalidate(&vm->i915->ggtt);
+		gen6_ggtt_invalidate(vm->gt->ggtt);
 	}
 
 	intel_runtime_pm_put(vm->i915, wakeref);
@@ -2059,7 +2059,7 @@ static const struct i915_vma_ops pd_vma_ops = {
 static struct i915_vma *pd_vma_create(struct gen6_ppgtt *ppgtt, int size)
 {
 	struct drm_i915_private *i915 = ppgtt->base.vm.i915;
-	struct i915_ggtt *ggtt = &i915->ggtt;
+	struct i915_ggtt *ggtt = ppgtt->base.vm.gt->ggtt;
 	struct i915_vma *vma;
 
 	GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 4ee032072d4f..6bda08c1e8d7 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -194,7 +194,7 @@ int i915_gem_render_state_emit(struct i915_request *rq)
 	if (IS_ERR(so.obj))
 		return PTR_ERR(so.obj);
 
-	so.vma = i915_vma_instance(so.obj, &engine->i915->ggtt.vm, NULL);
+	so.vma = i915_vma_instance(so.obj, &engine->gt->ggtt->vm, NULL);
 	if (IS_ERR(so.vma)) {
 		err = PTR_ERR(so.vma);
 		goto err_obj;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 26c9c0595bdf..d0f9b4aba241 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1408,12 +1408,12 @@ capture_object(struct drm_i915_private *dev_priv,
 static void gem_record_rings(struct i915_gpu_state *error)
 {
 	struct drm_i915_private *i915 = error->i915;
-	struct i915_ggtt *ggtt = &i915->ggtt;
 	int i;
 
 	for (i = 0; i < I915_NUM_ENGINES; i++) {
 		struct intel_engine_cs *engine = i915->engine[i];
 		struct drm_i915_error_engine *ee = &error->engine[i];
+		struct i915_ggtt *ggtt = engine->gt->ggtt;
 		struct i915_request *request;
 
 		ee->engine_id = -1;
-- 
2.20.1

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[RFC 29/31] drm/i915: Make timelines gt centric

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Our timelines are stored inside intel_gt so we can convert the interface
to take exactly that and not i915.

At the same time re-order the params to our more typical layout and
replace the backpointer to the new containing structure.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  8 ++--
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  9 ++--
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c    |  2 +-
 drivers/gpu/drm/i915/gt/mock_engine.c         |  4 +-
 drivers/gpu/drm/i915/i915_timeline.c          | 43 +++++++++----------
 drivers/gpu/drm/i915/i915_timeline.h          |  7 ++-
 drivers/gpu/drm/i915/i915_timeline_types.h    |  2 +-
 .../gpu/drm/i915/selftests/i915_timeline.c    |  8 ++--
 .../gpu/drm/i915/selftests/mock_timeline.c    |  2 +-
 10 files changed, 42 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c86ca9f21532..c52869e58cb5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -530,7 +530,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv, unsigned int flags)
 	if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
 		struct i915_timeline *timeline;
 
-		timeline = i915_timeline_create(dev_priv, NULL);
+		timeline = i915_timeline_create(&dev_priv->gt, NULL);
 		if (IS_ERR(timeline)) {
 			context_close(ctx);
 			return ERR_CAST(timeline);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ab9c5141ee0c..3aec009bee23 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -618,8 +618,8 @@ static int intel_engine_setup_common(struct intel_engine_cs *engine)
 	if (err)
 		return err;
 
-	err = i915_timeline_init(engine->i915,
-				 &engine->timeline,
+	err = i915_timeline_init(&engine->timeline,
+				 engine->gt,
 				 engine->status_page.vma);
 	if (err)
 		goto err_hwsp;
@@ -745,8 +745,8 @@ static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
 	if (!frame)
 		return -ENOMEM;
 
-	if (i915_timeline_init(engine->i915,
-			       &frame->timeline,
+	if (i915_timeline_init(&frame->timeline,
+			       engine->gt,
 			       engine->status_page.vma))
 		goto out_frame;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 68c6f11a03c5..0a49949c0599 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2984,12 +2984,13 @@ populate_lr_context(struct intel_context *ce,
 	return ret;
 }
 
-static struct i915_timeline *get_timeline(struct i915_gem_context *ctx)
+static struct i915_timeline *
+get_timeline(struct i915_gem_context *ctx, struct intel_gt *gt)
 {
 	if (ctx->timeline)
 		return i915_timeline_get(ctx->timeline);
 	else
-		return i915_timeline_create(ctx->i915, NULL);
+		return i915_timeline_create(gt, NULL);
 }
 
 static int execlists_context_deferred_alloc(struct intel_context *ce,
@@ -3023,7 +3024,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ce,
 		goto error_deref_obj;
 	}
 
-	timeline = get_timeline(ce->gem_context);
+	timeline = get_timeline(ce->gem_context, engine->gt);
 	if (IS_ERR(timeline)) {
 		ret = PTR_ERR(timeline);
 		goto error_deref_obj;
@@ -3343,7 +3344,7 @@ intel_execlists_create_virtual(struct i915_gem_context *ctx,
 
 	snprintf(ve->base.name, sizeof(ve->base.name), "virtual");
 
-	err = i915_timeline_init(ctx->i915, &ve->base.timeline, NULL);
+	err = i915_timeline_init(&ve->base.timeline, siblings[0]->gt, NULL);
 	if (err)
 		goto err_put;
 	i915_timeline_set_subclass(&ve->base.timeline, TIMELINE_VIRTUAL);
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index f74872cca686..d244ad68da7e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -2302,7 +2302,7 @@ int intel_ring_submission_init(struct intel_engine_cs *engine)
 	struct intel_ring *ring;
 	int err;
 
-	timeline = i915_timeline_create(engine->i915, engine->status_page.vma);
+	timeline = i915_timeline_create(engine->gt, engine->status_page.vma);
 	if (IS_ERR(timeline)) {
 		err = PTR_ERR(timeline);
 		goto err;
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
index 6d7562769eb2..0ebe78ada05b 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -56,7 +56,7 @@ static struct intel_ring *mock_ring(struct intel_engine_cs *engine)
 	if (!ring)
 		return NULL;
 
-	if (i915_timeline_init(engine->i915, &ring->timeline, NULL)) {
+	if (i915_timeline_init(&ring->timeline, engine->gt, NULL)) {
 		kfree(ring);
 		return NULL;
 	}
@@ -283,7 +283,7 @@ int mock_engine_init(struct intel_engine_cs *engine)
 	intel_engine_init_execlists(engine);
 	intel_engine_init__pm(engine);
 
-	if (i915_timeline_init(i915, &engine->timeline, NULL))
+	if (i915_timeline_init(&engine->timeline, engine->gt, NULL))
 		goto err_breadcrumbs;
 	i915_timeline_set_subclass(&engine->timeline, TIMELINE_ENGINE);
 
diff --git a/drivers/gpu/drm/i915/i915_timeline.c b/drivers/gpu/drm/i915/i915_timeline.c
index 4f1b696be42a..9b62f14ccc07 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -4,6 +4,8 @@
  * Copyright © 2016-2018 Intel Corporation
  */
 
+#include "gt/intel_gt_types.h"
+
 #include "i915_drv.h"
 
 #include "i915_active.h"
@@ -14,7 +16,8 @@
 #define ptr_test_bit(ptr, bit) ((unsigned long)(ptr) & BIT(bit))
 
 struct i915_timeline_hwsp {
-	struct i915_gt_timelines *gt;
+	struct intel_gt *gt;
+	struct i915_gt_timelines *gt_timelines;
 	struct list_head free_link;
 	struct i915_vma *vma;
 	u64 free_bitmap;
@@ -28,14 +31,9 @@ struct i915_timeline_cacheline {
 #define CACHELINE_FREE CACHELINE_BITS
 };
 
-static inline struct drm_i915_private *
-hwsp_to_i915(struct i915_timeline_hwsp *hwsp)
-{
-	return container_of(hwsp->gt, struct drm_i915_private, gt.timelines);
-}
-
-static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
+static struct i915_vma *__hwsp_alloc(struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 
@@ -45,7 +43,7 @@ static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
 
 	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
 
-	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 	if (IS_ERR(vma))
 		i915_gem_object_put(obj);
 
@@ -55,8 +53,7 @@ static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
 static struct i915_vma *
 hwsp_alloc(struct i915_timeline *timeline, unsigned int *cacheline)
 {
-	struct drm_i915_private *i915 = timeline->i915;
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
+	struct i915_gt_timelines *gt = &timeline->gt->timelines;
 	struct i915_timeline_hwsp *hwsp;
 
 	BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
@@ -75,16 +72,17 @@ hwsp_alloc(struct i915_timeline *timeline, unsigned int *cacheline)
 		if (!hwsp)
 			return ERR_PTR(-ENOMEM);
 
-		vma = __hwsp_alloc(i915);
+		vma = __hwsp_alloc(timeline->gt);
 		if (IS_ERR(vma)) {
 			kfree(hwsp);
 			return vma;
 		}
 
 		vma->private = hwsp;
+		hwsp->gt = timeline->gt;
 		hwsp->vma = vma;
 		hwsp->free_bitmap = ~0ull;
-		hwsp->gt = gt;
+		hwsp->gt_timelines = gt;
 
 		spin_lock_irq(&gt->hwsp_lock);
 		list_add(&hwsp->free_link, &gt->hwsp_free_list);
@@ -104,7 +102,7 @@ hwsp_alloc(struct i915_timeline *timeline, unsigned int *cacheline)
 
 static void __idle_hwsp_free(struct i915_timeline_hwsp *hwsp, int cacheline)
 {
-	struct i915_gt_timelines *gt = hwsp->gt;
+	struct i915_gt_timelines *gt = hwsp->gt_timelines;
 	unsigned long flags;
 
 	spin_lock_irqsave(&gt->hwsp_lock, flags);
@@ -170,7 +168,7 @@ cacheline_alloc(struct i915_timeline_hwsp *hwsp, unsigned int cacheline)
 	cl->hwsp = hwsp;
 	cl->vaddr = page_pack_bits(vaddr, cacheline);
 
-	i915_active_init(hwsp_to_i915(hwsp), &cl->active, __cacheline_retire);
+	i915_active_init(hwsp->gt->i915, &cl->active, __cacheline_retire);
 
 	return cl;
 }
@@ -196,8 +194,8 @@ static void cacheline_free(struct i915_timeline_cacheline *cl)
 		__idle_cacheline_free(cl);
 }
 
-int i915_timeline_init(struct drm_i915_private *i915,
-		       struct i915_timeline *timeline,
+int i915_timeline_init(struct i915_timeline *timeline,
+		       struct intel_gt *gt,
 		       struct i915_vma *hwsp)
 {
 	void *vaddr;
@@ -212,7 +210,7 @@ int i915_timeline_init(struct drm_i915_private *i915,
 	 */
 	BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
 
-	timeline->i915 = i915;
+	timeline->gt = gt;
 	timeline->pin_count = 0;
 	timeline->has_initial_breadcrumb = !hwsp;
 	timeline->hwsp_cacheline = NULL;
@@ -283,7 +281,7 @@ void i915_timelines_init(struct drm_i915_private *i915)
 
 static void timeline_add_to_active(struct i915_timeline *tl)
 {
-	struct i915_gt_timelines *gt = &tl->i915->gt.timelines;
+	struct i915_gt_timelines *gt = &tl->gt->timelines;
 
 	mutex_lock(&gt->mutex);
 	list_add(&tl->link, &gt->active_list);
@@ -292,7 +290,7 @@ static void timeline_add_to_active(struct i915_timeline *tl)
 
 static void timeline_remove_from_active(struct i915_timeline *tl)
 {
-	struct i915_gt_timelines *gt = &tl->i915->gt.timelines;
+	struct i915_gt_timelines *gt = &tl->gt->timelines;
 
 	mutex_lock(&gt->mutex);
 	list_del(&tl->link);
@@ -348,8 +346,7 @@ void i915_timeline_fini(struct i915_timeline *timeline)
 }
 
 struct i915_timeline *
-i915_timeline_create(struct drm_i915_private *i915,
-		     struct i915_vma *global_hwsp)
+i915_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp)
 {
 	struct i915_timeline *timeline;
 	int err;
@@ -358,7 +355,7 @@ i915_timeline_create(struct drm_i915_private *i915,
 	if (!timeline)
 		return ERR_PTR(-ENOMEM);
 
-	err = i915_timeline_init(i915, timeline, global_hwsp);
+	err = i915_timeline_init(timeline, gt, global_hwsp);
 	if (err) {
 		kfree(timeline);
 		return ERR_PTR(err);
diff --git a/drivers/gpu/drm/i915/i915_timeline.h b/drivers/gpu/drm/i915/i915_timeline.h
index 27668a1a69a3..8399e11e68b4 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -31,8 +31,8 @@
 #include "i915_syncmap.h"
 #include "i915_timeline_types.h"
 
-int i915_timeline_init(struct drm_i915_private *i915,
-		       struct i915_timeline *tl,
+int i915_timeline_init(struct i915_timeline *tl,
+		       struct intel_gt *gt,
 		       struct i915_vma *hwsp);
 void i915_timeline_fini(struct i915_timeline *tl);
 
@@ -56,8 +56,7 @@ i915_timeline_set_subclass(struct i915_timeline *timeline,
 }
 
 struct i915_timeline *
-i915_timeline_create(struct drm_i915_private *i915,
-		     struct i915_vma *global_hwsp);
+i915_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp);
 
 static inline struct i915_timeline *
 i915_timeline_get(struct i915_timeline *timeline)
diff --git a/drivers/gpu/drm/i915/i915_timeline_types.h b/drivers/gpu/drm/i915/i915_timeline_types.h
index 1688705f4a2b..041709087508 100644
--- a/drivers/gpu/drm/i915/i915_timeline_types.h
+++ b/drivers/gpu/drm/i915/i915_timeline_types.h
@@ -63,7 +63,7 @@ struct i915_timeline {
 	struct i915_syncmap *sync;
 
 	struct list_head link;
-	struct drm_i915_private *i915;
+	struct intel_gt *gt;
 
 	struct kref kref;
 };
diff --git a/drivers/gpu/drm/i915/selftests/i915_timeline.c b/drivers/gpu/drm/i915/selftests/i915_timeline.c
index acb2cc5136b7..57835127563b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/i915_timeline.c
@@ -66,7 +66,7 @@ static int __mock_hwsp_timeline(struct mock_hwsp_freelist *state,
 		unsigned long cacheline;
 		int err;
 
-		tl = i915_timeline_create(state->i915, NULL);
+		tl = i915_timeline_create(&state->i915->gt, NULL);
 		if (IS_ERR(tl))
 			return PTR_ERR(tl);
 
@@ -448,7 +448,7 @@ tl_write(struct i915_timeline *tl, struct intel_engine_cs *engine, u32 value)
 	struct i915_request *rq;
 	int err;
 
-	lockdep_assert_held(&tl->i915->drm.struct_mutex); /* lazy rq refs */
+	lockdep_assert_held(&tl->gt->i915->drm.struct_mutex); /* lazy rq refs */
 
 	err = i915_timeline_pin(tl);
 	if (err) {
@@ -478,7 +478,7 @@ checked_i915_timeline_create(struct drm_i915_private *i915)
 {
 	struct i915_timeline *tl;
 
-	tl = i915_timeline_create(i915, NULL);
+	tl = i915_timeline_create(&i915->gt, NULL);
 	if (IS_ERR(tl))
 		return tl;
 
@@ -660,7 +660,7 @@ static int live_hwsp_wrap(void *arg)
 	mutex_lock(&i915->drm.struct_mutex);
 	wakeref = intel_runtime_pm_get(i915);
 
-	tl = i915_timeline_create(i915, NULL);
+	tl = i915_timeline_create(&i915->gt, NULL);
 	if (IS_ERR(tl)) {
 		err = PTR_ERR(tl);
 		goto out_rpm;
diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.c b/drivers/gpu/drm/i915/selftests/mock_timeline.c
index e084476469ef..e1a256761d2c 100644
--- a/drivers/gpu/drm/i915/selftests/mock_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/mock_timeline.c
@@ -10,7 +10,7 @@
 
 void mock_timeline_init(struct i915_timeline *timeline, u64 context)
 {
-	timeline->i915 = NULL;
+	timeline->gt = NULL;
 	timeline->fence_context = context;
 
 	spin_lock_init(&timeline->lock);
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[RFC 30/31] drm/i915: Rename i915_timeline to intel_timeline and move under gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Move all timeline code under gt and rename to intel_gt prefix.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/Makefile                 |   2 +-
 drivers/gpu/drm/i915/Makefile.header-test     |   1 -
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |  10 +-
 .../gpu/drm/i915/gem/i915_gem_context_types.h |   4 +-
 drivers/gpu/drm/i915/gem/i915_gem_pm.c        |   2 +-
 drivers/gpu/drm/i915/gt/intel_engine.h        |   4 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  24 ++--
 drivers/gpu/drm/i915/gt/intel_engine_types.h  |   6 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  16 +--
 drivers/gpu/drm/i915/gt/intel_reset.c         |   2 +-
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c    |  20 +--
 .../{i915_timeline.c => gt/intel_timeline.c}  | 108 ++++++++--------
 .../{i915_timeline.h => gt/intel_timeline.h}  |  70 +++++-----
 .../intel_timeline_types.h}                   |   6 +-
 drivers/gpu/drm/i915/gt/mock_engine.c         |  18 +--
 .../selftest_timeline.c}                      | 122 +++++++++---------
 .../i915/{ => gt}/selftests/mock_timeline.c   |   6 +-
 .../i915/{ => gt}/selftests/mock_timeline.h   |   6 +-
 drivers/gpu/drm/i915/i915_drv.h               |   2 +-
 drivers/gpu/drm/i915/i915_gem.c               |   8 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h           |   2 +-
 drivers/gpu/drm/i915/i915_request.c           |  16 +--
 drivers/gpu/drm/i915/i915_request.h           |   8 +-
 .../drm/i915/selftests/i915_live_selftests.h  |   2 +-
 .../drm/i915/selftests/i915_mock_selftests.h  |   2 +-
 .../gpu/drm/i915/selftests/mock_gem_device.c  |   6 +-
 26 files changed, 236 insertions(+), 237 deletions(-)
 rename drivers/gpu/drm/i915/{i915_timeline.c => gt/intel_timeline.c} (82%)
 rename drivers/gpu/drm/i915/{i915_timeline.h => gt/intel_timeline.h} (53%)
 rename drivers/gpu/drm/i915/{i915_timeline_types.h => gt/intel_timeline_types.h} (94%)
 rename drivers/gpu/drm/i915/{selftests/i915_timeline.c => gt/selftest_timeline.c} (87%)
 rename drivers/gpu/drm/i915/{ => gt}/selftests/mock_timeline.c (73%)
 rename drivers/gpu/drm/i915/{ => gt}/selftests/mock_timeline.h (53%)

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8df1bf2855d0..f4f823275aaf 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -81,6 +81,7 @@ gt-y += \
 	gt/intel_ringbuffer.o \
 	gt/intel_mocs.o \
 	gt/intel_sseu.o \
+	gt/intel_timeline.o \
 	gt/intel_workarounds.o
 gt-$(CONFIG_DRM_I915_SELFTEST) += \
 	gt/mock_engine.o
@@ -126,7 +127,6 @@ i915-y += \
 	  i915_query.o \
 	  i915_request.o \
 	  i915_scheduler.o \
-	  i915_timeline.o \
 	  i915_trace_points.o \
 	  i915_vma.o \
 	  intel_wopcm.o
diff --git a/drivers/gpu/drm/i915/Makefile.header-test b/drivers/gpu/drm/i915/Makefile.header-test
index 6ef3b647ac65..f55346d3c27b 100644
--- a/drivers/gpu/drm/i915/Makefile.header-test
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -11,7 +11,6 @@ header_test := \
 	i915_priolist_types.h \
 	i915_reg.h \
 	i915_scheduler_types.h \
-	i915_timeline_types.h \
 	i915_utils.h \
 	intel_acpi.h \
 	intel_atomic.h \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c52869e58cb5..d831bdf752ca 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -316,7 +316,7 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
 	mutex_destroy(&ctx->engines_mutex);
 
 	if (ctx->timeline)
-		i915_timeline_put(ctx->timeline);
+		intel_timeline_put(ctx->timeline);
 
 	kfree(ctx->name);
 	put_pid(ctx->pid);
@@ -528,9 +528,9 @@ i915_gem_create_context(struct drm_i915_private *dev_priv, unsigned int flags)
 	}
 
 	if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
-		struct i915_timeline *timeline;
+		struct intel_timeline *timeline;
 
-		timeline = i915_timeline_create(&dev_priv->gt, NULL);
+		timeline = intel_timeline_create(&dev_priv->gt, NULL);
 		if (IS_ERR(timeline)) {
 			context_close(ctx);
 			return ERR_CAST(timeline);
@@ -2027,8 +2027,8 @@ static int clone_timeline(struct i915_gem_context *dst,
 		GEM_BUG_ON(src->timeline == dst->timeline);
 
 		if (dst->timeline)
-			i915_timeline_put(dst->timeline);
-		dst->timeline = i915_timeline_get(src->timeline);
+			intel_timeline_put(dst->timeline);
+		dst->timeline = intel_timeline_get(src->timeline);
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index cc513410eeef..0ee61482ef94 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -26,7 +26,7 @@ struct pid;
 struct drm_i915_private;
 struct drm_i915_file_private;
 struct i915_address_space;
-struct i915_timeline;
+struct intel_timeline;
 struct intel_ring;
 
 struct i915_gem_engines {
@@ -77,7 +77,7 @@ struct i915_gem_context {
 	struct i915_gem_engines __rcu *engines;
 	struct mutex engines_mutex; /* guards writes to engines */
 
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
 
 	/**
 	 * @vm: unique address space (GTT)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 6e75702c5671..259b95e2e052 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -20,7 +20,7 @@ static void i915_gem_park(struct drm_i915_private *i915)
 	for_each_engine(engine, i915, id)
 		i915_gem_batch_pool_fini(&engine->batch_pool);
 
-	i915_timelines_park(i915);
+	intel_timelines_park(i915);
 	i915_vma_parked(i915);
 
 	i915_globals_park();
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 1439fa4093ac..d3021b7971d0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -14,7 +14,7 @@
 #include "i915_reg.h"
 #include "i915_request.h"
 #include "i915_selftest.h"
-#include "i915_timeline.h"
+#include "gt/intel_timeline.h"
 #include "intel_engine_types.h"
 #include "intel_gpu_commands.h"
 #include "intel_workarounds.h"
@@ -245,7 +245,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 
 struct intel_ring *
 intel_engine_create_ring(struct intel_engine_cs *engine,
-			 struct i915_timeline *timeline,
+			 struct intel_timeline *timeline,
 			 int size);
 int intel_ring_pin(struct intel_ring *ring);
 void intel_ring_reset(struct intel_ring *ring, u32 tail);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3aec009bee23..cd8b22c934c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -618,13 +618,13 @@ static int intel_engine_setup_common(struct intel_engine_cs *engine)
 	if (err)
 		return err;
 
-	err = i915_timeline_init(&engine->timeline,
-				 engine->gt,
-				 engine->status_page.vma);
+	err = intel_timeline_init(&engine->timeline,
+				  engine->gt,
+				  engine->status_page.vma);
 	if (err)
 		goto err_hwsp;
 
-	i915_timeline_set_subclass(&engine->timeline, TIMELINE_ENGINE);
+	intel_timeline_set_subclass(&engine->timeline, TIMELINE_ENGINE);
 
 	intel_engine_init_breadcrumbs(engine);
 	intel_engine_init_execlists(engine);
@@ -729,7 +729,7 @@ void intel_engines_set_scheduler_caps(struct drm_i915_private *i915)
 
 struct measure_breadcrumb {
 	struct i915_request rq;
-	struct i915_timeline timeline;
+	struct intel_timeline timeline;
 	struct intel_ring ring;
 	u32 cs[1024];
 };
@@ -745,9 +745,9 @@ static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
 	if (!frame)
 		return -ENOMEM;
 
-	if (i915_timeline_init(&frame->timeline,
-			       engine->gt,
-			       engine->status_page.vma))
+	if (intel_timeline_init(&frame->timeline,
+				engine->gt,
+				engine->status_page.vma))
 		goto out_frame;
 
 	INIT_LIST_HEAD(&frame->ring.request_list);
@@ -762,17 +762,17 @@ static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
 	frame->rq.ring = &frame->ring;
 	frame->rq.timeline = &frame->timeline;
 
-	dw = i915_timeline_pin(&frame->timeline);
+	dw = intel_timeline_pin(&frame->timeline);
 	if (dw < 0)
 		goto out_timeline;
 
 	dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
 	GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
 
-	i915_timeline_unpin(&frame->timeline);
+	intel_timeline_unpin(&frame->timeline);
 
 out_timeline:
-	i915_timeline_fini(&frame->timeline);
+	intel_timeline_fini(&frame->timeline);
 out_frame:
 	kfree(frame);
 	return dw;
@@ -874,7 +874,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 		intel_context_unpin(engine->preempt_context);
 	intel_context_unpin(engine->kernel_context);
 
-	i915_timeline_fini(&engine->timeline);
+	intel_timeline_fini(&engine->timeline);
 
 	intel_wa_list_free(&engine->ctx_wa_list);
 	intel_wa_list_free(&engine->wa_list);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 343c4459e8a3..c33fa7f0cf71 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -18,7 +18,7 @@
 #include "i915_pmu.h"
 #include "i915_priolist_types.h"
 #include "i915_selftest.h"
-#include "i915_timeline_types.h"
+#include "gt/intel_timeline_types.h"
 #include "intel_sseu.h"
 #include "intel_wakeref.h"
 #include "intel_workarounds_types.h"
@@ -66,7 +66,7 @@ struct intel_ring {
 	struct i915_vma *vma;
 	void *vaddr;
 
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
 	struct list_head request_list;
 	struct list_head active_link;
 
@@ -289,7 +289,7 @@ struct intel_engine_cs {
 
 	struct intel_ring *buffer;
 
-	struct i915_timeline timeline;
+	struct intel_timeline timeline;
 
 	struct intel_context *kernel_context; /* pinned */
 	struct intel_context *preempt_context; /* pinned; optional */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 0a49949c0599..80d4fd71b01f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2984,13 +2984,13 @@ populate_lr_context(struct intel_context *ce,
 	return ret;
 }
 
-static struct i915_timeline *
+static struct intel_timeline *
 get_timeline(struct i915_gem_context *ctx, struct intel_gt *gt)
 {
 	if (ctx->timeline)
-		return i915_timeline_get(ctx->timeline);
+		return intel_timeline_get(ctx->timeline);
 	else
-		return i915_timeline_create(gt, NULL);
+		return intel_timeline_create(gt, NULL);
 }
 
 static int execlists_context_deferred_alloc(struct intel_context *ce,
@@ -3000,7 +3000,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ce,
 	struct i915_vma *vma;
 	u32 context_size;
 	struct intel_ring *ring;
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
 	int ret;
 
 	if (ce->state)
@@ -3033,7 +3033,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ce,
 	ring = intel_engine_create_ring(engine,
 					timeline,
 					ce->gem_context->ring_size);
-	i915_timeline_put(timeline);
+	intel_timeline_put(timeline);
 	if (IS_ERR(ring)) {
 		ret = PTR_ERR(ring);
 		goto error_deref_obj;
@@ -3088,7 +3088,7 @@ static void virtual_context_destroy(struct kref *kref)
 
 	kfree(ve->bonds);
 
-	i915_timeline_fini(&ve->base.timeline);
+	intel_timeline_fini(&ve->base.timeline);
 	kfree(ve);
 }
 
@@ -3344,10 +3344,10 @@ intel_execlists_create_virtual(struct i915_gem_context *ctx,
 
 	snprintf(ve->base.name, sizeof(ve->base.name), "virtual");
 
-	err = i915_timeline_init(&ve->base.timeline, siblings[0]->gt, NULL);
+	err = intel_timeline_init(&ve->base.timeline, siblings[0]->gt, NULL);
 	if (err)
 		goto err_put;
-	i915_timeline_set_subclass(&ve->base.timeline, TIMELINE_VIRTUAL);
+	intel_timeline_set_subclass(&ve->base.timeline, TIMELINE_VIRTUAL);
 
 	intel_engine_init_execlists(&ve->base);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index a837f30350d3..04e662b4e1c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -850,7 +850,7 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
 static bool __i915_gem_unset_wedged(struct drm_i915_private *i915)
 {
 	struct i915_gpu_error *error = &i915->gpu_error;
-	struct i915_timeline *tl;
+	struct intel_timeline *tl;
 
 	if (!test_bit(I915_WEDGED, &error->flags))
 		return true;
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index d244ad68da7e..79d550e5d86a 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -730,7 +730,7 @@ static void reset_prepare(struct intel_engine_cs *engine)
 
 static void reset_ring(struct intel_engine_cs *engine, bool stalled)
 {
-	struct i915_timeline *tl = &engine->timeline;
+	struct intel_timeline *tl = &engine->timeline;
 	struct i915_request *pos, *rq;
 	unsigned long flags;
 	u32 head;
@@ -1157,7 +1157,7 @@ int intel_ring_pin(struct intel_ring *ring)
 
 	GEM_BUG_ON(ring->vaddr);
 
-	ret = i915_timeline_pin(ring->timeline);
+	ret = intel_timeline_pin(ring->timeline);
 	if (ret)
 		return ret;
 
@@ -1192,7 +1192,7 @@ int intel_ring_pin(struct intel_ring *ring)
 unpin_ring:
 	i915_vma_unpin(vma);
 unpin_timeline:
-	i915_timeline_unpin(ring->timeline);
+	intel_timeline_unpin(ring->timeline);
 	return ret;
 }
 
@@ -1223,7 +1223,7 @@ void intel_ring_unpin(struct intel_ring *ring)
 	ring->vma->obj->pin_global--;
 	i915_vma_unpin(ring->vma);
 
-	i915_timeline_unpin(ring->timeline);
+	intel_timeline_unpin(ring->timeline);
 }
 
 static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
@@ -1259,7 +1259,7 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
 
 struct intel_ring *
 intel_engine_create_ring(struct intel_engine_cs *engine,
-			 struct i915_timeline *timeline,
+			 struct intel_timeline *timeline,
 			 int size)
 {
 	struct drm_i915_private *i915 = engine->i915;
@@ -1277,7 +1277,7 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
 
 	kref_init(&ring->ref);
 	INIT_LIST_HEAD(&ring->request_list);
-	ring->timeline = i915_timeline_get(timeline);
+	ring->timeline = intel_timeline_get(timeline);
 
 	ring->size = size;
 	/* Workaround an erratum on the i830 which causes a hang if
@@ -1307,7 +1307,7 @@ void intel_ring_free(struct kref *ref)
 	i915_vma_close(ring->vma);
 	i915_vma_put(ring->vma);
 
-	i915_timeline_put(ring->timeline);
+	intel_timeline_put(ring->timeline);
 	kfree(ring);
 }
 
@@ -2298,11 +2298,11 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine)
 
 int intel_ring_submission_init(struct intel_engine_cs *engine)
 {
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
 	struct intel_ring *ring;
 	int err;
 
-	timeline = i915_timeline_create(engine->gt, engine->status_page.vma);
+	timeline = intel_timeline_create(engine->gt, engine->status_page.vma);
 	if (IS_ERR(timeline)) {
 		err = PTR_ERR(timeline);
 		goto err;
@@ -2310,7 +2310,7 @@ int intel_ring_submission_init(struct intel_engine_cs *engine)
 	GEM_BUG_ON(timeline->has_initial_breadcrumb);
 
 	ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE);
-	i915_timeline_put(timeline);
+	intel_timeline_put(timeline);
 	if (IS_ERR(ring)) {
 		err = PTR_ERR(ring);
 		goto err;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
similarity index 82%
rename from drivers/gpu/drm/i915/i915_timeline.c
rename to drivers/gpu/drm/i915/gt/intel_timeline.c
index 9b62f14ccc07..11950eccbd91 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -10,12 +10,12 @@
 
 #include "i915_active.h"
 #include "i915_syncmap.h"
-#include "i915_timeline.h"
+#include "gt/intel_timeline.h"
 
 #define ptr_set_bit(ptr, bit) ((typeof(ptr))((unsigned long)(ptr) | BIT(bit)))
 #define ptr_test_bit(ptr, bit) ((unsigned long)(ptr) & BIT(bit))
 
-struct i915_timeline_hwsp {
+struct intel_timeline_hwsp {
 	struct intel_gt *gt;
 	struct i915_gt_timelines *gt_timelines;
 	struct list_head free_link;
@@ -23,9 +23,9 @@ struct i915_timeline_hwsp {
 	u64 free_bitmap;
 };
 
-struct i915_timeline_cacheline {
+struct intel_timeline_cacheline {
 	struct i915_active active;
-	struct i915_timeline_hwsp *hwsp;
+	struct intel_timeline_hwsp *hwsp;
 	void *vaddr;
 #define CACHELINE_BITS 6
 #define CACHELINE_FREE CACHELINE_BITS
@@ -51,10 +51,10 @@ static struct i915_vma *__hwsp_alloc(struct intel_gt *gt)
 }
 
 static struct i915_vma *
-hwsp_alloc(struct i915_timeline *timeline, unsigned int *cacheline)
+hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline)
 {
 	struct i915_gt_timelines *gt = &timeline->gt->timelines;
-	struct i915_timeline_hwsp *hwsp;
+	struct intel_timeline_hwsp *hwsp;
 
 	BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
 
@@ -100,7 +100,7 @@ hwsp_alloc(struct i915_timeline *timeline, unsigned int *cacheline)
 	return hwsp->vma;
 }
 
-static void __idle_hwsp_free(struct i915_timeline_hwsp *hwsp, int cacheline)
+static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline)
 {
 	struct i915_gt_timelines *gt = hwsp->gt_timelines;
 	unsigned long flags;
@@ -124,7 +124,7 @@ static void __idle_hwsp_free(struct i915_timeline_hwsp *hwsp, int cacheline)
 	spin_unlock_irqrestore(&gt->hwsp_lock, flags);
 }
 
-static void __idle_cacheline_free(struct i915_timeline_cacheline *cl)
+static void __idle_cacheline_free(struct intel_timeline_cacheline *cl)
 {
 	GEM_BUG_ON(!i915_active_is_idle(&cl->active));
 
@@ -138,7 +138,7 @@ static void __idle_cacheline_free(struct i915_timeline_cacheline *cl)
 
 static void __cacheline_retire(struct i915_active *active)
 {
-	struct i915_timeline_cacheline *cl =
+	struct intel_timeline_cacheline *cl =
 		container_of(active, typeof(*cl), active);
 
 	i915_vma_unpin(cl->hwsp->vma);
@@ -146,10 +146,10 @@ static void __cacheline_retire(struct i915_active *active)
 		__idle_cacheline_free(cl);
 }
 
-static struct i915_timeline_cacheline *
-cacheline_alloc(struct i915_timeline_hwsp *hwsp, unsigned int cacheline)
+static struct intel_timeline_cacheline *
+cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline)
 {
-	struct i915_timeline_cacheline *cl;
+	struct intel_timeline_cacheline *cl;
 	void *vaddr;
 
 	GEM_BUG_ON(cacheline >= BIT(CACHELINE_BITS));
@@ -173,19 +173,19 @@ cacheline_alloc(struct i915_timeline_hwsp *hwsp, unsigned int cacheline)
 	return cl;
 }
 
-static void cacheline_acquire(struct i915_timeline_cacheline *cl)
+static void cacheline_acquire(struct intel_timeline_cacheline *cl)
 {
 	if (cl && i915_active_acquire(&cl->active))
 		__i915_vma_pin(cl->hwsp->vma);
 }
 
-static void cacheline_release(struct i915_timeline_cacheline *cl)
+static void cacheline_release(struct intel_timeline_cacheline *cl)
 {
 	if (cl)
 		i915_active_release(&cl->active);
 }
 
-static void cacheline_free(struct i915_timeline_cacheline *cl)
+static void cacheline_free(struct intel_timeline_cacheline *cl)
 {
 	GEM_BUG_ON(ptr_test_bit(cl->vaddr, CACHELINE_FREE));
 	cl->vaddr = ptr_set_bit(cl->vaddr, CACHELINE_FREE);
@@ -194,9 +194,9 @@ static void cacheline_free(struct i915_timeline_cacheline *cl)
 		__idle_cacheline_free(cl);
 }
 
-int i915_timeline_init(struct i915_timeline *timeline,
-		       struct intel_gt *gt,
-		       struct i915_vma *hwsp)
+int intel_timeline_init(struct intel_timeline *timeline,
+			struct intel_gt *gt,
+			struct i915_vma *hwsp)
 {
 	void *vaddr;
 
@@ -216,7 +216,7 @@ int i915_timeline_init(struct i915_timeline *timeline,
 	timeline->hwsp_cacheline = NULL;
 
 	if (!hwsp) {
-		struct i915_timeline_cacheline *cl;
+		struct intel_timeline_cacheline *cl;
 		unsigned int cacheline;
 
 		hwsp = hwsp_alloc(timeline, &cacheline);
@@ -274,12 +274,12 @@ static void timelines_init(struct intel_gt *gt)
 	i915_gem_shrinker_taints_mutex(gt->i915, &timelines->mutex);
 }
 
-void i915_timelines_init(struct drm_i915_private *i915)
+void intel_timelines_init(struct drm_i915_private *i915)
 {
 	timelines_init(&i915->gt);
 }
 
-static void timeline_add_to_active(struct i915_timeline *tl)
+static void timeline_add_to_active(struct intel_timeline *tl)
 {
 	struct i915_gt_timelines *gt = &tl->gt->timelines;
 
@@ -288,7 +288,7 @@ static void timeline_add_to_active(struct i915_timeline *tl)
 	mutex_unlock(&gt->mutex);
 }
 
-static void timeline_remove_from_active(struct i915_timeline *tl)
+static void timeline_remove_from_active(struct intel_timeline *tl)
 {
 	struct i915_gt_timelines *gt = &tl->gt->timelines;
 
@@ -300,7 +300,7 @@ static void timeline_remove_from_active(struct i915_timeline *tl)
 static void timelines_park(struct intel_gt *gt)
 {
 	struct i915_gt_timelines *timelines = &gt->timelines;
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
 
 	mutex_lock(&timelines->mutex);
 	list_for_each_entry(timeline, &timelines->active_list, link) {
@@ -316,7 +316,7 @@ static void timelines_park(struct intel_gt *gt)
 }
 
 /**
- * i915_timelines_park - called when the driver idles
+ * intel_timelines_park - called when the driver idles
  * @i915: the drm_i915_private device
  *
  * When the driver is completely idle, we know that all of our sync points
@@ -325,12 +325,12 @@ static void timelines_park(struct intel_gt *gt)
  * the fence is signaled and therefore we will not even look them up in the
  * sync point map.
  */
-void i915_timelines_park(struct drm_i915_private *i915)
+void intel_timelines_park(struct drm_i915_private *i915)
 {
 	timelines_park(&i915->gt);
 }
 
-void i915_timeline_fini(struct i915_timeline *timeline)
+void intel_timeline_fini(struct intel_timeline *timeline)
 {
 	GEM_BUG_ON(timeline->pin_count);
 	GEM_BUG_ON(!list_empty(&timeline->requests));
@@ -345,17 +345,17 @@ void i915_timeline_fini(struct i915_timeline *timeline)
 	i915_vma_put(timeline->hwsp_ggtt);
 }
 
-struct i915_timeline *
-i915_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp)
+struct intel_timeline *
+intel_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp)
 {
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
 	int err;
 
 	timeline = kzalloc(sizeof(*timeline), GFP_KERNEL);
 	if (!timeline)
 		return ERR_PTR(-ENOMEM);
 
-	err = i915_timeline_init(timeline, gt, global_hwsp);
+	err = intel_timeline_init(timeline, gt, global_hwsp);
 	if (err) {
 		kfree(timeline);
 		return ERR_PTR(err);
@@ -366,7 +366,7 @@ i915_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp)
 	return timeline;
 }
 
-int i915_timeline_pin(struct i915_timeline *tl)
+int intel_timeline_pin(struct intel_timeline *tl)
 {
 	int err;
 
@@ -392,7 +392,7 @@ int i915_timeline_pin(struct i915_timeline *tl)
 	return err;
 }
 
-static u32 timeline_advance(struct i915_timeline *tl)
+static u32 timeline_advance(struct intel_timeline *tl)
 {
 	GEM_BUG_ON(!tl->pin_count);
 	GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
@@ -400,17 +400,17 @@ static u32 timeline_advance(struct i915_timeline *tl)
 	return tl->seqno += 1 + tl->has_initial_breadcrumb;
 }
 
-static void timeline_rollback(struct i915_timeline *tl)
+static void timeline_rollback(struct intel_timeline *tl)
 {
 	tl->seqno -= 1 + tl->has_initial_breadcrumb;
 }
 
 static noinline int
-__i915_timeline_get_seqno(struct i915_timeline *tl,
-			  struct i915_request *rq,
-			  u32 *seqno)
+__intel_timeline_get_seqno(struct intel_timeline *tl,
+			   struct i915_request *rq,
+			   u32 *seqno)
 {
-	struct i915_timeline_cacheline *cl;
+	struct intel_timeline_cacheline *cl;
 	unsigned int cacheline;
 	struct i915_vma *vma;
 	void *vaddr;
@@ -496,31 +496,31 @@ __i915_timeline_get_seqno(struct i915_timeline *tl,
 	return err;
 }
 
-int i915_timeline_get_seqno(struct i915_timeline *tl,
-			    struct i915_request *rq,
-			    u32 *seqno)
+int intel_timeline_get_seqno(struct intel_timeline *tl,
+			     struct i915_request *rq,
+			     u32 *seqno)
 {
 	*seqno = timeline_advance(tl);
 
 	/* Replace the HWSP on wraparound for HW semaphores */
 	if (unlikely(!*seqno && tl->hwsp_cacheline))
-		return __i915_timeline_get_seqno(tl, rq, seqno);
+		return __intel_timeline_get_seqno(tl, rq, seqno);
 
 	return 0;
 }
 
-static int cacheline_ref(struct i915_timeline_cacheline *cl,
+static int cacheline_ref(struct intel_timeline_cacheline *cl,
 			 struct i915_request *rq)
 {
 	return i915_active_ref(&cl->active, rq->fence.context, rq);
 }
 
-int i915_timeline_read_hwsp(struct i915_request *from,
-			    struct i915_request *to,
-			    u32 *hwsp)
+int intel_timeline_read_hwsp(struct i915_request *from,
+			     struct i915_request *to,
+			     u32 *hwsp)
 {
-	struct i915_timeline_cacheline *cl = from->hwsp_cacheline;
-	struct i915_timeline *tl = from->timeline;
+	struct intel_timeline_cacheline *cl = from->hwsp_cacheline;
+	struct intel_timeline *tl = from->timeline;
 	int err;
 
 	GEM_BUG_ON(to->timeline == tl);
@@ -543,7 +543,7 @@ int i915_timeline_read_hwsp(struct i915_request *from,
 	return err;
 }
 
-void i915_timeline_unpin(struct i915_timeline *tl)
+void intel_timeline_unpin(struct intel_timeline *tl)
 {
 	GEM_BUG_ON(!tl->pin_count);
 	if (--tl->pin_count)
@@ -562,12 +562,12 @@ void i915_timeline_unpin(struct i915_timeline *tl)
 	__i915_vma_unpin(tl->hwsp_ggtt);
 }
 
-void __i915_timeline_free(struct kref *kref)
+void __intel_timeline_free(struct kref *kref)
 {
-	struct i915_timeline *timeline =
+	struct intel_timeline *timeline =
 		container_of(kref, typeof(*timeline), kref);
 
-	i915_timeline_fini(timeline);
+	intel_timeline_fini(timeline);
 	kfree(timeline);
 }
 
@@ -581,12 +581,12 @@ static void timelines_fini(struct intel_gt *gt)
 	mutex_destroy(&timelines->mutex);
 }
 
-void i915_timelines_fini(struct drm_i915_private *i915)
+void intel_timelines_fini(struct drm_i915_private *i915)
 {
 	timelines_fini(&i915->gt);
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
-#include "selftests/mock_timeline.c"
-#include "selftests/i915_timeline.c"
+#include "gt/selftests/mock_timeline.c"
+#include "gt/selftest_timeline.c"
 #endif
diff --git a/drivers/gpu/drm/i915/i915_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h
similarity index 53%
rename from drivers/gpu/drm/i915/i915_timeline.h
rename to drivers/gpu/drm/i915/gt/intel_timeline.h
index 8399e11e68b4..dcc5afea6ab6 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -29,16 +29,16 @@
 
 #include "i915_active.h"
 #include "i915_syncmap.h"
-#include "i915_timeline_types.h"
+#include "gt/intel_timeline_types.h"
 
-int i915_timeline_init(struct i915_timeline *tl,
-		       struct intel_gt *gt,
-		       struct i915_vma *hwsp);
-void i915_timeline_fini(struct i915_timeline *tl);
+int intel_timeline_init(struct intel_timeline *tl,
+			struct intel_gt *gt,
+			struct i915_vma *hwsp);
+void intel_timeline_fini(struct intel_timeline *tl);
 
 static inline void
-i915_timeline_set_subclass(struct i915_timeline *timeline,
-			   unsigned int subclass)
+intel_timeline_set_subclass(struct intel_timeline *timeline,
+			    unsigned int subclass)
 {
 	lockdep_set_subclass(&timeline->lock, subclass);
 
@@ -55,58 +55,58 @@ i915_timeline_set_subclass(struct i915_timeline *timeline,
 #endif
 }
 
-struct i915_timeline *
-i915_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp);
+struct intel_timeline *
+intel_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp);
 
-static inline struct i915_timeline *
-i915_timeline_get(struct i915_timeline *timeline)
+static inline struct intel_timeline *
+intel_timeline_get(struct intel_timeline *timeline)
 {
 	kref_get(&timeline->kref);
 	return timeline;
 }
 
-void __i915_timeline_free(struct kref *kref);
-static inline void i915_timeline_put(struct i915_timeline *timeline)
+void __intel_timeline_free(struct kref *kref);
+static inline void intel_timeline_put(struct intel_timeline *timeline)
 {
-	kref_put(&timeline->kref, __i915_timeline_free);
+	kref_put(&timeline->kref, __intel_timeline_free);
 }
 
-static inline int __i915_timeline_sync_set(struct i915_timeline *tl,
-					   u64 context, u32 seqno)
+static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
+					    u64 context, u32 seqno)
 {
 	return i915_syncmap_set(&tl->sync, context, seqno);
 }
 
-static inline int i915_timeline_sync_set(struct i915_timeline *tl,
-					 const struct dma_fence *fence)
+static inline int intel_timeline_sync_set(struct intel_timeline *tl,
+					  const struct dma_fence *fence)
 {
-	return __i915_timeline_sync_set(tl, fence->context, fence->seqno);
+	return __intel_timeline_sync_set(tl, fence->context, fence->seqno);
 }
 
-static inline bool __i915_timeline_sync_is_later(struct i915_timeline *tl,
-						 u64 context, u32 seqno)
+static inline bool __intel_timeline_sync_is_later(struct intel_timeline *tl,
+						  u64 context, u32 seqno)
 {
 	return i915_syncmap_is_later(&tl->sync, context, seqno);
 }
 
-static inline bool i915_timeline_sync_is_later(struct i915_timeline *tl,
-					       const struct dma_fence *fence)
+static inline bool intel_timeline_sync_is_later(struct intel_timeline *tl,
+						const struct dma_fence *fence)
 {
-	return __i915_timeline_sync_is_later(tl, fence->context, fence->seqno);
+	return __intel_timeline_sync_is_later(tl, fence->context, fence->seqno);
 }
 
-int i915_timeline_pin(struct i915_timeline *tl);
-int i915_timeline_get_seqno(struct i915_timeline *tl,
-			    struct i915_request *rq,
-			    u32 *seqno);
-void i915_timeline_unpin(struct i915_timeline *tl);
+int intel_timeline_pin(struct intel_timeline *tl);
+int intel_timeline_get_seqno(struct intel_timeline *tl,
+			     struct i915_request *rq,
+			     u32 *seqno);
+void intel_timeline_unpin(struct intel_timeline *tl);
 
-int i915_timeline_read_hwsp(struct i915_request *from,
-			    struct i915_request *until,
-			    u32 *hwsp_offset);
+int intel_timeline_read_hwsp(struct i915_request *from,
+			     struct i915_request *until,
+			     u32 *hwsp_offset);
 
-void i915_timelines_init(struct drm_i915_private *i915);
-void i915_timelines_park(struct drm_i915_private *i915);
-void i915_timelines_fini(struct drm_i915_private *i915);
+void intel_timelines_init(struct drm_i915_private *i915);
+void intel_timelines_park(struct drm_i915_private *i915);
+void intel_timelines_fini(struct drm_i915_private *i915);
 
 #endif
diff --git a/drivers/gpu/drm/i915/i915_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
similarity index 94%
rename from drivers/gpu/drm/i915/i915_timeline_types.h
rename to drivers/gpu/drm/i915/gt/intel_timeline_types.h
index 041709087508..9c6438e4aec2 100644
--- a/drivers/gpu/drm/i915/i915_timeline_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
@@ -16,10 +16,10 @@
 
 struct drm_i915_private;
 struct i915_vma;
-struct i915_timeline_cacheline;
+struct intel_timeline_cacheline;
 struct i915_syncmap;
 
-struct i915_timeline {
+struct intel_timeline {
 	u64 fence_context;
 	u32 seqno;
 
@@ -34,7 +34,7 @@ struct i915_timeline {
 	struct i915_vma *hwsp_ggtt;
 	u32 hwsp_offset;
 
-	struct i915_timeline_cacheline *hwsp_cacheline;
+	struct intel_timeline_cacheline *hwsp_cacheline;
 
 	bool has_initial_breadcrumb;
 
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
index 0ebe78ada05b..e74755c98934 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -33,15 +33,15 @@
 
 struct mock_ring {
 	struct intel_ring base;
-	struct i915_timeline timeline;
+	struct intel_timeline timeline;
 };
 
-static void mock_timeline_pin(struct i915_timeline *tl)
+static void mock_timeline_pin(struct intel_timeline *tl)
 {
 	tl->pin_count++;
 }
 
-static void mock_timeline_unpin(struct i915_timeline *tl)
+static void mock_timeline_unpin(struct intel_timeline *tl)
 {
 	GEM_BUG_ON(!tl->pin_count);
 	tl->pin_count--;
@@ -56,7 +56,7 @@ static struct intel_ring *mock_ring(struct intel_engine_cs *engine)
 	if (!ring)
 		return NULL;
 
-	if (i915_timeline_init(&ring->timeline, engine->gt, NULL)) {
+	if (intel_timeline_init(&ring->timeline, engine->gt, NULL)) {
 		kfree(ring);
 		return NULL;
 	}
@@ -77,7 +77,7 @@ static void mock_ring_free(struct intel_ring *base)
 {
 	struct mock_ring *ring = container_of(base, typeof(*ring), base);
 
-	i915_timeline_fini(&ring->timeline);
+	intel_timeline_fini(&ring->timeline);
 	kfree(ring);
 }
 
@@ -283,9 +283,9 @@ int mock_engine_init(struct intel_engine_cs *engine)
 	intel_engine_init_execlists(engine);
 	intel_engine_init__pm(engine);
 
-	if (i915_timeline_init(&engine->timeline, engine->gt, NULL))
+	if (intel_timeline_init(&engine->timeline, engine->gt, NULL))
 		goto err_breadcrumbs;
-	i915_timeline_set_subclass(&engine->timeline, TIMELINE_ENGINE);
+	intel_timeline_set_subclass(&engine->timeline, TIMELINE_ENGINE);
 
 	engine->kernel_context =
 		i915_gem_context_get_engine(i915->kernel_context, engine->id);
@@ -300,7 +300,7 @@ int mock_engine_init(struct intel_engine_cs *engine)
 	return 0;
 
 err_timeline:
-	i915_timeline_fini(&engine->timeline);
+	intel_timeline_fini(&engine->timeline);
 err_breadcrumbs:
 	intel_engine_fini_breadcrumbs(engine);
 	return -ENOMEM;
@@ -339,7 +339,7 @@ void mock_engine_free(struct intel_engine_cs *engine)
 	intel_context_unpin(engine->kernel_context);
 
 	intel_engine_fini_breadcrumbs(engine);
-	i915_timeline_fini(&engine->timeline);
+	intel_timeline_fini(&engine->timeline);
 
 	kfree(engine);
 }
diff --git a/drivers/gpu/drm/i915/selftests/i915_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
similarity index 87%
rename from drivers/gpu/drm/i915/selftests/i915_timeline.c
rename to drivers/gpu/drm/i915/gt/selftest_timeline.c
index 57835127563b..fa6b7dc1fd7f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -8,14 +8,14 @@
 
 #include "gem/i915_gem_pm.h"
 
-#include "i915_random.h"
-#include "i915_selftest.h"
+#include "../selftests/i915_random.h"
+#include "../i915_selftest.h"
 
-#include "igt_flush_test.h"
-#include "mock_gem_device.h"
-#include "mock_timeline.h"
+#include "../selftests/igt_flush_test.h"
+#include "../selftests/mock_gem_device.h"
+#include "selftests/mock_timeline.h"
 
-static struct page *hwsp_page(struct i915_timeline *tl)
+static struct page *hwsp_page(struct intel_timeline *tl)
 {
 	struct drm_i915_gem_object *obj = tl->hwsp_ggtt->obj;
 
@@ -23,7 +23,7 @@ static struct page *hwsp_page(struct i915_timeline *tl)
 	return sg_page(obj->mm.pages->sgl);
 }
 
-static unsigned long hwsp_cacheline(struct i915_timeline *tl)
+static unsigned long hwsp_cacheline(struct intel_timeline *tl)
 {
 	unsigned long address = (unsigned long)page_address(hwsp_page(tl));
 
@@ -35,7 +35,7 @@ static unsigned long hwsp_cacheline(struct i915_timeline *tl)
 struct mock_hwsp_freelist {
 	struct drm_i915_private *i915;
 	struct radix_tree_root cachelines;
-	struct i915_timeline **history;
+	struct intel_timeline **history;
 	unsigned long count, max;
 	struct rnd_state prng;
 };
@@ -46,12 +46,12 @@ enum {
 
 static void __mock_hwsp_record(struct mock_hwsp_freelist *state,
 			       unsigned int idx,
-			       struct i915_timeline *tl)
+			       struct intel_timeline *tl)
 {
 	tl = xchg(&state->history[idx], tl);
 	if (tl) {
 		radix_tree_delete(&state->cachelines, hwsp_cacheline(tl));
-		i915_timeline_put(tl);
+		intel_timeline_put(tl);
 	}
 }
 
@@ -59,14 +59,14 @@ static int __mock_hwsp_timeline(struct mock_hwsp_freelist *state,
 				unsigned int count,
 				unsigned int flags)
 {
-	struct i915_timeline *tl;
+	struct intel_timeline *tl;
 	unsigned int idx;
 
 	while (count--) {
 		unsigned long cacheline;
 		int err;
 
-		tl = i915_timeline_create(&state->i915->gt, NULL);
+		tl = intel_timeline_create(&state->i915->gt, NULL);
 		if (IS_ERR(tl))
 			return PTR_ERR(tl);
 
@@ -77,7 +77,7 @@ static int __mock_hwsp_timeline(struct mock_hwsp_freelist *state,
 				pr_err("HWSP cacheline %lu already used; duplicate allocation!\n",
 				       cacheline);
 			}
-			i915_timeline_put(tl);
+			intel_timeline_put(tl);
 			return err;
 		}
 
@@ -162,21 +162,21 @@ struct __igt_sync {
 	bool set;
 };
 
-static int __igt_sync(struct i915_timeline *tl,
+static int __igt_sync(struct intel_timeline *tl,
 		      u64 ctx,
 		      const struct __igt_sync *p,
 		      const char *name)
 {
 	int ret;
 
-	if (__i915_timeline_sync_is_later(tl, ctx, p->seqno) != p->expected) {
+	if (__intel_timeline_sync_is_later(tl, ctx, p->seqno) != p->expected) {
 		pr_err("%s: %s(ctx=%llu, seqno=%u) expected passed %s but failed\n",
 		       name, p->name, ctx, p->seqno, yesno(p->expected));
 		return -EINVAL;
 	}
 
 	if (p->set) {
-		ret = __i915_timeline_sync_set(tl, ctx, p->seqno);
+		ret = __intel_timeline_sync_set(tl, ctx, p->seqno);
 		if (ret)
 			return ret;
 	}
@@ -204,7 +204,7 @@ static int igt_sync(void *arg)
 		{ "unwrap", UINT_MAX, true, false },
 		{},
 	}, *p;
-	struct i915_timeline tl;
+	struct intel_timeline tl;
 	int order, offset;
 	int ret = -ENODEV;
 
@@ -248,7 +248,7 @@ static unsigned int random_engine(struct rnd_state *rnd)
 static int bench_sync(void *arg)
 {
 	struct rnd_state prng;
-	struct i915_timeline tl;
+	struct intel_timeline tl;
 	unsigned long end_time, count;
 	u64 prng32_1M;
 	ktime_t kt;
@@ -286,7 +286,7 @@ static int bench_sync(void *arg)
 	do {
 		u64 id = i915_prandom_u64_state(&prng);
 
-		__i915_timeline_sync_set(&tl, id, 0);
+		__intel_timeline_sync_set(&tl, id, 0);
 		count++;
 	} while (!time_after(jiffies, end_time));
 	kt = ktime_sub(ktime_get(), kt);
@@ -301,7 +301,7 @@ static int bench_sync(void *arg)
 	while (end_time--) {
 		u64 id = i915_prandom_u64_state(&prng);
 
-		if (!__i915_timeline_sync_is_later(&tl, id, 0)) {
+		if (!__intel_timeline_sync_is_later(&tl, id, 0)) {
 			mock_timeline_fini(&tl);
 			pr_err("Lookup of %llu failed\n", id);
 			return -EINVAL;
@@ -322,7 +322,7 @@ static int bench_sync(void *arg)
 	kt = ktime_get();
 	end_time = jiffies + HZ/10;
 	do {
-		__i915_timeline_sync_set(&tl, count++, 0);
+		__intel_timeline_sync_set(&tl, count++, 0);
 	} while (!time_after(jiffies, end_time));
 	kt = ktime_sub(ktime_get(), kt);
 	pr_info("%s: %lu in-order insertions, %lluns/insert\n",
@@ -332,7 +332,7 @@ static int bench_sync(void *arg)
 	end_time = count;
 	kt = ktime_get();
 	while (end_time--) {
-		if (!__i915_timeline_sync_is_later(&tl, end_time, 0)) {
+		if (!__intel_timeline_sync_is_later(&tl, end_time, 0)) {
 			pr_err("Lookup of %lu failed\n", end_time);
 			mock_timeline_fini(&tl);
 			return -EINVAL;
@@ -356,8 +356,8 @@ static int bench_sync(void *arg)
 		u32 id = random_engine(&prng);
 		u32 seqno = prandom_u32_state(&prng);
 
-		if (!__i915_timeline_sync_is_later(&tl, id, seqno))
-			__i915_timeline_sync_set(&tl, id, seqno);
+		if (!__intel_timeline_sync_is_later(&tl, id, seqno))
+			__intel_timeline_sync_set(&tl, id, seqno);
 
 		count++;
 	} while (!time_after(jiffies, end_time));
@@ -385,8 +385,8 @@ static int bench_sync(void *arg)
 			 */
 			u64 id = (u64)(count & mask) << order;
 
-			__i915_timeline_sync_is_later(&tl, id, 0);
-			__i915_timeline_sync_set(&tl, id, 0);
+			__intel_timeline_sync_is_later(&tl, id, 0);
+			__intel_timeline_sync_set(&tl, id, 0);
 
 			count++;
 		} while (!time_after(jiffies, end_time));
@@ -401,7 +401,7 @@ static int bench_sync(void *arg)
 	return 0;
 }
 
-int i915_timeline_mock_selftests(void)
+int intel_timeline_mock_selftests(void)
 {
 	static const struct i915_subtest tests[] = {
 		SUBTEST(mock_hwsp_freelist),
@@ -443,14 +443,14 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
 }
 
 static struct i915_request *
-tl_write(struct i915_timeline *tl, struct intel_engine_cs *engine, u32 value)
+tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)
 {
 	struct i915_request *rq;
 	int err;
 
 	lockdep_assert_held(&tl->gt->i915->drm.struct_mutex); /* lazy rq refs */
 
-	err = i915_timeline_pin(tl);
+	err = intel_timeline_pin(tl);
 	if (err) {
 		rq = ERR_PTR(err);
 		goto out;
@@ -466,26 +466,26 @@ tl_write(struct i915_timeline *tl, struct intel_engine_cs *engine, u32 value)
 		rq = ERR_PTR(err);
 
 out_unpin:
-	i915_timeline_unpin(tl);
+	intel_timeline_unpin(tl);
 out:
 	if (IS_ERR(rq))
 		pr_err("Failed to write to timeline!\n");
 	return rq;
 }
 
-static struct i915_timeline *
-checked_i915_timeline_create(struct drm_i915_private *i915)
+static struct intel_timeline *
+checked_intel_timeline_create(struct drm_i915_private *i915)
 {
-	struct i915_timeline *tl;
+	struct intel_timeline *tl;
 
-	tl = i915_timeline_create(&i915->gt, NULL);
+	tl = intel_timeline_create(&i915->gt, NULL);
 	if (IS_ERR(tl))
 		return tl;
 
 	if (*tl->hwsp_seqno != tl->seqno) {
 		pr_err("Timeline created with incorrect breadcrumb, found %x, expected %x\n",
 		       *tl->hwsp_seqno, tl->seqno);
-		i915_timeline_put(tl);
+		intel_timeline_put(tl);
 		return ERR_PTR(-EINVAL);
 	}
 
@@ -496,7 +496,7 @@ static int live_hwsp_engine(void *arg)
 {
 #define NUM_TIMELINES 4096
 	struct drm_i915_private *i915 = arg;
-	struct i915_timeline **timelines;
+	struct intel_timeline **timelines;
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
 	intel_wakeref_t wakeref;
@@ -523,10 +523,10 @@ static int live_hwsp_engine(void *arg)
 			continue;
 
 		for (n = 0; n < NUM_TIMELINES; n++) {
-			struct i915_timeline *tl;
+			struct intel_timeline *tl;
 			struct i915_request *rq;
 
-			tl = checked_i915_timeline_create(i915);
+			tl = checked_intel_timeline_create(i915);
 			if (IS_ERR(tl)) {
 				err = PTR_ERR(tl);
 				goto out;
@@ -534,7 +534,7 @@ static int live_hwsp_engine(void *arg)
 
 			rq = tl_write(tl, engine, count);
 			if (IS_ERR(rq)) {
-				i915_timeline_put(tl);
+				intel_timeline_put(tl);
 				err = PTR_ERR(rq);
 				goto out;
 			}
@@ -548,14 +548,14 @@ static int live_hwsp_engine(void *arg)
 		err = -EIO;
 
 	for (n = 0; n < count; n++) {
-		struct i915_timeline *tl = timelines[n];
+		struct intel_timeline *tl = timelines[n];
 
 		if (!err && *tl->hwsp_seqno != n) {
 			pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
 			       n, *tl->hwsp_seqno);
 			err = -EINVAL;
 		}
-		i915_timeline_put(tl);
+		intel_timeline_put(tl);
 	}
 
 	intel_runtime_pm_put(i915, wakeref);
@@ -571,7 +571,7 @@ static int live_hwsp_alternate(void *arg)
 {
 #define NUM_TIMELINES 4096
 	struct drm_i915_private *i915 = arg;
-	struct i915_timeline **timelines;
+	struct intel_timeline **timelines;
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
 	intel_wakeref_t wakeref;
@@ -596,13 +596,13 @@ static int live_hwsp_alternate(void *arg)
 	count = 0;
 	for (n = 0; n < NUM_TIMELINES; n++) {
 		for_each_engine(engine, i915, id) {
-			struct i915_timeline *tl;
+			struct intel_timeline *tl;
 			struct i915_request *rq;
 
 			if (!intel_engine_can_store_dword(engine))
 				continue;
 
-			tl = checked_i915_timeline_create(i915);
+			tl = checked_intel_timeline_create(i915);
 			if (IS_ERR(tl)) {
 				err = PTR_ERR(tl);
 				goto out;
@@ -610,7 +610,7 @@ static int live_hwsp_alternate(void *arg)
 
 			rq = tl_write(tl, engine, count);
 			if (IS_ERR(rq)) {
-				i915_timeline_put(tl);
+				intel_timeline_put(tl);
 				err = PTR_ERR(rq);
 				goto out;
 			}
@@ -624,14 +624,14 @@ static int live_hwsp_alternate(void *arg)
 		err = -EIO;
 
 	for (n = 0; n < count; n++) {
-		struct i915_timeline *tl = timelines[n];
+		struct intel_timeline *tl = timelines[n];
 
 		if (!err && *tl->hwsp_seqno != n) {
 			pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
 			       n, *tl->hwsp_seqno);
 			err = -EINVAL;
 		}
-		i915_timeline_put(tl);
+		intel_timeline_put(tl);
 	}
 
 	intel_runtime_pm_put(i915, wakeref);
@@ -647,7 +647,7 @@ static int live_hwsp_wrap(void *arg)
 {
 	struct drm_i915_private *i915 = arg;
 	struct intel_engine_cs *engine;
-	struct i915_timeline *tl;
+	struct intel_timeline *tl;
 	enum intel_engine_id id;
 	intel_wakeref_t wakeref;
 	int err = 0;
@@ -660,7 +660,7 @@ static int live_hwsp_wrap(void *arg)
 	mutex_lock(&i915->drm.struct_mutex);
 	wakeref = intel_runtime_pm_get(i915);
 
-	tl = i915_timeline_create(&i915->gt, NULL);
+	tl = intel_timeline_create(&i915->gt, NULL);
 	if (IS_ERR(tl)) {
 		err = PTR_ERR(tl);
 		goto out_rpm;
@@ -668,7 +668,7 @@ static int live_hwsp_wrap(void *arg)
 	if (!tl->has_initial_breadcrumb || !tl->hwsp_cacheline)
 		goto out_free;
 
-	err = i915_timeline_pin(tl);
+	err = intel_timeline_pin(tl);
 	if (err)
 		goto out_free;
 
@@ -688,7 +688,7 @@ static int live_hwsp_wrap(void *arg)
 
 		tl->seqno = -4u;
 
-		err = i915_timeline_get_seqno(tl, rq, &seqno[0]);
+		err = intel_timeline_get_seqno(tl, rq, &seqno[0]);
 		if (err) {
 			i915_request_add(rq);
 			goto out;
@@ -703,7 +703,7 @@ static int live_hwsp_wrap(void *arg)
 		}
 		hwsp_seqno[0] = tl->hwsp_seqno;
 
-		err = i915_timeline_get_seqno(tl, rq, &seqno[1]);
+		err = intel_timeline_get_seqno(tl, rq, &seqno[1]);
 		if (err) {
 			i915_request_add(rq);
 			goto out;
@@ -745,9 +745,9 @@ static int live_hwsp_wrap(void *arg)
 	if (igt_flush_test(i915, I915_WAIT_LOCKED))
 		err = -EIO;
 
-	i915_timeline_unpin(tl);
+	intel_timeline_unpin(tl);
 out_free:
-	i915_timeline_put(tl);
+	intel_timeline_put(tl);
 out_rpm:
 	intel_runtime_pm_put(i915, wakeref);
 	mutex_unlock(&i915->drm.struct_mutex);
@@ -781,10 +781,10 @@ static int live_hwsp_recycle(void *arg)
 			continue;
 
 		do {
-			struct i915_timeline *tl;
+			struct intel_timeline *tl;
 			struct i915_request *rq;
 
-			tl = checked_i915_timeline_create(i915);
+			tl = checked_intel_timeline_create(i915);
 			if (IS_ERR(tl)) {
 				err = PTR_ERR(tl);
 				goto out;
@@ -792,7 +792,7 @@ static int live_hwsp_recycle(void *arg)
 
 			rq = tl_write(tl, engine, count);
 			if (IS_ERR(rq)) {
-				i915_timeline_put(tl);
+				intel_timeline_put(tl);
 				err = PTR_ERR(rq);
 				goto out;
 			}
@@ -801,7 +801,7 @@ static int live_hwsp_recycle(void *arg)
 					      I915_WAIT_LOCKED,
 					      HZ / 5) < 0) {
 				pr_err("Wait for timeline writes timed out!\n");
-				i915_timeline_put(tl);
+				intel_timeline_put(tl);
 				err = -EIO;
 				goto out;
 			}
@@ -812,13 +812,13 @@ static int live_hwsp_recycle(void *arg)
 				err = -EINVAL;
 			}
 
-			i915_timeline_put(tl);
+			intel_timeline_put(tl);
 			count++;
 
 			if (err)
 				goto out;
 
-			i915_timelines_park(i915); /* Encourage recycling! */
+			intel_timelines_park(i915); /* Encourage recycling! */
 		} while (!__igt_timeout(end_time, NULL));
 	}
 
@@ -831,7 +831,7 @@ static int live_hwsp_recycle(void *arg)
 	return err;
 }
 
-int i915_timeline_live_selftests(struct drm_i915_private *i915)
+int intel_timeline_live_selftests(struct drm_i915_private *i915)
 {
 	static const struct i915_subtest tests[] = {
 		SUBTEST(live_hwsp_recycle),
diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.c b/drivers/gpu/drm/i915/gt/selftests/mock_timeline.c
similarity index 73%
rename from drivers/gpu/drm/i915/selftests/mock_timeline.c
rename to drivers/gpu/drm/i915/gt/selftests/mock_timeline.c
index e1a256761d2c..f12d6547bf12 100644
--- a/drivers/gpu/drm/i915/selftests/mock_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftests/mock_timeline.c
@@ -4,11 +4,11 @@
  * Copyright © 2017-2018 Intel Corporation
  */
 
-#include "../i915_timeline.h"
+#include "../intel_timeline.h"
 
 #include "mock_timeline.h"
 
-void mock_timeline_init(struct i915_timeline *timeline, u64 context)
+void mock_timeline_init(struct intel_timeline *timeline, u64 context)
 {
 	timeline->gt = NULL;
 	timeline->fence_context = context;
@@ -24,7 +24,7 @@ void mock_timeline_init(struct i915_timeline *timeline, u64 context)
 	INIT_LIST_HEAD(&timeline->link);
 }
 
-void mock_timeline_fini(struct i915_timeline *timeline)
+void mock_timeline_fini(struct intel_timeline *timeline)
 {
 	i915_syncmap_free(&timeline->sync);
 }
diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.h b/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
similarity index 53%
rename from drivers/gpu/drm/i915/selftests/mock_timeline.h
rename to drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
index b6deaa61110d..689efc66c908 100644
--- a/drivers/gpu/drm/i915/selftests/mock_timeline.h
+++ b/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
@@ -7,9 +7,9 @@
 #ifndef __MOCK_TIMELINE__
 #define __MOCK_TIMELINE__
 
-struct i915_timeline;
+struct intel_timeline;
 
-void mock_timeline_init(struct i915_timeline *timeline, u64 context);
-void mock_timeline_fini(struct i915_timeline *timeline);
+void mock_timeline_init(struct intel_timeline *timeline, u64 context);
+void mock_timeline_fini(struct intel_timeline *timeline);
 
 #endif /* !__MOCK_TIMELINE__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cd5f7ba28f87..1957a085221b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -88,7 +88,7 @@
 #include "i915_gpu_error.h"
 #include "i915_request.h"
 #include "i915_scheduler.h"
-#include "i915_timeline.h"
+#include "gt/intel_timeline.h"
 #include "i915_vma.h"
 
 #include "intel_gvt.h"
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 248b473c3bee..ad1dc58a2374 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -907,7 +907,7 @@ wait_for_timelines(struct drm_i915_private *i915,
 		   unsigned int flags, long timeout)
 {
 	struct i915_gt_timelines *gt = &i915->gt.timelines;
-	struct i915_timeline *tl;
+	struct intel_timeline *tl;
 
 	mutex_lock(&gt->mutex);
 	list_for_each_entry(tl, &gt->active_list, link) {
@@ -1489,7 +1489,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 
 	dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
 
-	i915_timelines_init(dev_priv);
+	intel_timelines_init(dev_priv);
 
 	ret = i915_gem_init_userptr(dev_priv);
 	if (ret)
@@ -1626,7 +1626,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 
 	if (ret != -EIO) {
 		i915_gem_cleanup_userptr(dev_priv);
-		i915_timelines_fini(dev_priv);
+		intel_timelines_fini(dev_priv);
 	}
 
 	if (ret == -EIO) {
@@ -1690,7 +1690,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
 
 	intel_uc_fini_misc(dev_priv);
 	i915_gem_cleanup_userptr(dev_priv);
-	i915_timelines_fini(dev_priv);
+	intel_timelines_fini(dev_priv);
 
 	i915_gem_drain_freed_objects(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 827af6ba36c7..6ac2f45e2f19 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -43,7 +43,7 @@
 #include "i915_request.h"
 #include "i915_scatterlist.h"
 #include "i915_selftest.h"
-#include "i915_timeline.h"
+#include "gt/intel_timeline.h"
 
 #define I915_GTT_PAGE_SIZE_4K	BIT_ULL(12)
 #define I915_GTT_PAGE_SIZE_64K	BIT_ULL(16)
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index da76e4d1c7f1..caf69d9d45ad 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -416,7 +416,7 @@ __i915_request_await_execution(struct i915_request *rq,
 }
 
 static void move_to_timeline(struct i915_request *request,
-			     struct i915_timeline *timeline)
+			     struct intel_timeline *timeline)
 {
 	GEM_BUG_ON(request->timeline == &request->engine->timeline);
 	lockdep_assert_held(&request->engine->timeline.lock);
@@ -646,7 +646,7 @@ request_alloc_slow(struct intel_context *ce, gfp_t gfp)
 struct i915_request *
 __i915_request_create(struct intel_context *ce, gfp_t gfp)
 {
-	struct i915_timeline *tl = ce->ring->timeline;
+	struct intel_timeline *tl = ce->ring->timeline;
 	struct i915_request *rq;
 	u32 seqno;
 	int ret;
@@ -695,7 +695,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
 		}
 	}
 
-	ret = i915_timeline_get_seqno(tl, rq, &seqno);
+	ret = intel_timeline_get_seqno(tl, rq, &seqno);
 	if (ret)
 		goto err_free;
 
@@ -819,7 +819,7 @@ i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
 		return 0;
 
 	signal = list_prev_entry(signal, ring_link);
-	if (i915_timeline_sync_is_later(rq->timeline, &signal->fence))
+	if (intel_timeline_sync_is_later(rq->timeline, &signal->fence))
 		return 0;
 
 	return i915_sw_fence_await_dma_fence(&rq->submit,
@@ -873,7 +873,7 @@ emit_semaphore_wait(struct i915_request *to,
 		return err;
 
 	/* We need to pin the signaler's HWSP until we are finished reading. */
-	err = i915_timeline_read_hwsp(from, to, &hwsp_offset);
+	err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
 	if (err)
 		return err;
 
@@ -984,7 +984,7 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
 
 		/* Squash repeated waits to the same timelines */
 		if (fence->context != rq->i915->mm.unordered_timeline &&
-		    i915_timeline_sync_is_later(rq->timeline, fence))
+		    intel_timeline_sync_is_later(rq->timeline, fence))
 			continue;
 
 		if (dma_fence_is_i915(fence))
@@ -998,7 +998,7 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
 
 		/* Record the latest fence used against each timeline */
 		if (fence->context != rq->i915->mm.unordered_timeline)
-			i915_timeline_sync_set(rq->timeline, fence);
+			intel_timeline_sync_set(rq->timeline, fence);
 	} while (--nchild);
 
 	return 0;
@@ -1136,7 +1136,7 @@ void i915_request_skip(struct i915_request *rq, int error)
 static struct i915_request *
 __i915_request_add_to_timeline(struct i915_request *rq)
 {
-	struct i915_timeline *timeline = rq->timeline;
+	struct intel_timeline *timeline = rq->timeline;
 	struct i915_request *prev;
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index c9f7d07991c8..82928ba97acc 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -40,8 +40,8 @@
 struct drm_file;
 struct drm_i915_gem_object;
 struct i915_request;
-struct i915_timeline;
-struct i915_timeline_cacheline;
+struct intel_timeline;
+struct intel_timeline_cacheline;
 
 struct i915_capture_list {
 	struct i915_capture_list *next;
@@ -112,7 +112,7 @@ struct i915_request {
 	struct intel_engine_cs *engine;
 	struct intel_context *hw_context;
 	struct intel_ring *ring;
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
 	struct list_head signal_link;
 
 	/*
@@ -175,7 +175,7 @@ struct i915_request {
 	 * inside the timeline's HWSP vma, but it is only valid while this
 	 * request has not completed and guarded by the timeline mutex.
 	 */
-	struct i915_timeline_cacheline *hwsp_cacheline;
+	struct intel_timeline_cacheline *hwsp_cacheline;
 
 	/** Position in the ring of the start of the request */
 	u32 head;
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index d5dc4427d664..2b31a4ee0b4c 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -12,7 +12,7 @@
 selftest(sanitycheck, i915_live_sanitycheck) /* keep first (igt selfcheck) */
 selftest(uncore, intel_uncore_live_selftests)
 selftest(workarounds, intel_workarounds_live_selftests)
-selftest(timelines, i915_timeline_live_selftests)
+selftest(timelines, intel_timeline_live_selftests)
 selftest(requests, i915_request_live_selftests)
 selftest(active, i915_active_live_selftests)
 selftest(objects, i915_gem_object_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
index 510eb176bb2c..b55da4d9ccba 100644
--- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
@@ -15,7 +15,7 @@ selftest(scatterlist, scatterlist_mock_selftests)
 selftest(syncmap, i915_syncmap_mock_selftests)
 selftest(uncore, intel_uncore_mock_selftests)
 selftest(engine, intel_engine_cs_mock_selftests)
-selftest(timelines, i915_timeline_mock_selftests)
+selftest(timelines, intel_timeline_mock_selftests)
 selftest(requests, i915_request_mock_selftests)
 selftest(objects, i915_gem_object_mock_selftests)
 selftest(phys, i915_gem_phys_mock_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 413aaff1534b..1676462b647d 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -69,7 +69,7 @@ static void mock_device_release(struct drm_device *dev)
 	i915_gem_contexts_fini(i915);
 	mutex_unlock(&i915->drm.struct_mutex);
 
-	i915_timelines_fini(i915);
+	intel_timelines_fini(i915);
 
 	drain_workqueue(i915->wq);
 	i915_gem_drain_freed_objects(i915);
@@ -200,7 +200,7 @@ struct drm_i915_private *mock_gem_device(void)
 
 	i915->gt.awake = true;
 
-	i915_timelines_init(i915);
+	intel_timelines_init(i915);
 
 	intel_gt_init(&i915->gt, i915);
 
@@ -233,7 +233,7 @@ struct drm_i915_private *mock_gem_device(void)
 	mock_engine_free(i915->engine[RCS0]);
 err_unlock:
 	mutex_unlock(&i915->drm.struct_mutex);
-	i915_timelines_fini(i915);
+	intel_timelines_fini(i915);
 	destroy_workqueue(i915->wq);
 err_drv:
 	drm_mode_config_cleanup(&i915->drm);
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[RFC 31/31] drm/i915: Eliminate dual personality of i915_scratch_offset

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Scratch vma lives under gt but the API used to work on i915. Make this
consistent by renaming the function to intel_gt_scratch_offset and make
it take struct intel_gt.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.h         |  5 ++++
 drivers/gpu/drm/i915/gt/intel_lrc.c        |  9 ++++---
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 29 ++++++++++++++--------
 drivers/gpu/drm/i915/i915_drv.h            |  5 ----
 drivers/gpu/drm/i915/i915_gem.c            | 21 ++++++++++++----
 drivers/gpu/drm/i915/i915_gpu_error.c      |  2 +-
 7 files changed, 46 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index cd8b22c934c5..aae22f6d4a72 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -739,7 +739,7 @@ static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
 	struct measure_breadcrumb *frame;
 	int dw = -ENOMEM;
 
-	GEM_BUG_ON(!engine->i915->gt.scratch);
+	GEM_BUG_ON(!engine->gt->scratch);
 
 	frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 	if (!frame)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 53fcf4f276d3..efc1bc381428 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -27,4 +27,9 @@ static inline void intel_gt_chipset_flush(struct intel_gt *gt)
 		intel_gtt_chipset_flush();
 }
 
+static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt)
+{
+	return i915_ggtt_offset(gt->scratch);
+}
+
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 80d4fd71b01f..d2e842d99c9c 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -135,6 +135,7 @@
 
 #include "gem/i915_gem_context.h"
 
+#include "gt/intel_gt.h"
 #include "i915_drv.h"
 #include "i915_gem_render_state.h"
 #include "i915_vgpu.h"
@@ -1728,7 +1729,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
 	/* NB no one else is allowed to scribble over scratch + 256! */
 	*batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
-	*batch++ = i915_scratch_offset(engine->i915) + 256;
+	*batch++ = intel_gt_scratch_offset(engine->gt) + 256;
 	*batch++ = 0;
 
 	*batch++ = MI_LOAD_REGISTER_IMM(1);
@@ -1742,7 +1743,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
 
 	*batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
-	*batch++ = i915_scratch_offset(engine->i915) + 256;
+	*batch++ = intel_gt_scratch_offset(engine->gt) + 256;
 	*batch++ = 0;
 
 	return batch;
@@ -1779,7 +1780,7 @@ static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
 				       PIPE_CONTROL_GLOBAL_GTT_IVB |
 				       PIPE_CONTROL_CS_STALL |
 				       PIPE_CONTROL_QW_WRITE,
-				       i915_scratch_offset(engine->i915) +
+				       intel_gt_scratch_offset(engine->gt) +
 				       2 * CACHELINE_BYTES);
 
 	*batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
@@ -2486,7 +2487,7 @@ static int gen8_emit_flush_render(struct i915_request *request,
 {
 	struct intel_engine_cs *engine = request->engine;
 	u32 scratch_addr =
-		i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;
+		intel_gt_scratch_offset(engine->gt) + 2 * CACHELINE_BYTES;
 	bool vf_flush_wa = false, dc_flush_wa = false;
 	u32 *cs, flags = 0;
 	int len;
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index 79d550e5d86a..b09e57ab3dd6 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -33,6 +33,8 @@
 
 #include "gem/i915_gem_context.h"
 
+#include "gt/intel_gt.h"
+
 #include "i915_drv.h"
 #include "i915_gem_render_state.h"
 #include "i915_trace.h"
@@ -75,7 +77,7 @@ gen2_render_ring_flush(struct i915_request *rq, u32 mode)
 	*cs++ = cmd;
 	while (num_store_dw--) {
 		*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
-		*cs++ = i915_scratch_offset(rq->i915);
+		*cs++ = intel_gt_scratch_offset(rq->engine->gt);
 		*cs++ = 0;
 	}
 	*cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
@@ -148,7 +150,8 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
 	 */
 	if (mode & EMIT_INVALIDATE) {
 		*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
-		*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
+		*cs++ = intel_gt_scratch_offset(rq->engine->gt) |
+			PIPE_CONTROL_GLOBAL_GTT;
 		*cs++ = 0;
 		*cs++ = 0;
 
@@ -156,7 +159,8 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
 			*cs++ = MI_FLUSH;
 
 		*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
-		*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
+		*cs++ = intel_gt_scratch_offset(rq->engine->gt) |
+			PIPE_CONTROL_GLOBAL_GTT;
 		*cs++ = 0;
 		*cs++ = 0;
 	}
@@ -208,7 +212,8 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
 static int
 gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
 {
-	u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
+	u32 scratch_addr =
+		intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES;
 	u32 *cs;
 
 	cs = intel_ring_begin(rq, 6);
@@ -241,7 +246,8 @@ gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
 static int
 gen6_render_ring_flush(struct i915_request *rq, u32 mode)
 {
-	u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
+	u32 scratch_addr =
+		intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES;
 	u32 *cs, flags = 0;
 	int ret;
 
@@ -299,7 +305,7 @@ static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 
 	*cs++ = GFX_OP_PIPE_CONTROL(4);
 	*cs++ = PIPE_CONTROL_QW_WRITE;
-	*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
+	*cs++ = intel_gt_scratch_offset(rq->engine->gt) | PIPE_CONTROL_GLOBAL_GTT;
 	*cs++ = 0;
 
 	/* Finally we can flush and with it emit the breadcrumb */
@@ -342,7 +348,8 @@ gen7_render_ring_cs_stall_wa(struct i915_request *rq)
 static int
 gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 {
-	u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
+	u32 scratch_addr =
+		intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES;
 	u32 *cs, flags = 0;
 
 	/*
@@ -1072,9 +1079,9 @@ i830_emit_bb_start(struct i915_request *rq,
 		   u64 offset, u32 len,
 		   unsigned int dispatch_flags)
 {
-	u32 *cs, cs_offset = i915_scratch_offset(rq->i915);
+	u32 *cs, cs_offset = intel_gt_scratch_offset(rq->engine->gt);
 
-	GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE);
+	GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);
 
 	cs = intel_ring_begin(rq, 6);
 	if (IS_ERR(cs))
@@ -1543,7 +1550,7 @@ static int flush_pd_dir(struct i915_request *rq)
 	/* Stall until the page table load is complete */
 	*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
-	*cs++ = i915_scratch_offset(rq->i915);
+	*cs++ = intel_gt_scratch_offset(rq->engine->gt);
 	*cs++ = MI_NOOP;
 
 	intel_ring_advance(rq, cs);
@@ -1659,7 +1666,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
 			/* Insert a delay before the next switch! */
 			*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
 			*cs++ = i915_mmio_reg_offset(last_reg);
-			*cs++ = i915_scratch_offset(rq->i915);
+			*cs++ = intel_gt_scratch_offset(rq->engine->gt);
 			*cs++ = MI_NOOP;
 		}
 		*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1957a085221b..b07a6bbb0342 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2832,11 +2832,6 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
 		return I915_HWS_CSB_WRITE_INDEX;
 }
 
-static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
-{
-	return i915_ggtt_offset(i915->gt.scratch);
-}
-
 static inline enum i915_map_type
 i915_coherent_map_type(struct drm_i915_private *i915)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ad1dc58a2374..c80e26c1437d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1423,9 +1423,9 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
 	goto out_ctx;
 }
 
-static int
-i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
+static int gt_init_scratch(struct intel_gt *gt, unsigned int size)
 {
+	struct drm_i915_private *i915 = gt->i915;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 	int ret;
@@ -1438,7 +1438,7 @@ i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
 		return PTR_ERR(obj);
 	}
 
-	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 	if (IS_ERR(vma)) {
 		ret = PTR_ERR(vma);
 		goto err_unref;
@@ -1448,7 +1448,7 @@ i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
 	if (ret)
 		goto err_unref;
 
-	i915->gt.scratch = vma;
+	gt->scratch = vma;
 	return 0;
 
 err_unref:
@@ -1456,9 +1456,20 @@ i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
 	return ret;
 }
 
+static int
+i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
+{
+	return gt_init_scratch(&i915->gt, size);
+}
+
+static void gt_fini_scratch(struct intel_gt *gt)
+{
+	i915_vma_unpin_and_release(&gt->scratch, 0);
+}
+
 static void i915_gem_fini_scratch(struct drm_i915_private *i915)
 {
-	i915_vma_unpin_and_release(&i915->gt.scratch, 0);
+	gt_fini_scratch(&i915->gt);
 }
 
 static int intel_engines_verify_workarounds(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index d0f9b4aba241..2589c6766dc4 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1445,7 +1445,7 @@ static void gem_record_rings(struct i915_gpu_state *error)
 			if (HAS_BROKEN_CS_TLB(i915))
 				ee->wa_batchbuffer =
 					i915_error_object_create(i915,
-								 i915->gt.scratch);
+								 engine->gt->scratch);
 			request_record_user_bo(request, ee);
 
 			ee->ctx =
-- 
2.20.1

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Re: [RFC 06/31] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 04:17:06PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Start using the newly introduced struct intel_gt to fuse together correct
> logical init flow with uncore for more removal of implicit dev_priv in
> mmio access.
> 
> v2:
>  * Move code to i915_gem_fence_reg. (Chris)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c           |  4 +--
>  drivers/gpu/drm/i915/i915_drv.h           |  1 -
>  drivers/gpu/drm/i915/i915_gem.c           | 25 +--------------
>  drivers/gpu/drm/i915/i915_gem_fence_reg.c | 37 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_gem_fence_reg.h |  3 ++
>  5 files changed, 43 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 97155c5eb7e1..1df76f7c717e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2935,7 +2935,7 @@ static int intel_runtime_suspend(struct device *kdev)
>  
>  		intel_uc_resume(dev_priv);
>  
> -		i915_gem_init_swizzling(dev_priv);
> +		intel_gt_init_swizzling(&dev_priv->gt);
>  		i915_gem_restore_fences(dev_priv);
>  
>  		enable_rpm_wakeref_asserts(dev_priv);
> @@ -3036,7 +3036,7 @@ static int intel_runtime_resume(struct device *kdev)
>  	 * No point of rolling back things in case of an error, as the best
>  	 * we can do is to hope that things will still work (and disable RPM).
>  	 */
> -	i915_gem_init_swizzling(dev_priv);
> +	intel_gt_init_swizzling(&dev_priv->gt);
>  	i915_gem_restore_fences(dev_priv);
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e2c8813c9355..1eb203fdee60 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2586,7 +2586,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
>  void i915_gem_init_mmio(struct drm_i915_private *i915);
>  int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
>  int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
> -void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
>  void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
>  void i915_gem_fini(struct drm_i915_private *dev_priv);
>  int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 7fdf252f9322..5c0db934315b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1205,29 +1205,6 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
>  	mutex_unlock(&i915->drm.struct_mutex);
>  }
>  
> -void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
> -{
> -	if (INTEL_GEN(dev_priv) < 5 ||
> -	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> -		return;
> -
> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> -				 DISP_TILE_SURFACE_SWIZZLING);
> -
> -	if (IS_GEN(dev_priv, 5))
> -		return;
> -
> -	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
> -	if (IS_GEN(dev_priv, 6))
> -		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> -	else if (IS_GEN(dev_priv, 7))
> -		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> -	else if (IS_GEN(dev_priv, 8))
> -		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> -	else
> -		BUG();
> -}
> -
>  static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
>  {
>  	I915_WRITE(RING_CTL(base), 0);
> @@ -1274,7 +1251,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>  	/* ...and determine whether they are sticking. */
>  	intel_gt_verify_workarounds(dev_priv, "init");
>  
> -	i915_gem_init_swizzling(dev_priv);
> +	intel_gt_init_swizzling(&dev_priv->gt);
>  
>  	/*
>  	 * At least 830 can leave some of the unused rings
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index 1c9466676caf..fc268599a0c3 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -834,3 +834,40 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>  
>  	i915_gem_restore_fences(i915);
>  }
> +
> +void intel_gt_init_swizzling(struct intel_gt *gt)
> +{
> +	struct drm_i915_private *i915 = gt->i915;
> +	struct intel_uncore *uncore = gt->uncore;
> +
> +	if (INTEL_GEN(i915) < 5 ||
> +	    i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> +		return;
> +
> +	intel_uncore_write(uncore,
> +			   DISP_ARB_CTL,
> +			   intel_uncore_read(uncore, DISP_ARB_CTL) |
> +			   DISP_TILE_SURFACE_SWIZZLING);

could we change this to intel_uncore_rmw ?

> +
> +	if (IS_GEN(i915, 5))
> +		return;
> +
> +	intel_uncore_write(uncore,
> +			   TILECTL,
> +			   intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL);

and here as well?

> +
> +	if (IS_GEN(i915, 6))
> +		intel_uncore_write(uncore,
> +				   ARB_MODE,
> +				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> +	else if (IS_GEN(i915, 7))
> +		intel_uncore_write(uncore,
> +				   ARB_MODE,
> +				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> +	else if (IS_GEN(i915, 8))
> +		intel_uncore_write(uncore,
> +				   GAMTARBMODE,
> +				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> +	else
> +		MISSING_CASE(INTEL_GEN(i915));
> +}
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
> index d2da98828179..37e4f104f7c0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.h
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
> @@ -32,6 +32,7 @@ struct drm_i915_gem_object;
>  struct drm_i915_private;
>  struct i915_ggtt;
>  struct i915_vma;
> +struct intel_gt;
>  struct sg_table;
>  
>  #define I965_FENCE_PAGE 4096UL
> @@ -66,4 +67,6 @@ void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
>  
>  void i915_ggtt_init_fences(struct i915_ggtt *ggtt);
>  
> +void intel_gt_init_swizzling(struct intel_gt *gt);
> +
>  #endif
> -- 
> 2.20.1
> 
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Re: [RFC v4 00/31] Implicit dev_priv removal and GT compartmentalization

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 04:17:00PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Most of v3 review feedback plus more of:
> """"
> Also, while nosing around in the code I have spotted more opportunities to
> compartmentalize, either using intel_gt, or some other object as appropriate.
> """
> 
> This time even smoke tested.

Oh, I forgot to tell you that even your v1 version was smoke tested and
it was working for my cases :)

> 
> Tvrtko Ursulin (31):
>   drm/i915: Convert intel_vgt_(de)balloon to uncore
>   drm/i915: Introduce struct intel_gt as replacement for anonymous
>     i915->gt
>   drm/i915: Move intel_gt initialization to a separate file
>   drm/i915: Store some backpointers in struct intel_gt
>   drm/i915: Make i915_check_and_clear_faults take intel_gt
>   drm/i915: Convert i915_gem_init_swizzling to intel_gt
>   drm/i915: Convert init_unused_rings to intel_gt
>   drm/i915: Convert gt workarounds to intel_gt
>   drm/i915: Store backpointer to intel_gt in the engine
>   drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt
>   drm/i915: Convert i915_ppgtt_init_hw to intel_gt
>   drm/i915: Consolidate some open coded mmio rmw
>   drm/i915: Convert i915_gem_init_hw to intel_gt
>   drm/i915: Move intel_engines_resume into common init
>   drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw
>   drm/i915: Compartmentalize i915_ggtt_probe_hw
>   drm/i915: Compartmentalize i915_ggtt_init_hw
>   drm/i915: Make ggtt invalidation work on ggtt
>   drm/i915: Store intel_gt backpointer in vm
>   drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings
>   drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt
>   drm/i915: Move i915_gem_chipset_flush to intel_gt
>   drm/i915: Compartmentalize timeline_init/park/fini
>   drm/i915: Compartmentalize i915_ggtt_cleanup_hw
>   drm/i915: Compartmentalize i915_gem_init_ggtt
>   drm/i915: Store ggtt pointer in intel_gt
>   drm/i915: Compartmentalize ring buffer creation
>   drm/i915: Save trip via top-level i915 in a few more places
>   drm/i915: Make timelines gt centric
>   drm/i915: Rename i915_timeline to intel_timeline and move under gt
>   drm/i915: Eliminate dual personality of i915_scratch_offset
> 
>  drivers/gpu/drm/i915/Makefile                 |   3 +-
>  drivers/gpu/drm/i915/Makefile.header-test     |   1 -
>  drivers/gpu/drm/i915/gem/i915_gem_context.c   |  10 +-
>  .../gpu/drm/i915/gem/i915_gem_context_types.h |   4 +-
>  .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |   5 +-
>  drivers/gpu/drm/i915/gem/i915_gem_object.c    |   5 +-
>  drivers/gpu/drm/i915/gem/i915_gem_phys.c      |   3 +-
>  drivers/gpu/drm/i915/gem/i915_gem_pm.c        |   2 +-
>  .../gpu/drm/i915/gem/selftests/huge_pages.c   |   7 +-
>  .../drm/i915/gem/selftests/i915_gem_context.c |   3 +-
>  .../drm/i915/gem/selftests/i915_gem_mman.c    |   3 +-
>  drivers/gpu/drm/i915/gt/intel_engine.h        |   4 +-
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  33 +-
>  drivers/gpu/drm/i915/gt/intel_engine_types.h  |   8 +-
>  drivers/gpu/drm/i915/gt/intel_gt.c            | 195 ++++++++++
>  drivers/gpu/drm/i915/gt/intel_gt.h            |  35 ++
>  drivers/gpu/drm/i915/gt/intel_gt_types.h      |  61 +++
>  drivers/gpu/drm/i915/gt/intel_lrc.c           |  32 +-
>  drivers/gpu/drm/i915/gt/intel_mocs.c          |  52 ++-
>  drivers/gpu/drm/i915/gt/intel_mocs.h          |   3 +-
>  drivers/gpu/drm/i915/gt/intel_reset.c         | 128 +-----
>  drivers/gpu/drm/i915/gt/intel_reset.h         |   2 -
>  drivers/gpu/drm/i915/gt/intel_ringbuffer.c    |  68 ++--
>  .../{i915_timeline.c => gt/intel_timeline.c}  | 204 +++++-----
>  .../{i915_timeline.h => gt/intel_timeline.h}  |  71 ++--
>  .../intel_timeline_types.h}                   |   8 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   |  12 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.h   |   6 +-
>  drivers/gpu/drm/i915/gt/mock_engine.c         |  18 +-
>  drivers/gpu/drm/i915/gt/selftest_hangcheck.c  |  20 +-
>  .../selftest_timeline.c}                      | 124 +++---
>  .../gpu/drm/i915/gt/selftest_workarounds.c    |   7 +-
>  .../i915/{ => gt}/selftests/mock_timeline.c   |   8 +-
>  .../i915/{ => gt}/selftests/mock_timeline.h   |   6 +-
>  drivers/gpu/drm/i915/i915_drv.c               |   9 +-
>  drivers/gpu/drm/i915/i915_drv.h               |  52 +--
>  drivers/gpu/drm/i915/i915_gem.c               | 227 +++++------
>  drivers/gpu/drm/i915/i915_gem_fence_reg.c     |  37 ++
>  drivers/gpu/drm/i915/i915_gem_fence_reg.h     |   3 +
>  drivers/gpu/drm/i915/i915_gem_gtt.c           | 367 +++++++++++-------
>  drivers/gpu/drm/i915/i915_gem_gtt.h           |  10 +-
>  drivers/gpu/drm/i915/i915_gem_render_state.c  |   2 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c         |   4 +-
>  drivers/gpu/drm/i915/i915_request.c           |  16 +-
>  drivers/gpu/drm/i915/i915_request.h           |   8 +-
>  drivers/gpu/drm/i915/i915_vgpu.c              |  24 +-
>  drivers/gpu/drm/i915/i915_vgpu.h              |   4 +-
>  drivers/gpu/drm/i915/i915_vma.c               |   3 +-
>  drivers/gpu/drm/i915/intel_wopcm.c            |  31 +-
>  drivers/gpu/drm/i915/intel_wopcm.h            |   4 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |   2 +-
>  .../drm/i915/selftests/i915_live_selftests.h  |   2 +-
>  .../drm/i915/selftests/i915_mock_selftests.h  |   2 +-
>  drivers/gpu/drm/i915/selftests/i915_request.c |  10 +-
>  drivers/gpu/drm/i915/selftests/igt_spinner.c  |   7 +-
>  drivers/gpu/drm/i915/selftests/igt_spinner.h  |   3 +
>  .../gpu/drm/i915/selftests/mock_gem_device.c  |  11 +-
>  57 files changed, 1143 insertions(+), 846 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_types.h
>  rename drivers/gpu/drm/i915/{i915_timeline.c => gt/intel_timeline.c} (72%)
>  rename drivers/gpu/drm/i915/{i915_timeline.h => gt/intel_timeline.h} (53%)
>  rename drivers/gpu/drm/i915/{i915_timeline_types.h => gt/intel_timeline_types.h} (92%)
>  rename drivers/gpu/drm/i915/{selftests/i915_timeline.c => gt/selftest_timeline.c} (86%)
>  rename drivers/gpu/drm/i915/{ => gt}/selftests/mock_timeline.c (70%)
>  rename drivers/gpu/drm/i915/{ => gt}/selftests/mock_timeline.h (53%)
> 
> -- 
> 2.20.1
> 
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Re: [RFC 03/31] drm/i915: Move intel_gt initialization to a separate file

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 04:17:03PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> As it will grow in a following patch make a new home for it.
> 
> v2:
>  * Convert mock_gem_device as well. (Chris)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/Makefile                    |  1 +
>  drivers/gpu/drm/i915/gt/intel_gt.c               | 15 +++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_gt.h               | 14 ++++++++++++++
>  drivers/gpu/drm/i915/i915_gem.c                  |  6 ++----
>  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  5 ++---
>  5 files changed, 34 insertions(+), 7 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index c0a7b2994077..8df1bf2855d0 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -73,6 +73,7 @@ gt-y += \
>  	gt/intel_context.o \
>  	gt/intel_engine_cs.o \
>  	gt/intel_engine_pm.o \
> +	gt/intel_gt.o \
>  	gt/intel_gt_pm.o \
>  	gt/intel_hangcheck.o \
>  	gt/intel_lrc.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> new file mode 100644
> index 000000000000..807c5f746110
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -0,0 +1,15 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#include "intel_gt.h"
> +
> +void intel_gt_init(struct intel_gt *gt)
> +{
> +	INIT_LIST_HEAD(&gt->active_rings);
> +	INIT_LIST_HEAD(&gt->closed_vma);
> +
> +	spin_lock_init(&gt->closed_lock);
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> new file mode 100644
> index 000000000000..d0b599dd6d0f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -0,0 +1,14 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#ifndef __INTEL_GT__
> +#define __INTEL_GT__
> +
> +#include "gt/intel_gt_types.h"
> +
> +void intel_gt_init(struct intel_gt *gt);
> +
> +#endif /* __INTEL_GT_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 7232361973fd..d5897e13897b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -44,6 +44,7 @@
>  #include "gem/i915_gem_pm.h"
>  #include "gem/i915_gemfs.h"
>  #include "gt/intel_engine_pm.h"
> +#include "gt/intel_gt.h"
>  #include "gt/intel_gt_pm.h"
>  #include "gt/intel_mocs.h"
>  #include "gt/intel_reset.h"
> @@ -1748,12 +1749,9 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
>  {
>  	int err;
>  
> +	intel_gt_init(&dev_priv->gt);
>  	intel_gt_pm_init(dev_priv);
>  
> -	INIT_LIST_HEAD(&dev_priv->gt.active_rings);
> -	INIT_LIST_HEAD(&dev_priv->gt.closed_vma);
> -	spin_lock_init(&dev_priv->gt.closed_lock);
> -
>  	i915_gem_init__mm(dev_priv);
>  	i915_gem_init__pm(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index b7f3fbb4ae89..fbcccc3cf85a 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -25,6 +25,7 @@
>  #include <linux/pm_domain.h>
>  #include <linux/pm_runtime.h>
>  
> +#include "gt/intel_gt.h"
>  #include "gt/mock_engine.h"
>  
>  #include "mock_request.h"
> @@ -201,9 +202,7 @@ struct drm_i915_private *mock_gem_device(void)
>  
>  	i915_timelines_init(i915);
>  
> -	INIT_LIST_HEAD(&i915->gt.active_rings);
> -	INIT_LIST_HEAD(&i915->gt.closed_vma);
> -	spin_lock_init(&i915->gt.closed_lock);
> +	intel_gt_init(&i915->gt);
>  
>  	mutex_lock(&i915->drm.struct_mutex);
>  
> -- 
> 2.20.1
> 
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Re: [RFC 06/31] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Tvrtko Ursulin]

On 14/06/2019 16:25, Rodrigo Vivi wrote:
> On Fri, Jun 14, 2019 at 04:17:06PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Start using the newly introduced struct intel_gt to fuse together correct
>> logical init flow with uncore for more removal of implicit dev_priv in
>> mmio access.
>>
>> v2:
>>   * Move code to i915_gem_fence_reg. (Chris)
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.c           |  4 +--
>>   drivers/gpu/drm/i915/i915_drv.h           |  1 -
>>   drivers/gpu/drm/i915/i915_gem.c           | 25 +--------------
>>   drivers/gpu/drm/i915/i915_gem_fence_reg.c | 37 +++++++++++++++++++++++
>>   drivers/gpu/drm/i915/i915_gem_fence_reg.h |  3 ++
>>   5 files changed, 43 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 97155c5eb7e1..1df76f7c717e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -2935,7 +2935,7 @@ static int intel_runtime_suspend(struct device *kdev)
>>   
>>   		intel_uc_resume(dev_priv);
>>   
>> -		i915_gem_init_swizzling(dev_priv);
>> +		intel_gt_init_swizzling(&dev_priv->gt);
>>   		i915_gem_restore_fences(dev_priv);
>>   
>>   		enable_rpm_wakeref_asserts(dev_priv);
>> @@ -3036,7 +3036,7 @@ static int intel_runtime_resume(struct device *kdev)
>>   	 * No point of rolling back things in case of an error, as the best
>>   	 * we can do is to hope that things will still work (and disable RPM).
>>   	 */
>> -	i915_gem_init_swizzling(dev_priv);
>> +	intel_gt_init_swizzling(&dev_priv->gt);
>>   	i915_gem_restore_fences(dev_priv);
>>   
>>   	/*
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index e2c8813c9355..1eb203fdee60 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2586,7 +2586,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
>>   void i915_gem_init_mmio(struct drm_i915_private *i915);
>>   int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
>>   int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
>> -void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
>>   void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
>>   void i915_gem_fini(struct drm_i915_private *dev_priv);
>>   int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>> index 7fdf252f9322..5c0db934315b 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.c
>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>> @@ -1205,29 +1205,6 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
>>   	mutex_unlock(&i915->drm.struct_mutex);
>>   }
>>   
>> -void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
>> -{
>> -	if (INTEL_GEN(dev_priv) < 5 ||
>> -	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>> -		return;
>> -
>> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>> -				 DISP_TILE_SURFACE_SWIZZLING);
>> -
>> -	if (IS_GEN(dev_priv, 5))
>> -		return;
>> -
>> -	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
>> -	if (IS_GEN(dev_priv, 6))
>> -		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>> -	else if (IS_GEN(dev_priv, 7))
>> -		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
>> -	else if (IS_GEN(dev_priv, 8))
>> -		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
>> -	else
>> -		BUG();
>> -}
>> -
>>   static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
>>   {
>>   	I915_WRITE(RING_CTL(base), 0);
>> @@ -1274,7 +1251,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>>   	/* ...and determine whether they are sticking. */
>>   	intel_gt_verify_workarounds(dev_priv, "init");
>>   
>> -	i915_gem_init_swizzling(dev_priv);
>> +	intel_gt_init_swizzling(&dev_priv->gt);
>>   
>>   	/*
>>   	 * At least 830 can leave some of the unused rings
>> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>> index 1c9466676caf..fc268599a0c3 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>> @@ -834,3 +834,40 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>>   
>>   	i915_gem_restore_fences(i915);
>>   }
>> +
>> +void intel_gt_init_swizzling(struct intel_gt *gt)
>> +{
>> +	struct drm_i915_private *i915 = gt->i915;
>> +	struct intel_uncore *uncore = gt->uncore;
>> +
>> +	if (INTEL_GEN(i915) < 5 ||
>> +	    i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>> +		return;
>> +
>> +	intel_uncore_write(uncore,
>> +			   DISP_ARB_CTL,
>> +			   intel_uncore_read(uncore, DISP_ARB_CTL) |
>> +			   DISP_TILE_SURFACE_SWIZZLING);
> 
> could we change this to intel_uncore_rmw ?
> 
>> +
>> +	if (IS_GEN(i915, 5))
>> +		return;
>> +
>> +	intel_uncore_write(uncore,
>> +			   TILECTL,
>> +			   intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL);
> 
> and here as well?

Yes of course.. marking as TODO.

Regards,

Tvrtko

>> +
>> +	if (IS_GEN(i915, 6))
>> +		intel_uncore_write(uncore,
>> +				   ARB_MODE,
>> +				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>> +	else if (IS_GEN(i915, 7))
>> +		intel_uncore_write(uncore,
>> +				   ARB_MODE,
>> +				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
>> +	else if (IS_GEN(i915, 8))
>> +		intel_uncore_write(uncore,
>> +				   GAMTARBMODE,
>> +				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
>> +	else
>> +		MISSING_CASE(INTEL_GEN(i915));
>> +}
>> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
>> index d2da98828179..37e4f104f7c0 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
>> @@ -32,6 +32,7 @@ struct drm_i915_gem_object;
>>   struct drm_i915_private;
>>   struct i915_ggtt;
>>   struct i915_vma;
>> +struct intel_gt;
>>   struct sg_table;
>>   
>>   #define I965_FENCE_PAGE 4096UL
>> @@ -66,4 +67,6 @@ void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
>>   
>>   void i915_ggtt_init_fences(struct i915_ggtt *ggtt);
>>   
>> +void intel_gt_init_swizzling(struct intel_gt *gt);
>> +
>>   #endif
>> -- 
>> 2.20.1
>>
> 
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✗ Fi.CI.BAT: failure for Implicit dev_priv removal and GT compartmentalization (rev6)

[Patchwork]

== Series Details ==

Series: Implicit dev_priv removal and GT compartmentalization (rev6)
URL   : https://patchwork.freedesktop.org/series/62046/
State : failure

== Summary ==

Applying: drm/i915: Convert intel_vgt_(de)balloon to uncore
Applying: drm/i915: Introduce struct intel_gt as replacement for anonymous i915->gt
Applying: drm/i915: Move intel_gt initialization to a separate file
Applying: drm/i915: Store some backpointers in struct intel_gt
Applying: drm/i915: Make i915_check_and_clear_faults take intel_gt
Applying: drm/i915: Convert i915_gem_init_swizzling to intel_gt
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_drv.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0006 drm/i915: Convert i915_gem_init_swizzling to intel_gt
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [RFC 13/31] drm/i915: Convert i915_gem_init_hw to intel_gt

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 04:17:13PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> More removal of implicit dev_priv from using old mmio accessors.
> 
> Actually the top level function remains but is split into a part which
> writes to i915 and part which operates on intel_gt in order to initialize
> the hardware.
> 
> GuC and engines are the only odd ones out remaining.

we can take care of them later, but soon :)

> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem.c | 66 ++++++++++++++++++++-------------
>  1 file changed, 40 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e54cd30534dc..b6f450e782e7 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1234,28 +1234,32 @@ static void init_unused_rings(struct intel_gt *gt)
>  	}
>  }
>  
> -int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> +static int init_hw(struct intel_gt *gt)
>  {
> +	struct drm_i915_private *i915 = gt->i915;
> +	struct intel_uncore *uncore = gt->uncore;
>  	int ret;
>  
> -	dev_priv->gt.last_init_time = ktime_get();
> +	gt->last_init_time = ktime_get();
>  
>  	/* Double layer security blanket, see i915_gem_init() */
> -	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> +	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>  
> -	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
> -		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
> +	if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
> +		intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
>  
> -	if (IS_HASWELL(dev_priv))
> -		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> -			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
> +	if (IS_HASWELL(i915))
> +		intel_uncore_write(uncore,
> +				   MI_PREDICATE_RESULT_2,
> +				   IS_HSW_GT3(i915) ?
> +				   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>  
>  	/* Apply the GT workarounds... */
> -	intel_gt_apply_workarounds(&dev_priv->gt);
> +	intel_gt_apply_workarounds(gt);
>  	/* ...and determine whether they are sticking. */
> -	intel_gt_verify_workarounds(&dev_priv->gt, "init");
> +	intel_gt_verify_workarounds(gt, "init");
>  
> -	intel_gt_init_swizzling(&dev_priv->gt);
> +	intel_gt_init_swizzling(gt);
>  
>  	/*
>  	 * At least 830 can leave some of the unused rings
> @@ -1263,48 +1267,58 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>  	 * will prevent c3 entry. Makes sure all unused rings
>  	 * are totally idle.
>  	 */
> -	init_unused_rings(&dev_priv->gt);
> -
> -	BUG_ON(!dev_priv->kernel_context);
> -	ret = i915_terminally_wedged(dev_priv);
> -	if (ret)
> -		goto out;
> +	init_unused_rings(gt);
>  
> -	ret = i915_ppgtt_init_hw(&dev_priv->gt);
> +	ret = i915_ppgtt_init_hw(gt);
>  	if (ret) {
>  		DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
>  		goto out;
>  	}
>  
> -	ret = intel_wopcm_init_hw(&dev_priv->wopcm);
> +	ret = intel_wopcm_init_hw(&i915->wopcm);
>  	if (ret) {
>  		DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
>  		goto out;
>  	}
>  
>  	/* We can't enable contexts until all firmware is loaded */
> -	ret = intel_uc_init_hw(dev_priv);
> +	ret = intel_uc_init_hw(i915);
>  	if (ret) {
>  		DRM_ERROR("Enabling uc failed (%d)\n", ret);
>  		goto out;
>  	}
>  
> -	intel_mocs_init_l3cc_table(&dev_priv->gt);
> +	intel_mocs_init_l3cc_table(gt);
>  
>  	/* Only when the HW is re-initialised, can we replay the requests */
> -	ret = intel_engines_resume(dev_priv);
> +	ret = intel_engines_resume(i915);
>  	if (ret)
>  		goto cleanup_uc;
>  
> -	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> +	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>  
> -	intel_engines_set_scheduler_caps(dev_priv);
>  	return 0;
>  
>  cleanup_uc:
> -	intel_uc_fini_hw(dev_priv);
> +	intel_uc_fini_hw(i915);
>  out:
> -	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> +	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> +
> +	return ret;
> +}
> +
> +int i915_gem_init_hw(struct drm_i915_private *i915)
> +{
> +	int ret;
> +
> +	BUG_ON(!i915->kernel_context);
> +	ret = i915_terminally_wedged(i915);
> +	if (ret)
> +		return ret;
> +
> +	ret = init_hw(&i915->gt);
> +
> +	intel_engines_set_scheduler_caps(i915);
>  
>  	return ret;
>  }
> -- 
> 2.20.1
> 
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Re: [RFC 15/31] drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 04:17:15PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> More legacy mmio accessor removal. We pass in intel_gt explicitly allowing
> code to use new intel_uncore_read/write helpers.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem.c    |  2 +-
>  drivers/gpu/drm/i915/intel_wopcm.c | 31 ++++++++++++++++--------------
>  drivers/gpu/drm/i915/intel_wopcm.h |  4 +++-
>  3 files changed, 21 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 77d9d092b2f4..b7f88e2bd7df 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1275,7 +1275,7 @@ static int init_hw(struct intel_gt *gt)
>  		goto out;
>  	}
>  
> -	ret = intel_wopcm_init_hw(&i915->wopcm);
> +	ret = intel_wopcm_init_hw(&i915->wopcm, gt);
>  	if (ret) {
>  		DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
>  		goto out;
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
> index 7b4ba84b9fb8..931987e37241 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -225,17 +225,18 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
>  	return 0;
>  }
>  
> -static inline int write_and_verify(struct drm_i915_private *dev_priv,
> -				   i915_reg_t reg, u32 val, u32 mask,
> -				   u32 locked_bit)
> +static int
> +write_and_verify(struct intel_gt *gt,
> +		 i915_reg_t reg, u32 val, u32 mask, u32 locked_bit)
>  {
> +	struct intel_uncore *uncore = gt->uncore;
>  	u32 reg_val;
>  
>  	GEM_BUG_ON(val & ~mask);
>  
> -	I915_WRITE(reg, val);
> +	intel_uncore_write(uncore, reg, val);
>  
> -	reg_val = I915_READ(reg);
> +	reg_val = intel_uncore_read(uncore, reg);
>  
>  	return (reg_val & mask) != (val | locked_bit) ? -EIO : 0;
>  }
> @@ -250,29 +251,30 @@ static inline int write_and_verify(struct drm_i915_private *dev_priv,
>   *
>   * Return: 0 on success. -EIO if registers were locked with incorrect values.
>   */
> -int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
> +int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt)
>  {
> -	struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
> +	struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
> +	struct intel_uncore *uncore = gt->uncore;
>  	u32 huc_agent;
>  	u32 mask;
>  	int err;
>  
> -	if (!USES_GUC(dev_priv))
> +	if (!USES_GUC(i915))
>  		return 0;
>  
> -	GEM_BUG_ON(!HAS_GUC(dev_priv));
> +	GEM_BUG_ON(!HAS_GUC(i915));
>  	GEM_BUG_ON(!wopcm->guc.size);
>  	GEM_BUG_ON(!wopcm->guc.base);
>  
> -	err = write_and_verify(dev_priv, GUC_WOPCM_SIZE, wopcm->guc.size,
> +	err = write_and_verify(gt, GUC_WOPCM_SIZE, wopcm->guc.size,
>  			       GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED,
>  			       GUC_WOPCM_SIZE_LOCKED);
>  	if (err)
>  		goto err_out;
>  
> -	huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
> +	huc_agent = USES_HUC(i915) ? HUC_LOADING_AGENT_GUC : 0;
>  	mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
> -	err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
> +	err = write_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
>  			       wopcm->guc.base | huc_agent, mask,
>  			       GUC_WOPCM_OFFSET_VALID);
>  	if (err)
> @@ -283,8 +285,9 @@ int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
>  err_out:
>  	DRM_ERROR("Failed to init WOPCM registers:\n");
>  	DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
> -		  I915_READ(DMA_GUC_WOPCM_OFFSET));
> -	DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));
> +		  intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
> +	DRM_ERROR("GUC_WOPCM_SIZE=%#x\n",
> +		  intel_uncore_read(uncore, GUC_WOPCM_SIZE));
>  
>  	return err;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.h b/drivers/gpu/drm/i915/intel_wopcm.h
> index 114401971520..56aaed4d64ff 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.h
> +++ b/drivers/gpu/drm/i915/intel_wopcm.h
> @@ -9,6 +9,8 @@
>  
>  #include <linux/types.h>
>  
> +struct intel_gt;
> +
>  /**
>   * struct intel_wopcm - Overall WOPCM info and WOPCM regions.
>   * @size: Size of overall WOPCM.
> @@ -41,6 +43,6 @@ static inline u32 intel_wopcm_guc_size(struct intel_wopcm *wopcm)
>  
>  void intel_wopcm_init_early(struct intel_wopcm *wopcm);
>  int intel_wopcm_init(struct intel_wopcm *wopcm);
> -int intel_wopcm_init_hw(struct intel_wopcm *wopcm);
> +int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt);
>  
>  #endif
> -- 
> 2.20.1
> 
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Re: [RFC 16/31] drm/i915: Compartmentalize i915_ggtt_probe_hw

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 04:17:16PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Having made start to better code compartmentalization by introducing
> struct intel_gt, continue the theme elsewhere in code by making functions
> take parameters take what logically makes most sense for them instead of
> the global struct drm_i915_private.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 31 +++++++++++++++++++----------
>  1 file changed, 21 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0810c1655224..c88213fa18af 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3507,21 +3507,16 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
>  	return 0;
>  }
>  
> -/**
> - * i915_ggtt_probe_hw - Probe GGTT hardware location
> - * @dev_priv: i915 device
> - */
> -int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
> +static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct drm_i915_private *i915)
>  {
> -	struct i915_ggtt *ggtt = &dev_priv->ggtt;
>  	int ret;
>  
> -	ggtt->vm.i915 = dev_priv;
> -	ggtt->vm.dma = &dev_priv->drm.pdev->dev;
> +	ggtt->vm.i915 = i915;
> +	ggtt->vm.dma = &i915->drm.pdev->dev;
>  
> -	if (INTEL_GEN(dev_priv) <= 5)
> +	if (INTEL_GEN(i915) <= 5)
>  		ret = i915_gmch_probe(ggtt);
> -	else if (INTEL_GEN(dev_priv) < 8)
> +	else if (INTEL_GEN(i915) < 8)
>  		ret = gen6_gmch_probe(ggtt);
>  	else
>  		ret = gen8_gmch_probe(ggtt);
> @@ -3549,6 +3544,22 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
>  	DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20);
>  	DRM_DEBUG_DRIVER("DSM size = %lluM\n",
>  			 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
> +
> +	return 0;
> +}
> +
> +/**
> + * i915_ggtt_probe_hw - Probe GGTT hardware location
> + * @dev_priv: i915 device
> + */
> +int i915_ggtt_probe_hw(struct drm_i915_private *i915)
> +{
> +	int ret;
> +
> +	ret = ggtt_probe_hw(&i915->ggtt, i915);
> +	if (ret)
> +		return ret;
> +
>  	if (intel_vtd_active())
>  		DRM_INFO("VT-d active for gfx access\n");
>  
> -- 
> 2.20.1
> 
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Re: [RFC 03/31] drm/i915: Move intel_gt initialization to a separate file

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:03)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> As it will grow in a following patch make a new home for it.
> 
> v2:
>  * Convert mock_gem_device as well. (Chris)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                    |  1 +
>  drivers/gpu/drm/i915/gt/intel_gt.c               | 15 +++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_gt.h               | 14 ++++++++++++++
>  drivers/gpu/drm/i915/i915_gem.c                  |  6 ++----
>  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  5 ++---
>  5 files changed, 34 insertions(+), 7 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index c0a7b2994077..8df1bf2855d0 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -73,6 +73,7 @@ gt-y += \
>         gt/intel_context.o \
>         gt/intel_engine_cs.o \
>         gt/intel_engine_pm.o \
> +       gt/intel_gt.o \
>         gt/intel_gt_pm.o \
>         gt/intel_hangcheck.o \
>         gt/intel_lrc.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> new file mode 100644
> index 000000000000..807c5f746110
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -0,0 +1,15 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#include "intel_gt.h"
> +
> +void intel_gt_init(struct intel_gt *gt)

Please use intel_gt_init_early() to keep the phase known.

Hmm, I did expect you to pull across i915_gem_init_hw() as well, or did
I miss that?
-Chris
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Re: [RFC 03/31] drm/i915: Move intel_gt initialization to a separate file

[Chris Wilson]

Quoting Chris Wilson (2019-06-14 17:13:03)
> Quoting Tvrtko Ursulin (2019-06-14 16:17:03)
> > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > 
> > As it will grow in a following patch make a new home for it.
> > 
> > v2:
> >  * Convert mock_gem_device as well. (Chris)
> > 
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >  drivers/gpu/drm/i915/Makefile                    |  1 +
> >  drivers/gpu/drm/i915/gt/intel_gt.c               | 15 +++++++++++++++
> >  drivers/gpu/drm/i915/gt/intel_gt.h               | 14 ++++++++++++++
> >  drivers/gpu/drm/i915/i915_gem.c                  |  6 ++----
> >  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  5 ++---
> >  5 files changed, 34 insertions(+), 7 deletions(-)
> >  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
> >  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h
> > 
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index c0a7b2994077..8df1bf2855d0 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -73,6 +73,7 @@ gt-y += \
> >         gt/intel_context.o \
> >         gt/intel_engine_cs.o \
> >         gt/intel_engine_pm.o \
> > +       gt/intel_gt.o \
> >         gt/intel_gt_pm.o \
> >         gt/intel_hangcheck.o \
> >         gt/intel_lrc.o \
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > new file mode 100644
> > index 000000000000..807c5f746110
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > @@ -0,0 +1,15 @@
> > +/*
> > + * SPDX-License-Identifier: MIT
> > + *
> > + * Copyright © 2019 Intel Corporation
> > + */
> > +
> > +#include "intel_gt.h"
> > +
> > +void intel_gt_init(struct intel_gt *gt)
> 
> Please use intel_gt_init_early() to keep the phase known.

(And yes, I know I violated my own rule, it's easier to spot in review
:)
-Chris
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Re: [RFC 06/31] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 04:36:57PM +0100, Tvrtko Ursulin wrote:
> 
> On 14/06/2019 16:25, Rodrigo Vivi wrote:
> > On Fri, Jun 14, 2019 at 04:17:06PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > 
> > > Start using the newly introduced struct intel_gt to fuse together correct
> > > logical init flow with uncore for more removal of implicit dev_priv in
> > > mmio access.
> > > 
> > > v2:
> > >   * Move code to i915_gem_fence_reg. (Chris)
> > > 
> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/i915_drv.c           |  4 +--
> > >   drivers/gpu/drm/i915/i915_drv.h           |  1 -
> > >   drivers/gpu/drm/i915/i915_gem.c           | 25 +--------------
> > >   drivers/gpu/drm/i915/i915_gem_fence_reg.c | 37 +++++++++++++++++++++++
> > >   drivers/gpu/drm/i915/i915_gem_fence_reg.h |  3 ++
> > >   5 files changed, 43 insertions(+), 27 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index 97155c5eb7e1..1df76f7c717e 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -2935,7 +2935,7 @@ static int intel_runtime_suspend(struct device *kdev)
> > >   		intel_uc_resume(dev_priv);
> > > -		i915_gem_init_swizzling(dev_priv);
> > > +		intel_gt_init_swizzling(&dev_priv->gt);
> > >   		i915_gem_restore_fences(dev_priv);
> > >   		enable_rpm_wakeref_asserts(dev_priv);
> > > @@ -3036,7 +3036,7 @@ static int intel_runtime_resume(struct device *kdev)
> > >   	 * No point of rolling back things in case of an error, as the best
> > >   	 * we can do is to hope that things will still work (and disable RPM).
> > >   	 */
> > > -	i915_gem_init_swizzling(dev_priv);
> > > +	intel_gt_init_swizzling(&dev_priv->gt);
> > >   	i915_gem_restore_fences(dev_priv);
> > >   	/*
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index e2c8813c9355..1eb203fdee60 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -2586,7 +2586,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
> > >   void i915_gem_init_mmio(struct drm_i915_private *i915);
> > >   int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
> > >   int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
> > > -void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
> > >   void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
> > >   void i915_gem_fini(struct drm_i915_private *dev_priv);
> > >   int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
> > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > > index 7fdf252f9322..5c0db934315b 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > @@ -1205,29 +1205,6 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
> > >   	mutex_unlock(&i915->drm.struct_mutex);
> > >   }
> > > -void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
> > > -{
> > > -	if (INTEL_GEN(dev_priv) < 5 ||
> > > -	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> > > -		return;
> > > -
> > > -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> > > -				 DISP_TILE_SURFACE_SWIZZLING);
> > > -
> > > -	if (IS_GEN(dev_priv, 5))
> > > -		return;
> > > -
> > > -	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
> > > -	if (IS_GEN(dev_priv, 6))
> > > -		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> > > -	else if (IS_GEN(dev_priv, 7))
> > > -		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> > > -	else if (IS_GEN(dev_priv, 8))
> > > -		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> > > -	else
> > > -		BUG();
> > > -}
> > > -
> > >   static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
> > >   {
> > >   	I915_WRITE(RING_CTL(base), 0);
> > > @@ -1274,7 +1251,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> > >   	/* ...and determine whether they are sticking. */
> > >   	intel_gt_verify_workarounds(dev_priv, "init");
> > > -	i915_gem_init_swizzling(dev_priv);
> > > +	intel_gt_init_swizzling(&dev_priv->gt);
> > >   	/*
> > >   	 * At least 830 can leave some of the unused rings
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> > > index 1c9466676caf..fc268599a0c3 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> > > @@ -834,3 +834,40 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
> > >   	i915_gem_restore_fences(i915);
> > >   }
> > > +
> > > +void intel_gt_init_swizzling(struct intel_gt *gt)
> > > +{
> > > +	struct drm_i915_private *i915 = gt->i915;
> > > +	struct intel_uncore *uncore = gt->uncore;
> > > +
> > > +	if (INTEL_GEN(i915) < 5 ||
> > > +	    i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> > > +		return;
> > > +
> > > +	intel_uncore_write(uncore,
> > > +			   DISP_ARB_CTL,
> > > +			   intel_uncore_read(uncore, DISP_ARB_CTL) |
> > > +			   DISP_TILE_SURFACE_SWIZZLING);
> > 
> > could we change this to intel_uncore_rmw ?
> > 
> > > +
> > > +	if (IS_GEN(i915, 5))
> > > +		return;
> > > +
> > > +	intel_uncore_write(uncore,
> > > +			   TILECTL,
> > > +			   intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL);
> > 
> > and here as well?
> 
> Yes of course.. marking as TODO.

ops, and I forgot to state that with that already add

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> 
> Regards,
> 
> Tvrtko
> 
> > > +
> > > +	if (IS_GEN(i915, 6))
> > > +		intel_uncore_write(uncore,
> > > +				   ARB_MODE,
> > > +				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> > > +	else if (IS_GEN(i915, 7))
> > > +		intel_uncore_write(uncore,
> > > +				   ARB_MODE,
> > > +				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> > > +	else if (IS_GEN(i915, 8))
> > > +		intel_uncore_write(uncore,
> > > +				   GAMTARBMODE,
> > > +				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> > > +	else
> > > +		MISSING_CASE(INTEL_GEN(i915));
> > > +}
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
> > > index d2da98828179..37e4f104f7c0 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
> > > @@ -32,6 +32,7 @@ struct drm_i915_gem_object;
> > >   struct drm_i915_private;
> > >   struct i915_ggtt;
> > >   struct i915_vma;
> > > +struct intel_gt;
> > >   struct sg_table;
> > >   #define I965_FENCE_PAGE 4096UL
> > > @@ -66,4 +67,6 @@ void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
> > >   void i915_ggtt_init_fences(struct i915_ggtt *ggtt);
> > > +void intel_gt_init_swizzling(struct intel_gt *gt);
> > > +
> > >   #endif
> > > -- 
> > > 2.20.1
> > > 
> > 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [RFC 03/31] drm/i915: Move intel_gt initialization to a separate file

[Chris Wilson]

Quoting Chris Wilson (2019-06-14 17:14:08)
> Quoting Chris Wilson (2019-06-14 17:13:03)
> > Quoting Tvrtko Ursulin (2019-06-14 16:17:03)
> > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > 
> > > As it will grow in a following patch make a new home for it.
> > > 
> > > v2:
> > >  * Convert mock_gem_device as well. (Chris)
> > > 
> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/Makefile                    |  1 +
> > >  drivers/gpu/drm/i915/gt/intel_gt.c               | 15 +++++++++++++++
> > >  drivers/gpu/drm/i915/gt/intel_gt.h               | 14 ++++++++++++++
> > >  drivers/gpu/drm/i915/i915_gem.c                  |  6 ++----
> > >  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  5 ++---
> > >  5 files changed, 34 insertions(+), 7 deletions(-)
> > >  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
> > >  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h
> > > 
> > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > > index c0a7b2994077..8df1bf2855d0 100644
> > > --- a/drivers/gpu/drm/i915/Makefile
> > > +++ b/drivers/gpu/drm/i915/Makefile
> > > @@ -73,6 +73,7 @@ gt-y += \
> > >         gt/intel_context.o \
> > >         gt/intel_engine_cs.o \
> > >         gt/intel_engine_pm.o \
> > > +       gt/intel_gt.o \
> > >         gt/intel_gt_pm.o \
> > >         gt/intel_hangcheck.o \
> > >         gt/intel_lrc.o \
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > new file mode 100644
> > > index 000000000000..807c5f746110
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > @@ -0,0 +1,15 @@
> > > +/*
> > > + * SPDX-License-Identifier: MIT
> > > + *
> > > + * Copyright © 2019 Intel Corporation
> > > + */
> > > +
> > > +#include "intel_gt.h"
> > > +
> > > +void intel_gt_init(struct intel_gt *gt)
> > 
> > Please use intel_gt_init_early() to keep the phase known.
> 
> (And yes, I know I violated my own rule, it's easier to spot in review
> :)

Oh, and I would promote it to being called directly by i915_drv.c and
start pulling the HW setup out from under i915_gem.c. I would also like
to push intel_gt_pm_init() into intel_gt_init(), and do want to split
out ips/rps and rc6 out of intel_pm.c into gt/
-Chris
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[RFC 21/31] drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Having introduced struct intel_gt (named the anonymous structure in i915)
we can start using it to compartmentalize our code better. It makes more
sense logically to have the code internally like this and it will also
help with future split between gt and display in i915.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c    |  5 +--
 .../drm/i915/gem/selftests/i915_gem_mman.c    |  3 +-
 drivers/gpu/drm/i915/gt/intel_gt.c            | 41 +++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h            |  2 +
 drivers/gpu/drm/i915/i915_drv.h               |  2 -
 drivers/gpu/drm/i915/i915_gem.c               | 40 ------------------
 drivers/gpu/drm/i915/i915_vma.c               |  3 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  2 +-
 8 files changed, 50 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index a4047a585c8b..341681e602cd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -22,6 +22,7 @@
  *
  */
 
+#include "gt/intel_gt.h"
 #include "i915_drv.h"
 #include "i915_gem_clflush.h"
 #include "i915_gem_context.h"
@@ -367,7 +368,6 @@ void
 i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 				   unsigned int flush_domains)
 {
-	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 	struct i915_vma *vma;
 
 	assert_object_held(obj);
@@ -377,8 +377,6 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 
 	switch (obj->write_domain) {
 	case I915_GEM_DOMAIN_GTT:
-		i915_gem_flush_ggtt_writes(dev_priv);
-
 		intel_fb_obj_flush(obj,
 				   fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
 
@@ -386,6 +384,7 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 			if (vma->iomap)
 				continue;
 
+			intel_gt_flush_ggtt_writes(vma->vm->gt);
 			i915_vma_unset_ggtt_write(vma);
 		}
 		break;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 5c81f4b4813a..2812f7fa27fe 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -6,6 +6,7 @@
 
 #include <linux/prime_numbers.h>
 
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "huge_gem_object.h"
 #include "i915_selftest.h"
@@ -143,7 +144,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj,
 		if (offset >= obj->base.size)
 			continue;
 
-		i915_gem_flush_ggtt_writes(to_i915(obj->base.dev));
+		intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt);
 
 		p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
 		cpu = kmap(p) + offset_in_page(offset);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d5ee3487e180..4d398055f37c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -147,3 +147,44 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 
 	intel_gt_clear_error_registers(gt, ALL_ENGINES);
 }
+
+void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	intel_wakeref_t wakeref;
+
+	/*
+	 * No actual flushing is required for the GTT write domain for reads
+	 * from the GTT domain. Writes to it "immediately" go to main memory
+	 * as far as we know, so there's no chipset flush. It also doesn't
+	 * land in the GPU render cache.
+	 *
+	 * However, we do have to enforce the order so that all writes through
+	 * the GTT land before any writes to the device, such as updates to
+	 * the GATT itself.
+	 *
+	 * We also have to wait a bit for the writes to land from the GTT.
+	 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
+	 * timing. This issue has only been observed when switching quickly
+	 * between GTT writes and CPU reads from inside the kernel on recent hw,
+	 * and it appears to only affect discrete GTT blocks (i.e. on LLC
+	 * system agents we cannot reproduce this behaviour, until Cannonlake
+	 * that was!).
+	 */
+
+	wmb();
+
+	if (INTEL_INFO(i915)->has_coherent_ggtt)
+		return;
+
+	i915_gem_chipset_flush(i915);
+
+	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+		struct intel_uncore *uncore = gt->uncore;
+
+		spin_lock_irq(&uncore->lock);
+		intel_uncore_posting_read_fw(uncore,
+					     RING_HEAD(RENDER_RING_BASE));
+		spin_unlock_irq(&uncore->lock);
+	}
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index d4f585151527..051d7069db55 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -18,4 +18,6 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt);
 void intel_gt_clear_error_registers(struct intel_gt *gt,
 				    intel_engine_mask_t engine_mask);
 
+void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
+
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c4c8ee4133b..d9c02bf42052 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2600,8 +2600,6 @@ int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
 					 unsigned int flags);
 int i915_gem_evict_vm(struct i915_address_space *vm);
 
-void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
-
 /* belongs in i915_gem_gtt.h */
 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5e914ba6724e..dcadffd21339 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -233,46 +233,6 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
 			       &args->size, &args->handle);
 }
 
-void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv)
-{
-	intel_wakeref_t wakeref;
-
-	/*
-	 * No actual flushing is required for the GTT write domain for reads
-	 * from the GTT domain. Writes to it "immediately" go to main memory
-	 * as far as we know, so there's no chipset flush. It also doesn't
-	 * land in the GPU render cache.
-	 *
-	 * However, we do have to enforce the order so that all writes through
-	 * the GTT land before any writes to the device, such as updates to
-	 * the GATT itself.
-	 *
-	 * We also have to wait a bit for the writes to land from the GTT.
-	 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
-	 * timing. This issue has only been observed when switching quickly
-	 * between GTT writes and CPU reads from inside the kernel on recent hw,
-	 * and it appears to only affect discrete GTT blocks (i.e. on LLC
-	 * system agents we cannot reproduce this behaviour, until Cannonlake
-	 * that was!).
-	 */
-
-	wmb();
-
-	if (INTEL_INFO(dev_priv)->has_coherent_ggtt)
-		return;
-
-	i915_gem_chipset_flush(dev_priv);
-
-	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
-		struct intel_uncore *uncore = &dev_priv->uncore;
-
-		spin_lock_irq(&uncore->lock);
-		intel_uncore_posting_read_fw(uncore,
-					     RING_HEAD(RENDER_RING_BASE));
-		spin_unlock_irq(&uncore->lock);
-	}
-}
-
 static int
 shmem_pread(struct page *page, int offset, int len, char __user *user_data,
 	    bool needs_clflush)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index b295c53085ee..571c6ddd7eaf 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -23,6 +23,7 @@
  */
 
 #include "gt/intel_engine.h"
+#include "gt/intel_gt.h"
 
 #include "i915_vma.h"
 
@@ -408,7 +409,7 @@ void i915_vma_flush_writes(struct i915_vma *vma)
 	if (!i915_vma_has_ggtt_write(vma))
 		return;
 
-	i915_gem_flush_ggtt_writes(vma->vm->i915);
+	intel_gt_flush_ggtt_writes(vma->vm->gt);
 
 	i915_vma_unset_ggtt_write(vma);
 }
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 1a60b9fe8221..d9531cb5f235 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1195,7 +1195,7 @@ static int igt_ggtt_page(void *arg)
 		iowrite32(n, vaddr + n);
 		io_mapping_unmap_atomic(vaddr);
 	}
-	i915_gem_flush_ggtt_writes(i915);
+	intel_gt_flush_ggtt_writes(ggtt->vm.gt);
 
 	i915_random_reorder(order, count, &prng);
 	for (n = 0; n < count; n++) {
-- 
2.20.1

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Re: [RFC 20/31] drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:20)
> +void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)

You could have just slipped in a s/dev_priv/i915/...

> +{
> +       ggtt_suspend_mappings(&dev_priv->ggtt);
> +}
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Re: [RFC 06/31] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Tvrtko Ursulin]

On 14/06/2019 17:16, Rodrigo Vivi wrote:
> On Fri, Jun 14, 2019 at 04:36:57PM +0100, Tvrtko Ursulin wrote:
>>
>> On 14/06/2019 16:25, Rodrigo Vivi wrote:
>>> On Fri, Jun 14, 2019 at 04:17:06PM +0100, Tvrtko Ursulin wrote:
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> Start using the newly introduced struct intel_gt to fuse together correct
>>>> logical init flow with uncore for more removal of implicit dev_priv in
>>>> mmio access.
>>>>
>>>> v2:
>>>>    * Move code to i915_gem_fence_reg. (Chris)
>>>>
>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/i915_drv.c           |  4 +--
>>>>    drivers/gpu/drm/i915/i915_drv.h           |  1 -
>>>>    drivers/gpu/drm/i915/i915_gem.c           | 25 +--------------
>>>>    drivers/gpu/drm/i915/i915_gem_fence_reg.c | 37 +++++++++++++++++++++++
>>>>    drivers/gpu/drm/i915/i915_gem_fence_reg.h |  3 ++
>>>>    5 files changed, 43 insertions(+), 27 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>>>> index 97155c5eb7e1..1df76f7c717e 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>>> @@ -2935,7 +2935,7 @@ static int intel_runtime_suspend(struct device *kdev)
>>>>    		intel_uc_resume(dev_priv);
>>>> -		i915_gem_init_swizzling(dev_priv);
>>>> +		intel_gt_init_swizzling(&dev_priv->gt);
>>>>    		i915_gem_restore_fences(dev_priv);
>>>>    		enable_rpm_wakeref_asserts(dev_priv);
>>>> @@ -3036,7 +3036,7 @@ static int intel_runtime_resume(struct device *kdev)
>>>>    	 * No point of rolling back things in case of an error, as the best
>>>>    	 * we can do is to hope that things will still work (and disable RPM).
>>>>    	 */
>>>> -	i915_gem_init_swizzling(dev_priv);
>>>> +	intel_gt_init_swizzling(&dev_priv->gt);
>>>>    	i915_gem_restore_fences(dev_priv);
>>>>    	/*
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>> index e2c8813c9355..1eb203fdee60 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -2586,7 +2586,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
>>>>    void i915_gem_init_mmio(struct drm_i915_private *i915);
>>>>    int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
>>>>    int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
>>>> -void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
>>>>    void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
>>>>    void i915_gem_fini(struct drm_i915_private *dev_priv);
>>>>    int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
>>>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>>>> index 7fdf252f9322..5c0db934315b 100644
>>>> --- a/drivers/gpu/drm/i915/i915_gem.c
>>>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>>>> @@ -1205,29 +1205,6 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
>>>>    	mutex_unlock(&i915->drm.struct_mutex);
>>>>    }
>>>> -void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
>>>> -{
>>>> -	if (INTEL_GEN(dev_priv) < 5 ||
>>>> -	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>>>> -		return;
>>>> -
>>>> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>>>> -				 DISP_TILE_SURFACE_SWIZZLING);
>>>> -
>>>> -	if (IS_GEN(dev_priv, 5))
>>>> -		return;
>>>> -
>>>> -	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
>>>> -	if (IS_GEN(dev_priv, 6))
>>>> -		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>>>> -	else if (IS_GEN(dev_priv, 7))
>>>> -		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
>>>> -	else if (IS_GEN(dev_priv, 8))
>>>> -		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
>>>> -	else
>>>> -		BUG();
>>>> -}
>>>> -
>>>>    static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
>>>>    {
>>>>    	I915_WRITE(RING_CTL(base), 0);
>>>> @@ -1274,7 +1251,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>>>>    	/* ...and determine whether they are sticking. */
>>>>    	intel_gt_verify_workarounds(dev_priv, "init");
>>>> -	i915_gem_init_swizzling(dev_priv);
>>>> +	intel_gt_init_swizzling(&dev_priv->gt);
>>>>    	/*
>>>>    	 * At least 830 can leave some of the unused rings
>>>> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>>> index 1c9466676caf..fc268599a0c3 100644
>>>> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>>> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>>> @@ -834,3 +834,40 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>>>>    	i915_gem_restore_fences(i915);
>>>>    }
>>>> +
>>>> +void intel_gt_init_swizzling(struct intel_gt *gt)
>>>> +{
>>>> +	struct drm_i915_private *i915 = gt->i915;
>>>> +	struct intel_uncore *uncore = gt->uncore;
>>>> +
>>>> +	if (INTEL_GEN(i915) < 5 ||
>>>> +	    i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>>>> +		return;
>>>> +
>>>> +	intel_uncore_write(uncore,
>>>> +			   DISP_ARB_CTL,
>>>> +			   intel_uncore_read(uncore, DISP_ARB_CTL) |
>>>> +			   DISP_TILE_SURFACE_SWIZZLING);
>>>
>>> could we change this to intel_uncore_rmw ?
>>>
>>>> +
>>>> +	if (IS_GEN(i915, 5))
>>>> +		return;
>>>> +
>>>> +	intel_uncore_write(uncore,
>>>> +			   TILECTL,
>>>> +			   intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL);
>>>
>>> and here as well?
>>
>> Yes of course.. marking as TODO.
> 
> ops, and I forgot to state that with that already add
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Thanks! I however planned to consolidate with rmw in a separate patch. 
Just to keep different class of changes separate. Can I keep the r-b for 
this patch as is in this case?

Regards,

Tvrtko
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Re: [RFC 20/31] drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings

[Tvrtko Ursulin]

On 14/06/2019 17:19, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-14 16:17:20)
>> +void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
> 
> You could have just slipped in a s/dev_priv/i915/...

In this instance I apparently forgot, but yes, marking as TODO.

Regards,

Tvrtko

>> +{
>> +       ggtt_suspend_mappings(&dev_priv->ggtt);
>> +}
> 
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Re: [RFC 21/31] drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:21)
> @@ -367,7 +368,6 @@ void
>  i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
>                                    unsigned int flush_domains)
>  {
> -       struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
>         struct i915_vma *vma;
>  
>         assert_object_held(obj);
> @@ -377,8 +377,6 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
>  
>         switch (obj->write_domain) {
>         case I915_GEM_DOMAIN_GTT:
> -               i915_gem_flush_ggtt_writes(dev_priv);
> -
>                 intel_fb_obj_flush(obj,
>                                    fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
>  
> @@ -386,6 +384,7 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
>                         if (vma->iomap)
>                                 continue;
>  
> +                       intel_gt_flush_ggtt_writes(vma->vm->gt);

Hmm. I'd like to have the flush before we tell fbc it can read from
memory, and I'd rather not have the heavy flush on every vma.

I'm probably being overly sensitive, but at the very least I would
reorder this flush to memory before the frontbuffer.
-Chris
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Re: [RFC 22/31] drm/i915: Move i915_gem_chipset_flush to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:22)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 051d7069db55..8d84716c3b3b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -9,8 +9,7 @@
>  
>  #include "gt/intel_engine_types.h"
>  #include "gt/intel_gt_types.h"
> -
> -struct drm_i915_private;
> +#include "i915_drv.h"
>  
>  void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915);
>  
> @@ -20,4 +19,11 @@ void intel_gt_clear_error_registers(struct intel_gt *gt,
>  
>  void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
>  
> +static inline void intel_gt_chipset_flush(struct intel_gt *gt)
> +{
> +       wmb();
> +       if (INTEL_GEN(gt->i915) < 6)
> +               intel_gtt_chipset_flush();
> +}

Grr, in my current mindset I'd take an out-of-line chipset flush over an
include "i915_drv.h"

In the long run, having it out-of-line may be better for detecting if it
is ever a problem (more noticeable).
-Chris
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Re: [RFC 23/31] drm/i915: Compartmentalize timeline_init/park/fini

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:23)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Continuing on the theme of better logical organization of our code, make
> the first step towards making the timeline code better isolated from wider
> struct drm_i915_private.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

You win (with regards to me going around calling everything gt).

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 22/31] drm/i915: Move i915_gem_chipset_flush to intel_gt

[Tvrtko Ursulin]

On 14/06/2019 17:26, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-14 16:17:22)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
>> index 051d7069db55..8d84716c3b3b 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>> @@ -9,8 +9,7 @@
>>   
>>   #include "gt/intel_engine_types.h"
>>   #include "gt/intel_gt_types.h"
>> -
>> -struct drm_i915_private;
>> +#include "i915_drv.h"
>>   
>>   void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915);
>>   
>> @@ -20,4 +19,11 @@ void intel_gt_clear_error_registers(struct intel_gt *gt,
>>   
>>   void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
>>   
>> +static inline void intel_gt_chipset_flush(struct intel_gt *gt)
>> +{
>> +       wmb();
>> +       if (INTEL_GEN(gt->i915) < 6)
>> +               intel_gtt_chipset_flush();
>> +}
> 
> Grr, in my current mindset I'd take an out-of-line chipset flush over an
> include "i915_drv.h"
> 
> In the long run, having it out-of-line may be better for detecting if it
> is ever a problem (more noticeable).

You know that was my first choice but then I saw you replying "A 
function call, for this, you cannot be serious!". :)

So okay, will make it a function call.

Regards,

Tvrtko

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Re: [RFC 24/31] drm/i915: Compartmentalize i915_ggtt_cleanup_hw

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:24)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Continuing on the theme of better logical organization of our code, make
> the first step towards making the ggtt code better isolated from wider
> struct drm_i915_private.
> 
> v2:
>  * Cleanup of mm.wc_stash does not need struct_mutex. (Chris)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

* shakes first at struct_mutex

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 25/31] drm/i915: Compartmentalize i915_gem_init_ggtt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:25)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Continuing on the theme of better logical organization of our code, make
> the first step towards making the ggtt code better isolated from wider
> struct drm_i915_private.
> 
> v2:
>  * Bring the ickle onion unwind back. (Chris)
>  * Rename to i915_init_ggtt. (Chris)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

But not passing gt? Or is that still waiting on moving ggtt and
aliasing_ppgtt?
-Chris
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Re: [RFC 27/31] drm/i915: Compartmentalize ring buffer creation

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:27)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Continuing on the theme of compartmentalizing the code better to make
> future split between gt and display in global i915 clearer.
> 
> v2:
>  * Pass in ggtt instead of gt. (Chris)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Comments about the residual i915->ggtt notwithstanding,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 28/31] drm/i915: Save trip via top-level i915 in a few more places

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:28)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> For gt related operations it makes more logical sense to stay in the realm
> of gt instead of dereferencing via driver i915.

And quite a few of those come under the scope of tracking vm in
intel_context and should simply disappear.

> This patch handles a few of the easy ones with work requiring more
> refactoring still outstanding.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 29/31] drm/i915: Make timelines gt centric

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:29)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Our timelines are stored inside intel_gt so we can convert the interface
> to take exactly that and not i915.
> 
> At the same time re-order the params to our more typical layout and
> replace the backpointer to the new containing structure.

It also makes sense to move to gt/intel_timeline.[ch] then.

> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Preemptive
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
for the move and rename. I think I've gotten over my desire to make
i915_timeline part of sched/
-Chris
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Re: [RFC 30/31] drm/i915: Rename i915_timeline to intel_timeline and move under gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:30)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Move all timeline code under gt and rename to intel_gt prefix.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
You preempted my preempt,
Reviewed-by-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 25/31] drm/i915: Compartmentalize i915_gem_init_ggtt

[Tvrtko Ursulin]

On 14/06/2019 17:32, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-14 16:17:25)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Continuing on the theme of better logical organization of our code, make
>> the first step towards making the ggtt code better isolated from wider
>> struct drm_i915_private.
>>
>> v2:
>>   * Bring the ickle onion unwind back. (Chris)
>>   * Rename to i915_init_ggtt. (Chris)
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> But not passing gt? Or is that still waiting on moving ggtt and
> aliasing_ppgtt?

Yes, init_aliasing_ppgtt stores to i915->mm.aliasing_ppgtt. But at least 
this extracts out init_ggtt which operates on ggtt only.

Regards,

Tvrtko
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Re: [RFC 31/31] drm/i915: Eliminate dual personality of i915_scratch_offset

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:17:31)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index ad1dc58a2374..c80e26c1437d 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1423,9 +1423,9 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
>         goto out_ctx;
>  }
>  
> -static int
> -i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
> +static int gt_init_scratch(struct intel_gt *gt, unsigned int size)
>  {
> +       struct drm_i915_private *i915 = gt->i915;
>         struct drm_i915_gem_object *obj;
>         struct i915_vma *vma;
>         int ret;
> @@ -1438,7 +1438,7 @@ i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
>                 return PTR_ERR(obj);
>         }
>  
> -       vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
> +       vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
>         if (IS_ERR(vma)) {
>                 ret = PTR_ERR(vma);
>                 goto err_unref;
> @@ -1448,7 +1448,7 @@ i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
>         if (ret)
>                 goto err_unref;
>  
> -       i915->gt.scratch = vma;
> +       gt->scratch = vma;
>         return 0;
>  
>  err_unref:
> @@ -1456,9 +1456,20 @@ i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
>         return ret;
>  }
>  
> +static int
> +i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
> +{
> +       return gt_init_scratch(&i915->gt, size);
> +}
> +
> +static void gt_fini_scratch(struct intel_gt *gt)
> +{
> +       i915_vma_unpin_and_release(&gt->scratch, 0);
> +}
> +
>  static void i915_gem_fini_scratch(struct drm_i915_private *i915)
>  {
> -       i915_vma_unpin_and_release(&i915->gt.scratch, 0);
> +       gt_fini_scratch(&i915->gt);
>  }

Apart from this is now decidedly part of intel_gt.
-Chris
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Re: [RFC 31/31] drm/i915: Eliminate dual personality of i915_scratch_offset

[Tvrtko Ursulin]

On 14/06/2019 17:40, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-14 16:17:31)
>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>> index ad1dc58a2374..c80e26c1437d 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.c
>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>> @@ -1423,9 +1423,9 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
>>          goto out_ctx;
>>   }
>>   
>> -static int
>> -i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
>> +static int gt_init_scratch(struct intel_gt *gt, unsigned int size)
>>   {
>> +       struct drm_i915_private *i915 = gt->i915;
>>          struct drm_i915_gem_object *obj;
>>          struct i915_vma *vma;
>>          int ret;
>> @@ -1438,7 +1438,7 @@ i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
>>                  return PTR_ERR(obj);
>>          }
>>   
>> -       vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
>> +       vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
>>          if (IS_ERR(vma)) {
>>                  ret = PTR_ERR(vma);
>>                  goto err_unref;
>> @@ -1448,7 +1448,7 @@ i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
>>          if (ret)
>>                  goto err_unref;
>>   
>> -       i915->gt.scratch = vma;
>> +       gt->scratch = vma;
>>          return 0;
>>   
>>   err_unref:
>> @@ -1456,9 +1456,20 @@ i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
>>          return ret;
>>   }
>>   
>> +static int
>> +i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
>> +{
>> +       return gt_init_scratch(&i915->gt, size);
>> +}
>> +
>> +static void gt_fini_scratch(struct intel_gt *gt)
>> +{
>> +       i915_vma_unpin_and_release(&gt->scratch, 0);
>> +}
>> +
>>   static void i915_gem_fini_scratch(struct drm_i915_private *i915)
>>   {
>> -       i915_vma_unpin_and_release(&i915->gt.scratch, 0);
>> +       gt_fini_scratch(&i915->gt);
>>   }
> 
> Apart from this is now decidedly part of intel_gt.

Was considering to move it, not sure what tipped the scales at the end, 
but yes, can do.

Regards,

Tvrtko
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✗ Fi.CI.BAT: failure for Implicit dev_priv removal and GT compartmentalization (rev7)

[Patchwork]

== Series Details ==

Series: Implicit dev_priv removal and GT compartmentalization (rev7)
URL   : https://patchwork.freedesktop.org/series/62046/
State : failure

== Summary ==

Applying: drm/i915: Convert intel_vgt_(de)balloon to uncore
Applying: drm/i915: Introduce struct intel_gt as replacement for anonymous i915->gt
Applying: drm/i915: Move intel_gt initialization to a separate file
Applying: drm/i915: Store some backpointers in struct intel_gt
Applying: drm/i915: Make i915_check_and_clear_faults take intel_gt
Applying: drm/i915: Convert i915_gem_init_swizzling to intel_gt
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_drv.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0006 drm/i915: Convert i915_gem_init_swizzling to intel_gt
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[RFC 06/31] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Start using the newly introduced struct intel_gt to fuse together correct
logical init flow with uncore for more removal of implicit dev_priv in
mmio access.

v2:
 * Move code to i915_gem_fence_reg. (Chris)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c           |  4 +--
 drivers/gpu/drm/i915/i915_drv.h           |  1 -
 drivers/gpu/drm/i915/i915_gem.c           | 25 +--------------
 drivers/gpu/drm/i915/i915_gem_fence_reg.c | 37 +++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_gem_fence_reg.h |  3 ++
 5 files changed, 43 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 42b52c9f2da6..1fc9623bfa5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2938,7 +2938,7 @@ static int intel_runtime_suspend(struct device *kdev)
 
 		intel_uc_resume(dev_priv);
 
-		i915_gem_init_swizzling(dev_priv);
+		intel_gt_init_swizzling(&dev_priv->gt);
 		i915_gem_restore_fences(dev_priv);
 
 		enable_rpm_wakeref_asserts(rpm);
@@ -3040,7 +3040,7 @@ static int intel_runtime_resume(struct device *kdev)
 	 * No point of rolling back things in case of an error, as the best
 	 * we can do is to hope that things will still work (and disable RPM).
 	 */
-	i915_gem_init_swizzling(dev_priv);
+	intel_gt_init_swizzling(&dev_priv->gt);
 	i915_gem_restore_fences(dev_priv);
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 714963d7b3fe..2c4c8ee4133b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2538,7 +2538,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
 void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
 void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
 void i915_gem_fini(struct drm_i915_private *dev_priv);
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 721277a2ec35..642ab97ced62 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1206,29 +1206,6 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 	mutex_unlock(&i915->drm.struct_mutex);
 }
 
-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
-{
-	if (INTEL_GEN(dev_priv) < 5 ||
-	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
-		return;
-
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
-				 DISP_TILE_SURFACE_SWIZZLING);
-
-	if (IS_GEN(dev_priv, 5))
-		return;
-
-	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
-	if (IS_GEN(dev_priv, 6))
-		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
-	else if (IS_GEN(dev_priv, 7))
-		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
-	else if (IS_GEN(dev_priv, 8))
-		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
-	else
-		BUG();
-}
-
 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
 {
 	I915_WRITE(RING_CTL(base), 0);
@@ -1275,7 +1252,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	/* ...and determine whether they are sticking. */
 	intel_gt_verify_workarounds(dev_priv, "init");
 
-	i915_gem_init_swizzling(dev_priv);
+	intel_gt_init_swizzling(&dev_priv->gt);
 
 	/*
 	 * At least 830 can leave some of the unused rings
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 0bf53ac1c835..dd09790c420d 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -834,3 +834,40 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
 
 	i915_gem_restore_fences(i915);
 }
+
+void intel_gt_init_swizzling(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
+
+	if (INTEL_GEN(i915) < 5 ||
+	    i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+		return;
+
+	intel_uncore_write(uncore,
+			   DISP_ARB_CTL,
+			   intel_uncore_read(uncore, DISP_ARB_CTL) |
+			   DISP_TILE_SURFACE_SWIZZLING);
+
+	if (IS_GEN(i915, 5))
+		return;
+
+	intel_uncore_write(uncore,
+			   TILECTL,
+			   intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL);
+
+	if (IS_GEN(i915, 6))
+		intel_uncore_write(uncore,
+				   ARB_MODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
+	else if (IS_GEN(i915, 7))
+		intel_uncore_write(uncore,
+				   ARB_MODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
+	else if (IS_GEN(i915, 8))
+		intel_uncore_write(uncore,
+				   GAMTARBMODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
+	else
+		MISSING_CASE(INTEL_GEN(i915));
+}
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
index d2da98828179..37e4f104f7c0 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.h
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
@@ -32,6 +32,7 @@ struct drm_i915_gem_object;
 struct drm_i915_private;
 struct i915_ggtt;
 struct i915_vma;
+struct intel_gt;
 struct sg_table;
 
 #define I965_FENCE_PAGE 4096UL
@@ -66,4 +67,6 @@ void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
 
 void i915_ggtt_init_fences(struct i915_ggtt *ggtt);
 
+void intel_gt_init_swizzling(struct intel_gt *gt);
+
 #endif
-- 
2.20.1

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Re: [RFC 01/31] drm/i915: Convert intel_vgt_(de)balloon to uncore

[Michal Wajdeczko]

On Fri, 14 Jun 2019 17:17:01 +0200, Tvrtko Ursulin  
<tvrtko.ursulin@linux.intel.com> wrote:

> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> More removal of implicit dev_priv from using old mmio accessors.
>
> Furthermore these calls really operate on ggtt so it logically makes  
> sense
> if they take it as parameter.

Hmm, I'm not sure that we going in right direction here, as these
functions mostly operate on bl_info that today is separate to ggtt.

Maybe better option would be to move pure ggtt related functions
vgt_balloon_space/vgt_deballoon_space to i915_gem_ggtt.c|h (after
rename) and allow vgpu functions to keep i915 as parameter ?

Michal

>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c |  4 ++--
>  drivers/gpu/drm/i915/i915_vgpu.c    | 24 ++++++++++++++----------
>  drivers/gpu/drm/i915/i915_vgpu.h    |  4 ++--
>  3 files changed, 18 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c  
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7be72388b052..90d9669ff313 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2859,7 +2859,7 @@ int i915_gem_init_ggtt(struct drm_i915_private  
> *dev_priv)
>  	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
>  			       intel_wopcm_guc_size(&dev_priv->wopcm));
> -	ret = intel_vgt_balloon(dev_priv);
> +	ret = intel_vgt_balloon(ggtt);
>  	if (ret)
>  		return ret;
> @@ -2930,7 +2930,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private  
> *dev_priv)
>  	ggtt_release_guc_top(ggtt);
> 	if (drm_mm_initialized(&ggtt->vm.mm)) {
> -		intel_vgt_deballoon(dev_priv);
> +		intel_vgt_deballoon(ggtt);
>  		i915_address_space_fini(&ggtt->vm);
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c  
> b/drivers/gpu/drm/i915/i915_vgpu.c
> index 94d3992b599d..41ed9a3f52b4 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -117,17 +117,17 @@ static void vgt_deballoon_space(struct i915_ggtt  
> *ggtt,
>   * This function is called to deallocate the ballooned-out graphic  
> memory, when
>   * driver is unloaded or when ballooning fails.
>   */
> -void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
> +void intel_vgt_deballoon(struct i915_ggtt *ggtt)
>  {
>  	int i;
> -	if (!intel_vgpu_active(dev_priv))
> +	if (!intel_vgpu_active(ggtt->vm.i915))
>  		return;
> 	DRM_DEBUG("VGT deballoon.\n");
> 	for (i = 0; i < 4; i++)
> -		vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
> +		vgt_deballoon_space(ggtt, &bl_info.space[i]);
>  }
> static int vgt_balloon_space(struct i915_ggtt *ggtt,
> @@ -195,22 +195,26 @@ static int vgt_balloon_space(struct i915_ggtt  
> *ggtt,
>   * Returns:
>   * zero on success, non-zero if configuration invalid or ballooning  
> failed
>   */
> -int intel_vgt_balloon(struct drm_i915_private *dev_priv)
> +int intel_vgt_balloon(struct i915_ggtt *ggtt)
>  {
> -	struct i915_ggtt *ggtt = &dev_priv->ggtt;
> +	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
>  	unsigned long ggtt_end = ggtt->vm.total;
> 	unsigned long mappable_base, mappable_size, mappable_end;
>  	unsigned long unmappable_base, unmappable_size, unmappable_end;
>  	int ret;
> -	if (!intel_vgpu_active(dev_priv))
> +	if (!intel_vgpu_active(ggtt->vm.i915))
>  		return 0;
> -	mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
> -	mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
> -	unmappable_base =  
> I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
> -	unmappable_size =  
> I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
> +	mappable_base =
> +	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
> +	mappable_size =
> +	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
> +	unmappable_base =
> +	  intel_uncore_read(uncore,  
> vgtif_reg(avail_rs.nonmappable_gmadr.base));
> +	unmappable_size =
> +	  intel_uncore_read(uncore,  
> vgtif_reg(avail_rs.nonmappable_gmadr.size));
> 	mappable_end = mappable_base + mappable_size;
>  	unmappable_end = unmappable_base + unmappable_size;
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h  
> b/drivers/gpu/drm/i915/i915_vgpu.h
> index ebe1b7bced98..e918f418503f 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -42,7 +42,7 @@ intel_vgpu_has_huge_gtt(struct drm_i915_private  
> *dev_priv)
>  	return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
>  }
> -int intel_vgt_balloon(struct drm_i915_private *dev_priv);
> -void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
> +int intel_vgt_balloon(struct i915_ggtt *ggtt);
> +void intel_vgt_deballoon(struct i915_ggtt *ggtt);
> #endif /* _I915_VGPU_H_ */
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Re: [RFC 06/31] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 05:21:39PM +0100, Tvrtko Ursulin wrote:
> 
> On 14/06/2019 17:16, Rodrigo Vivi wrote:
> > On Fri, Jun 14, 2019 at 04:36:57PM +0100, Tvrtko Ursulin wrote:
> > > 
> > > On 14/06/2019 16:25, Rodrigo Vivi wrote:
> > > > On Fri, Jun 14, 2019 at 04:17:06PM +0100, Tvrtko Ursulin wrote:
> > > > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > 
> > > > > Start using the newly introduced struct intel_gt to fuse together correct
> > > > > logical init flow with uncore for more removal of implicit dev_priv in
> > > > > mmio access.
> > > > > 
> > > > > v2:
> > > > >    * Move code to i915_gem_fence_reg. (Chris)
> > > > > 
> > > > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > ---
> > > > >    drivers/gpu/drm/i915/i915_drv.c           |  4 +--
> > > > >    drivers/gpu/drm/i915/i915_drv.h           |  1 -
> > > > >    drivers/gpu/drm/i915/i915_gem.c           | 25 +--------------
> > > > >    drivers/gpu/drm/i915/i915_gem_fence_reg.c | 37 +++++++++++++++++++++++
> > > > >    drivers/gpu/drm/i915/i915_gem_fence_reg.h |  3 ++
> > > > >    5 files changed, 43 insertions(+), 27 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > > > index 97155c5eb7e1..1df76f7c717e 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > > @@ -2935,7 +2935,7 @@ static int intel_runtime_suspend(struct device *kdev)
> > > > >    		intel_uc_resume(dev_priv);
> > > > > -		i915_gem_init_swizzling(dev_priv);
> > > > > +		intel_gt_init_swizzling(&dev_priv->gt);
> > > > >    		i915_gem_restore_fences(dev_priv);
> > > > >    		enable_rpm_wakeref_asserts(dev_priv);
> > > > > @@ -3036,7 +3036,7 @@ static int intel_runtime_resume(struct device *kdev)
> > > > >    	 * No point of rolling back things in case of an error, as the best
> > > > >    	 * we can do is to hope that things will still work (and disable RPM).
> > > > >    	 */
> > > > > -	i915_gem_init_swizzling(dev_priv);
> > > > > +	intel_gt_init_swizzling(&dev_priv->gt);
> > > > >    	i915_gem_restore_fences(dev_priv);
> > > > >    	/*
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > > index e2c8813c9355..1eb203fdee60 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > @@ -2586,7 +2586,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
> > > > >    void i915_gem_init_mmio(struct drm_i915_private *i915);
> > > > >    int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
> > > > >    int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
> > > > > -void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
> > > > >    void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
> > > > >    void i915_gem_fini(struct drm_i915_private *dev_priv);
> > > > >    int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
> > > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > > > > index 7fdf252f9322..5c0db934315b 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > > > @@ -1205,29 +1205,6 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
> > > > >    	mutex_unlock(&i915->drm.struct_mutex);
> > > > >    }
> > > > > -void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
> > > > > -{
> > > > > -	if (INTEL_GEN(dev_priv) < 5 ||
> > > > > -	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> > > > > -		return;
> > > > > -
> > > > > -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> > > > > -				 DISP_TILE_SURFACE_SWIZZLING);
> > > > > -
> > > > > -	if (IS_GEN(dev_priv, 5))
> > > > > -		return;
> > > > > -
> > > > > -	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
> > > > > -	if (IS_GEN(dev_priv, 6))
> > > > > -		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> > > > > -	else if (IS_GEN(dev_priv, 7))
> > > > > -		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> > > > > -	else if (IS_GEN(dev_priv, 8))
> > > > > -		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> > > > > -	else
> > > > > -		BUG();
> > > > > -}
> > > > > -
> > > > >    static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
> > > > >    {
> > > > >    	I915_WRITE(RING_CTL(base), 0);
> > > > > @@ -1274,7 +1251,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> > > > >    	/* ...and determine whether they are sticking. */
> > > > >    	intel_gt_verify_workarounds(dev_priv, "init");
> > > > > -	i915_gem_init_swizzling(dev_priv);
> > > > > +	intel_gt_init_swizzling(&dev_priv->gt);
> > > > >    	/*
> > > > >    	 * At least 830 can leave some of the unused rings
> > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> > > > > index 1c9466676caf..fc268599a0c3 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> > > > > @@ -834,3 +834,40 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
> > > > >    	i915_gem_restore_fences(i915);
> > > > >    }
> > > > > +
> > > > > +void intel_gt_init_swizzling(struct intel_gt *gt)
> > > > > +{
> > > > > +	struct drm_i915_private *i915 = gt->i915;
> > > > > +	struct intel_uncore *uncore = gt->uncore;
> > > > > +
> > > > > +	if (INTEL_GEN(i915) < 5 ||
> > > > > +	    i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> > > > > +		return;
> > > > > +
> > > > > +	intel_uncore_write(uncore,
> > > > > +			   DISP_ARB_CTL,
> > > > > +			   intel_uncore_read(uncore, DISP_ARB_CTL) |
> > > > > +			   DISP_TILE_SURFACE_SWIZZLING);
> > > > 
> > > > could we change this to intel_uncore_rmw ?
> > > > 
> > > > > +
> > > > > +	if (IS_GEN(i915, 5))
> > > > > +		return;
> > > > > +
> > > > > +	intel_uncore_write(uncore,
> > > > > +			   TILECTL,
> > > > > +			   intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL);
> > > > 
> > > > and here as well?
> > > 
> > > Yes of course.. marking as TODO.
> > 
> > ops, and I forgot to state that with that already add
> > 
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> Thanks! I however planned to consolidate with rmw in a separate patch. Just
> to keep different class of changes separate. Can I keep the r-b for this
> patch as is in this case?

oh, sure! whatever is easier

> 
> Regards,
> 
> Tvrtko
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Re: [RFC 19/31] drm/i915: Store intel_gt backpointer in vm

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 04:17:19PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> This will come useful in the following patch.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

an individual commit message would be better, but let's focus
on the content:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 16 ++++++++++------
>  drivers/gpu/drm/i915/i915_gem_gtt.h |  1 +
>  2 files changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 95af45156cc2..0bc75c963955 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1587,9 +1587,11 @@ static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
>  	return -ENOMEM;
>  }
>  
> -static void ppgtt_init(struct drm_i915_private *i915,
> -		       struct i915_ppgtt *ppgtt)
> +static void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
>  {
> +	struct drm_i915_private *i915 = gt->i915;
> +
> +	ppgtt->vm.gt = gt;
>  	ppgtt->vm.i915 = i915;
>  	ppgtt->vm.dma = &i915->drm.pdev->dev;
>  	ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
> @@ -1618,7 +1620,7 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>  	if (!ppgtt)
>  		return ERR_PTR(-ENOMEM);
>  
> -	ppgtt_init(i915, ppgtt);
> +	ppgtt_init(ppgtt, &i915->gt);
>  
>  	/*
>  	 * From bdw, there is hw support for read-only pages in the PPGTT.
> @@ -2155,7 +2157,7 @@ static struct i915_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
>  	if (!ppgtt)
>  		return ERR_PTR(-ENOMEM);
>  
> -	ppgtt_init(i915, &ppgtt->base);
> +	ppgtt_init(&ppgtt->base, &i915->gt);
>  
>  	ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
>  	ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
> @@ -3502,10 +3504,12 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
>  	return 0;
>  }
>  
> -static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct drm_i915_private *i915)
> +static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
>  {
> +	struct drm_i915_private *i915 = gt->i915;
>  	int ret;
>  
> +	ggtt->vm.gt = gt;
>  	ggtt->vm.i915 = i915;
>  	ggtt->vm.dma = &i915->drm.pdev->dev;
>  
> @@ -3551,7 +3555,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
>  {
>  	int ret;
>  
> -	ret = ggtt_probe_hw(&i915->ggtt, i915);
> +	ret = ggtt_probe_hw(&i915->ggtt, &i915->gt);
>  	if (ret)
>  		return ret;
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index b541190db6e8..9a3d96370f07 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -297,6 +297,7 @@ struct i915_address_space {
>  	struct kref ref;
>  
>  	struct drm_mm mm;
> +	struct intel_gt *gt;
>  	struct drm_i915_private *i915;
>  	struct device *dma;
>  	/* Every address space belongs to a struct file - except for the global
> -- 
> 2.20.1
> 
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✗ Fi.CI.BAT: failure for Implicit dev_priv removal and GT compartmentalization (rev8)

[Patchwork]

== Series Details ==

Series: Implicit dev_priv removal and GT compartmentalization (rev8)
URL   : https://patchwork.freedesktop.org/series/62046/
State : failure

== Summary ==

Applying: drm/i915: Convert intel_vgt_(de)balloon to uncore
Applying: drm/i915: Introduce struct intel_gt as replacement for anonymous i915->gt
Applying: drm/i915: Move intel_gt initialization to a separate file
Applying: drm/i915: Store some backpointers in struct intel_gt
Applying: drm/i915: Make i915_check_and_clear_faults take intel_gt
Applying: drm/i915: Convert i915_gem_init_swizzling to intel_gt
Applying: drm/i915: Convert init_unused_rings to intel_gt
Applying: drm/i915: Convert gt workarounds to intel_gt
Applying: drm/i915: Store backpointer to intel_gt in the engine
Applying: drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt
Applying: drm/i915: Convert i915_ppgtt_init_hw to intel_gt
Applying: drm/i915: Consolidate some open coded mmio rmw
Applying: drm/i915: Convert i915_gem_init_hw to intel_gt
Applying: drm/i915: Move intel_engines_resume into common init
Applying: drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw
Applying: drm/i915: Compartmentalize i915_ggtt_probe_hw
Applying: drm/i915: Compartmentalize i915_ggtt_init_hw
Applying: drm/i915: Make ggtt invalidation work on ggtt
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_gem_gtt.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0018 drm/i915: Make ggtt invalidation work on ggtt
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [RFC 26/31] drm/i915: Store ggtt pointer in intel_gt

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 04:17:26PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> This will become useful in the following patch.
> 
> v2:
>  * Assign the pointer through a helper on the top level to work around
>    the layering violation. (Chris)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c       | 5 +++++
>  drivers/gpu/drm/i915/gt/intel_gt.h       | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 ++
>  drivers/gpu/drm/i915/i915_drv.c          | 2 ++
>  4 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 5bc460d68c8b..6746c40c2132 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -20,6 +20,11 @@ void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915)
>  	spin_lock_init(&gt->closed_lock);
>  }
>  
> +void intel_gt_init_hw(struct drm_i915_private *i915)
> +{
> +	i915->gt.ggtt = &i915->ggtt;
> +}
> +
>  static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
>  {
>  	intel_uncore_rmw(uncore, reg, 0, set);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 8d84716c3b3b..53fcf4f276d3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -12,6 +12,7 @@
>  #include "i915_drv.h"
>  
>  void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915);
> +void intel_gt_init_hw(struct drm_i915_private *i915);
>  
>  void intel_gt_check_and_clear_faults(struct intel_gt *gt);
>  void intel_gt_clear_error_registers(struct intel_gt *gt,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index d96df4f68741..233f73316a43 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -18,11 +18,13 @@
>  #include "intel_wakeref.h"
>  
>  struct drm_i915_private;
> +struct i915_ggtt;
>  struct intel_uncore;
>  
>  struct intel_gt {
>  	struct drm_i915_private *i915;
>  	struct intel_uncore *uncore;
> +	struct i915_ggtt *ggtt;
>  
>  	struct i915_gt_timelines {
>  		struct mutex mutex; /* protects list, tainted by GPU */
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1df76f7c717e..783cbbda75fb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1584,6 +1584,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>  	if (ret)
>  		goto err_ggtt;
>  
> +	intel_gt_init_hw(dev_priv);
> +
>  	ret = i915_ggtt_enable_hw(dev_priv);
>  	if (ret) {
>  		DRM_ERROR("failed to enable GGTT\n");
> -- 
> 2.20.1
> 
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Re: [RFC 01/31] drm/i915: Convert intel_vgt_(de)balloon to uncore

[Chris Wilson]

Quoting Michal Wajdeczko (2019-06-14 18:18:54)
> On Fri, 14 Jun 2019 17:17:01 +0200, Tvrtko Ursulin  
> <tvrtko.ursulin@linux.intel.com> wrote:
> 
> > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >
> > More removal of implicit dev_priv from using old mmio accessors.
> >
> > Furthermore these calls really operate on ggtt so it logically makes  
> > sense
> > if they take it as parameter.
> 
> Hmm, I'm not sure that we going in right direction here, as these
> functions mostly operate on bl_info that today is separate to ggtt.

That was my first thought too, except they are operating inside of ggtt
init/fini.

> Maybe better option would be to move pure ggtt related functions
> vgt_balloon_space/vgt_deballoon_space to i915_gem_ggtt.c|h (after
> rename) and allow vgpu functions to keep i915 as parameter ?

Presumably, vgpu would migrate to taking its own object as well. Still
undecided how best to handle ggtt init plugins. My ideal would be that
vgpu init was dynamic and be tuned to work with an existing ggtt, and
never rely on static partitioning.
-Chris
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Re: [RFC 20/31] drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings

[Rodrigo Vivi]

On Fri, Jun 14, 2019 at 04:17:20PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Having made start to better code compartmentalization by introducing
> struct intel_gt, continue the theme elsewhere in code by making functions
> take parameters take what logically makes most sense for them instead of
> the global struct drm_i915_private.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 23 ++++++++++++++++-------
>  1 file changed, 16 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0bc75c963955..516ffc4a521a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2323,23 +2323,28 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
>  	return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
>  }
>  
> -void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
> +static void ggtt_suspend_mappings(struct i915_ggtt *ggtt)
>  {
> -	struct i915_ggtt *ggtt = &dev_priv->ggtt;
> +	struct drm_i915_private *i915 = ggtt->vm.i915;
>  
>  	/* Don't bother messing with faults pre GEN6 as we have little
>  	 * documentation supporting that it's a good idea.
>  	 */
> -	if (INTEL_GEN(dev_priv) < 6)
> +	if (INTEL_GEN(i915) < 6)
>  		return;
>  
> -	intel_gt_check_and_clear_faults(&dev_priv->gt);
> +	intel_gt_check_and_clear_faults(ggtt->vm.gt);
>  
>  	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
>  
>  	ggtt->invalidate(ggtt);
>  }
>  
> +void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
> +{
> +	ggtt_suspend_mappings(&dev_priv->ggtt);
> +}
> +
>  int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
>  			       struct sg_table *pages)
>  {
> @@ -3674,12 +3679,11 @@ void i915_ggtt_disable_guc(struct drm_i915_private *i915)
>  	ggtt->invalidate(ggtt);
>  }
>  
> -void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
> +static void ggtt_restore_mappings(struct i915_ggtt *ggtt)
>  {
> -	struct i915_ggtt *ggtt = &dev_priv->ggtt;
>  	struct i915_vma *vma, *vn;
>  
> -	intel_gt_check_and_clear_faults(&dev_priv->gt);
> +	intel_gt_check_and_clear_faults(ggtt->vm.gt);
>  
>  	mutex_lock(&ggtt->vm.mutex);
>  
> @@ -3716,6 +3720,11 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
>  	ggtt->invalidate(ggtt);
>  
>  	mutex_unlock(&ggtt->vm.mutex);
> +}
> +
> +void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)

I'd say maybe more places to s/dev_priv/i915, but I'm actually in favor
of the big sed so:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> +{
> +	ggtt_restore_mappings(&dev_priv->ggtt);
>  
>  	if (INTEL_GEN(dev_priv) >= 8) {
>  		struct intel_ppat *ppat = &dev_priv->ppat;
> -- 
> 2.20.1
> 
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Re: [RFC 01/31] drm/i915: Convert intel_vgt_(de)balloon to uncore

[Tvrtko Ursulin]

On 14/06/2019 18:43, Chris Wilson wrote:
> Quoting Michal Wajdeczko (2019-06-14 18:18:54)
>> On Fri, 14 Jun 2019 17:17:01 +0200, Tvrtko Ursulin
>> <tvrtko.ursulin@linux.intel.com> wrote:
>>
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> More removal of implicit dev_priv from using old mmio accessors.
>>>
>>> Furthermore these calls really operate on ggtt so it logically makes
>>> sense
>>> if they take it as parameter.
>>
>> Hmm, I'm not sure that we going in right direction here, as these
>> functions mostly operate on bl_info that today is separate to ggtt.
> 
> That was my first thought too, except they are operating inside of ggtt
> init/fini.

And it does actually modify ggtt: intel_vgt_balloon -> vgt_balloon_space 
-> i915_gem_gtt_reserve.

So to me it sounded passable to make them take ggtt as input parameter. 
It is not detrimental if they (the functions) one day decide to wrap 
both bl_info and ggtt into a new object.

Sounds passable or objection is hard?

Regards,

Tvrtko

>> Maybe better option would be to move pure ggtt related functions
>> vgt_balloon_space/vgt_deballoon_space to i915_gem_ggtt.c|h (after
>> rename) and allow vgpu functions to keep i915 as parameter ?
> 
> Presumably, vgpu would migrate to taking its own object as well. Still
> undecided how best to handle ggtt init plugins. My ideal would be that
> vgpu init was dynamic and be tuned to work with an existing ggtt, and
> never rely on static partitioning.
> -Chris
> 
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