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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
Date: Tue,  8 Oct 2019 19:14:35 +0300	[thread overview]
Message-ID: <20191008161441.12721-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20191008161441.12721-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
On VLV and CHV pipe A/C these are only supported by the the primary
plane. Add the require bits to expose the new formats.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h             | 14 +++++----
 2 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 90b0e65420a5..fb36da58390a 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -861,6 +861,12 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_ABGR2101010:
 		sprctl |= SP_FORMAT_RGBA1010102;
 		break;
+	case DRM_FORMAT_XRGB2101010:
+		sprctl |= SP_FORMAT_BGRX1010102;
+		break;
+	case DRM_FORMAT_ARGB2101010:
+		sprctl |= SP_FORMAT_BGRA1010102;
+		break;
 	case DRM_FORMAT_XBGR8888:
 		sprctl |= SP_FORMAT_RGBX8888;
 		break;
@@ -2017,6 +2023,22 @@ static const u32 vlv_plane_formats[] = {
 	DRM_FORMAT_VYUY,
 };
 
+static const u32 chv_pipe_b_sprite_formats[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_ABGR2101010,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_ARGB2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+};
+
 static const u32 skl_plane_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
@@ -2241,6 +2263,8 @@ static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_ABGR2101010:
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_ARGB2101010:
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
@@ -2637,8 +2661,13 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 		plane->get_hw_state = vlv_plane_get_hw_state;
 		plane->check_plane = vlv_sprite_check;
 
-		formats = vlv_plane_formats;
-		num_formats = ARRAY_SIZE(vlv_plane_formats);
+		if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
+			formats = chv_pipe_b_sprite_formats;
+			num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
+		} else {
+			formats = vlv_plane_formats;
+			num_formats = ARRAY_SIZE(vlv_plane_formats);
+		}
 		modifiers = i9xx_plane_format_modifiers;
 
 		plane_funcs = &vlv_sprite_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd75eff1266..74bb5a6cbe4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6545,12 +6545,14 @@ enum {
 #define   SP_ENABLE			(1 << 31)
 #define   SP_GAMMA_ENABLE		(1 << 30)
 #define   SP_PIXFORMAT_MASK		(0xf << 26)
-#define   SP_FORMAT_YUV422		(0 << 26)
-#define   SP_FORMAT_BGR565		(5 << 26)
-#define   SP_FORMAT_BGRX8888		(6 << 26)
-#define   SP_FORMAT_BGRA8888		(7 << 26)
-#define   SP_FORMAT_RGBX1010102		(8 << 26)
-#define   SP_FORMAT_RGBA1010102		(9 << 26)
+#define   SP_FORMAT_YUV422		(0x0 << 26)
+#define   SP_FORMAT_BGR565		(0x5 << 26)
+#define   SP_FORMAT_BGRX8888		(0x6 << 26)
+#define   SP_FORMAT_BGRA8888		(0x7 << 26)
+#define   SP_FORMAT_RGBX1010102		(0x8 << 26)
+#define   SP_FORMAT_RGBA1010102		(0x9 << 26)
+#define   SP_FORMAT_BGRX1010102		(0xa << 26) /* CHV pipe B */
+#define   SP_FORMAT_BGRA1010102		(0xb << 26) /* CHV pipe B */
 #define   SP_FORMAT_RGBX8888		(0xe << 26)
 #define   SP_FORMAT_RGBA8888		(0xf << 26)
 #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */
-- 
2.21.0

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  parent reply	other threads:[~2019-10-08 16:14 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
2019-10-08 16:14 ` [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes Ville Syrjala
2019-10-29 10:01   ` Shankar, Uma
2019-10-29 10:01     ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` Ville Syrjala [this message]
2019-10-29 11:53   ` [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV Shankar, Uma
2019-10-29 11:53     ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes Ville Syrjala
2019-10-29 10:29   ` Shankar, Uma
2019-10-29 10:29     ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 5/9] drm/i915: Add 10bpc formats with alpha for icl+ Ville Syrjala
2019-10-09 10:43   ` [PATCH v2 " Ville Syrjala
2019-10-29 12:08     ` Shankar, Uma
2019-10-29 12:08       ` [Intel-gfx] " Shankar, Uma
2019-10-29 20:07   ` [PATCH " Juha-Pekka Heikkila
2019-10-29 20:07     ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-08 16:14 ` [PATCH 6/9] drm/i915: Sort format arrays consistently Ville Syrjala
2019-10-27 20:53   ` Juha-Pekka Heikkila
2019-10-27 20:53     ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-29 12:10   ` Shankar, Uma
2019-10-29 12:10     ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+ Ville Syrjala
2019-10-29 13:07   ` Shankar, Uma
2019-10-29 13:07     ` [Intel-gfx] " Shankar, Uma
2019-10-29 13:35     ` Shankar, Uma
2019-10-29 13:35       ` [Intel-gfx] " Shankar, Uma
2019-10-29 15:22       ` Ville Syrjälä
2019-10-29 15:22         ` [Intel-gfx] " Ville Syrjälä
2019-10-30 15:26         ` Shankar, Uma
2019-10-30 15:26           ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active Ville Syrjala
2019-10-29 13:22   ` Shankar, Uma
2019-10-29 13:22     ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create() Ville Syrjala
2019-10-27 20:53   ` Juha-Pekka Heikkila
2019-10-27 20:53     ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-29 13:24   ` Shankar, Uma
2019-10-29 13:24     ` [Intel-gfx] " Shankar, Uma
2019-10-08 18:24 ` ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Patchwork
2019-10-09  0:55 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-10-09 15:45 ` ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2) Patchwork
2019-10-09 21:12 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-10-14 19:23   ` Ville Syrjälä
2019-10-14 20:23     ` Chris Wilson
2019-10-15  6:41     ` Arkadiusz Hiler
2019-10-15  9:25       ` Petri Latvala
2019-10-15 11:51         ` Ville Syrjälä
2019-10-15 12:08         ` Arkadiusz Hiler
2019-10-29  9:08 ` [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Shankar, Uma
2019-10-29  9:08   ` [Intel-gfx] " Shankar, Uma
2019-10-29 20:15 ` Juha-Pekka Heikkila
2019-10-29 20:15   ` [Intel-gfx] " Juha-Pekka Heikkila

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