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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active
Date: Tue,  8 Oct 2019 19:14:40 +0300	[thread overview]
Message-ID: <20191008161441.12721-8-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20191008161441.12721-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The spec says that color keying and HDR mode are mutually exclusive.
So let's not enable HDR mode when color keying is active.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c  |  5 +++++
 drivers/gpu/drm/i915/display/intel_display.c       | 13 ++++++++++---
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 98b7766eaa7a..f64204f6f37f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -150,6 +150,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	new_crtc_state->active_planes &= ~BIT(plane->id);
 	new_crtc_state->nv12_planes &= ~BIT(plane->id);
 	new_crtc_state->c8_planes &= ~BIT(plane->id);
+	new_crtc_state->ckey_planes &= ~BIT(plane->id);
 	new_crtc_state->data_rate[plane->id] = 0;
 	new_plane_state->base.visible = false;
 
@@ -172,6 +173,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	    fb->format->format == DRM_FORMAT_C8)
 		new_crtc_state->c8_planes |= BIT(plane->id);
 
+	if (new_plane_state->base.visible &&
+	    new_plane_state->ckey.flags)
+		new_crtc_state->ckey_planes |= BIT(plane->id);
+
 	if (new_plane_state->base.visible || old_plane_state->base.visible)
 		new_crtc_state->update_planes |= BIT(plane->id);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a8124f01bdb2..c553a3417891 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9514,6 +9514,15 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	POSTING_READ(PIPECONF(cpu_transcoder));
 }
 
+static bool icl_can_hdr_mode(const struct intel_crtc_state *crtc_state)
+{
+	u8 ckey_planes = crtc_state->ckey_planes;
+	u8 sdr_planes = crtc_state->active_planes &
+		~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR));
+
+	return !ckey_planes && !sdr_planes;
+}
+
 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -9549,9 +9558,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
 		val |= PIPEMISC_YUV420_ENABLE |
 			PIPEMISC_YUV420_MODE_FULL_BLEND;
 
-	if (INTEL_GEN(dev_priv) >= 11 &&
-	    (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
-					   BIT(PLANE_CURSOR))) == 0)
+	if (INTEL_GEN(dev_priv) >= 11 && icl_can_hdr_mode(crtc_state))
 		val |= PIPEMISC_HDR_MODE_PRECISION;
 
 	I915_WRITE(PIPEMISC(crtc->pipe), val);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40390d855815..4935ea41d3e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -949,6 +949,7 @@ struct intel_crtc_state {
 	u8 active_planes;
 	u8 nv12_planes;
 	u8 c8_planes;
+	u8 ckey_planes;
 
 	/* bitmask of planes that will be updated during the commit */
 	u8 update_planes;
-- 
2.21.0

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  parent reply	other threads:[~2019-10-08 16:15 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
2019-10-08 16:14 ` [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes Ville Syrjala
2019-10-29 10:01   ` Shankar, Uma
2019-10-29 10:01     ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV Ville Syrjala
2019-10-29 11:53   ` Shankar, Uma
2019-10-29 11:53     ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes Ville Syrjala
2019-10-29 10:29   ` Shankar, Uma
2019-10-29 10:29     ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 5/9] drm/i915: Add 10bpc formats with alpha for icl+ Ville Syrjala
2019-10-09 10:43   ` [PATCH v2 " Ville Syrjala
2019-10-29 12:08     ` Shankar, Uma
2019-10-29 12:08       ` [Intel-gfx] " Shankar, Uma
2019-10-29 20:07   ` [PATCH " Juha-Pekka Heikkila
2019-10-29 20:07     ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-08 16:14 ` [PATCH 6/9] drm/i915: Sort format arrays consistently Ville Syrjala
2019-10-27 20:53   ` Juha-Pekka Heikkila
2019-10-27 20:53     ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-29 12:10   ` Shankar, Uma
2019-10-29 12:10     ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+ Ville Syrjala
2019-10-29 13:07   ` Shankar, Uma
2019-10-29 13:07     ` [Intel-gfx] " Shankar, Uma
2019-10-29 13:35     ` Shankar, Uma
2019-10-29 13:35       ` [Intel-gfx] " Shankar, Uma
2019-10-29 15:22       ` Ville Syrjälä
2019-10-29 15:22         ` [Intel-gfx] " Ville Syrjälä
2019-10-30 15:26         ` Shankar, Uma
2019-10-30 15:26           ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` Ville Syrjala [this message]
2019-10-29 13:22   ` [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active Shankar, Uma
2019-10-29 13:22     ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create() Ville Syrjala
2019-10-27 20:53   ` Juha-Pekka Heikkila
2019-10-27 20:53     ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-29 13:24   ` Shankar, Uma
2019-10-29 13:24     ` [Intel-gfx] " Shankar, Uma
2019-10-08 18:24 ` ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Patchwork
2019-10-09  0:55 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-10-09 15:45 ` ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2) Patchwork
2019-10-09 21:12 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-10-14 19:23   ` Ville Syrjälä
2019-10-14 20:23     ` Chris Wilson
2019-10-15  6:41     ` Arkadiusz Hiler
2019-10-15  9:25       ` Petri Latvala
2019-10-15 11:51         ` Ville Syrjälä
2019-10-15 12:08         ` Arkadiusz Hiler
2019-10-29  9:08 ` [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Shankar, Uma
2019-10-29  9:08   ` [Intel-gfx] " Shankar, Uma
2019-10-29 20:15 ` Juha-Pekka Heikkila
2019-10-29 20:15   ` [Intel-gfx] " Juha-Pekka Heikkila

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