From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes
Date: Tue, 8 Oct 2019 19:14:36 +0300 [thread overview]
Message-ID: <20191008161441.12721-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20191008161441.12721-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
VLV/CHV sprite planes also support the C8 format. Let's expose that.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index fb36da58390a..4cd0982dc8a2 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -846,6 +846,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
case DRM_FORMAT_VYUY:
sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
break;
+ case DRM_FORMAT_C8:
+ sprctl |= SP_FORMAT_8BPP;
+ break;
case DRM_FORMAT_RGB565:
sprctl |= SP_FORMAT_BGR565;
break;
@@ -2010,6 +2013,7 @@ static const u32 snb_plane_formats[] = {
};
static const u32 vlv_plane_formats[] = {
+ DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
@@ -2024,6 +2028,7 @@ static const u32 vlv_plane_formats[] = {
};
static const u32 chv_pipe_b_sprite_formats[] = {
+ DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
@@ -2256,6 +2261,7 @@ static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
}
switch (format) {
+ case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
case DRM_FORMAT_ABGR8888:
case DRM_FORMAT_ARGB8888:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 74bb5a6cbe4f..577468928ffa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6546,6 +6546,7 @@ enum {
#define SP_GAMMA_ENABLE (1 << 30)
#define SP_PIXFORMAT_MASK (0xf << 26)
#define SP_FORMAT_YUV422 (0x0 << 26)
+#define SP_FORMAT_8BPP (0x2 << 26)
#define SP_FORMAT_BGR565 (0x5 << 26)
#define SP_FORMAT_BGRX8888 (0x6 << 26)
#define SP_FORMAT_BGRA8888 (0x7 << 26)
--
2.21.0
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next prev parent reply other threads:[~2019-10-08 16:14 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
2019-10-08 16:14 ` [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes Ville Syrjala
2019-10-29 10:01 ` Shankar, Uma
2019-10-29 10:01 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV Ville Syrjala
2019-10-29 11:53 ` Shankar, Uma
2019-10-29 11:53 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` Ville Syrjala [this message]
2019-10-29 10:29 ` [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes Shankar, Uma
2019-10-29 10:29 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 5/9] drm/i915: Add 10bpc formats with alpha for icl+ Ville Syrjala
2019-10-09 10:43 ` [PATCH v2 " Ville Syrjala
2019-10-29 12:08 ` Shankar, Uma
2019-10-29 12:08 ` [Intel-gfx] " Shankar, Uma
2019-10-29 20:07 ` [PATCH " Juha-Pekka Heikkila
2019-10-29 20:07 ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-08 16:14 ` [PATCH 6/9] drm/i915: Sort format arrays consistently Ville Syrjala
2019-10-27 20:53 ` Juha-Pekka Heikkila
2019-10-27 20:53 ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-29 12:10 ` Shankar, Uma
2019-10-29 12:10 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+ Ville Syrjala
2019-10-29 13:07 ` Shankar, Uma
2019-10-29 13:07 ` [Intel-gfx] " Shankar, Uma
2019-10-29 13:35 ` Shankar, Uma
2019-10-29 13:35 ` [Intel-gfx] " Shankar, Uma
2019-10-29 15:22 ` Ville Syrjälä
2019-10-29 15:22 ` [Intel-gfx] " Ville Syrjälä
2019-10-30 15:26 ` Shankar, Uma
2019-10-30 15:26 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active Ville Syrjala
2019-10-29 13:22 ` Shankar, Uma
2019-10-29 13:22 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create() Ville Syrjala
2019-10-27 20:53 ` Juha-Pekka Heikkila
2019-10-27 20:53 ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-29 13:24 ` Shankar, Uma
2019-10-29 13:24 ` [Intel-gfx] " Shankar, Uma
2019-10-08 18:24 ` ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Patchwork
2019-10-09 0:55 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-10-09 15:45 ` ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2) Patchwork
2019-10-09 21:12 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-10-14 19:23 ` Ville Syrjälä
2019-10-14 20:23 ` Chris Wilson
2019-10-15 6:41 ` Arkadiusz Hiler
2019-10-15 9:25 ` Petri Latvala
2019-10-15 11:51 ` Ville Syrjälä
2019-10-15 12:08 ` Arkadiusz Hiler
2019-10-29 9:08 ` [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Shankar, Uma
2019-10-29 9:08 ` [Intel-gfx] " Shankar, Uma
2019-10-29 20:15 ` Juha-Pekka Heikkila
2019-10-29 20:15 ` [Intel-gfx] " Juha-Pekka Heikkila
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