Re: [PATCH 01/14] drm/i915: Rework watermark readout to use plane api

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Oct 17, 2019 at 03:20:52PM +0200, Maarten Lankhorst wrote:
> Instead of unconditionally verifying the cursor plane, handle it in the
> same way as any other plane, and use our existing api to verify.
> 
> While at it, ensure that on gen9+ we verify active_planes mask as well.
> This should give the correct results for planar YUV planes too, as we
> update active_planes for them.

Why is that hidden in the watermark verification code? We already have
intel_verify_planes() which seems like a better fit.

> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 83 ++++++--------------
>  1 file changed, 23 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 164ded862148..945ab2180614 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12932,7 +12932,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  	struct skl_pipe_wm *sw_wm;
>  	struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
>  	const enum pipe pipe = crtc->pipe;
> -	int plane, level, max_level = ilk_wm_max_level(dev_priv);
> +	int level, max_level = ilk_wm_max_level(dev_priv);
> +	struct intel_plane *plane;
>  
>  	if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
>  		return;
> @@ -12956,63 +12957,25 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  			  hw->ddb.enabled_slices);
>  
>  	/* planes */
> -	for_each_universal_plane(dev_priv, pipe, plane) {
> +	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
>  		struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> +		enum pipe plane_pipe = pipe;
>  
> -		hw_plane_wm = &hw->wm.planes[plane];
> -		sw_plane_wm = &sw_wm->planes[plane];
> -
> -		/* Watermarks */
> -		for (level = 0; level <= max_level; level++) {
> -			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> -						&sw_plane_wm->wm[level]))
> -				continue;
> -
> -			DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				  pipe_name(pipe), plane + 1, level,
> -				  sw_plane_wm->wm[level].plane_en,
> -				  sw_plane_wm->wm[level].plane_res_b,
> -				  sw_plane_wm->wm[level].plane_res_l,
> -				  hw_plane_wm->wm[level].plane_en,
> -				  hw_plane_wm->wm[level].plane_res_b,
> -				  hw_plane_wm->wm[level].plane_res_l);
> -		}
> +		hw_plane_wm = &hw->wm.planes[plane->id];
> +		sw_plane_wm = &sw_wm->planes[plane->id];
>  
> -		if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
> -					 &sw_plane_wm->trans_wm)) {
> -			DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				  pipe_name(pipe), plane + 1,
> -				  sw_plane_wm->trans_wm.plane_en,
> -				  sw_plane_wm->trans_wm.plane_res_b,
> -				  sw_plane_wm->trans_wm.plane_res_l,
> -				  hw_plane_wm->trans_wm.plane_en,
> -				  hw_plane_wm->trans_wm.plane_res_b,
> -				  hw_plane_wm->trans_wm.plane_res_l);
> -		}
> -
> -		/* DDB */
> -		hw_ddb_entry = &hw->ddb_y[plane];
> -		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
> -
> -		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
> -			DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
> -				  pipe_name(pipe), plane + 1,
> -				  sw_ddb_entry->start, sw_ddb_entry->end,
> -				  hw_ddb_entry->start, hw_ddb_entry->end);
> +		if (!plane->get_hw_state(plane, &plane_pipe)) {
> +			WARN(new_crtc_state->active_planes & BIT(plane->id),
> +			     "pipe %c %s should be visible, but isn't\n",
> +			     pipe_name(pipe), plane->base.name);
> +			continue;
>  		}
> -	}
>  
> -	/*
> -	 * cursor
> -	 * If the cursor plane isn't active, we may not have updated it's ddb
> -	 * allocation. In that case since the ddb allocation will be updated
> -	 * once the plane becomes visible, we can skip this check
> -	 */
> -	if (1) {
> -		struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> +		WARN_ON(plane_pipe != pipe);
>  
> -		hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
> -		sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
> +		WARN(!(new_crtc_state->active_planes & BIT(plane->id)),
> +		     "pipe %c %s should be invisible, but visible.\n",
> +		     pipe_name(pipe), plane->base.name);
>  
>  		/* Watermarks */
>  		for (level = 0; level <= max_level; level++) {
> @@ -13020,8 +12983,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  						&sw_plane_wm->wm[level]))
>  				continue;
>  
> -			DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				  pipe_name(pipe), level,
> +			DRM_ERROR("mismatch in WM pipe %c %s level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> +				  pipe_name(pipe), plane->base.name, level,
>  				  sw_plane_wm->wm[level].plane_en,
>  				  sw_plane_wm->wm[level].plane_res_b,
>  				  sw_plane_wm->wm[level].plane_res_l,
> @@ -13032,8 +12995,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  
>  		if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
>  					 &sw_plane_wm->trans_wm)) {
> -			DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				  pipe_name(pipe),
> +			DRM_ERROR("mismatch in trans WM pipe %c %s (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> +				  pipe_name(pipe), plane->base.name,
>  				  sw_plane_wm->trans_wm.plane_en,
>  				  sw_plane_wm->trans_wm.plane_res_b,
>  				  sw_plane_wm->trans_wm.plane_res_l,
> @@ -13043,12 +13006,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		}
>  
>  		/* DDB */
> -		hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
> -		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
> +		hw_ddb_entry = &hw->ddb_y[plane->id];
> +		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
>  
>  		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
> -			DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
> -				  pipe_name(pipe),
> +			DRM_ERROR("mismatch in DDB state pipe %c %s (expected (%u,%u), found (%u,%u))\n",
> +				  pipe_name(pipe), plane->base.name,
>  				  sw_ddb_entry->start, sw_ddb_entry->end,
>  				  hw_ddb_entry->start, hw_ddb_entry->end);
>  		}
> -- 
> 2.23.0
> 
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-- 
Ville Syrjälä
Intel
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