Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 5/7] drm/i915: Don't try to place HWS in non-existing mappable region
Date: Tue, 29 Oct 2019 09:58:54 +0000	[thread overview]
Message-ID: <20191029095856.25431-5-matthew.auld@intel.com> (raw)
In-Reply-To: <20191029095856.25431-1-matthew.auld@intel.com>

From: Michal Wajdeczko <michal.wajdeczko@intel.com>

HWS placement restrictions can't just rely on HAS_LLC flag.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9cc1ea6519ec..355523114c71 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -528,7 +528,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine,
 	unsigned int flags;
 
 	flags = PIN_GLOBAL;
-	if (!HAS_LLC(engine->i915))
+	if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
 		/*
 		 * On g33, we cannot place HWS above 256MiB, so
 		 * restrict its pinning to the low mappable arena.
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 5/7] drm/i915: Don't try to place HWS in non-existing mappable region
Date: Tue, 29 Oct 2019 09:58:54 +0000	[thread overview]
Message-ID: <20191029095856.25431-5-matthew.auld@intel.com> (raw)
Message-ID: <20191029095854.gta1pyWoJooIgBuPb7clrvQpjgeeJRUk_5fiii4Bfp8@z> (raw)
In-Reply-To: <20191029095856.25431-1-matthew.auld@intel.com>

From: Michal Wajdeczko <michal.wajdeczko@intel.com>

HWS placement restrictions can't just rely on HAS_LLC flag.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9cc1ea6519ec..355523114c71 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -528,7 +528,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine,
 	unsigned int flags;
 
 	flags = PIN_GLOBAL;
-	if (!HAS_LLC(engine->i915))
+	if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
 		/*
 		 * On g33, we cannot place HWS above 256MiB, so
 		 * restrict its pinning to the low mappable arena.
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-10-29  9:59 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-29  9:58 [PATCH 1/7] drm/i915: define i915_ggtt_has_aperture Matthew Auld
2019-10-29  9:58 ` [Intel-gfx] " Matthew Auld
2019-10-29  9:58 ` [PATCH 2/7] drm/i915: do not map aperture if it is not available Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:04   ` Chris Wilson
2019-10-29 10:04     ` [Intel-gfx] " Chris Wilson
2019-10-29  9:58 ` [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:06   ` Chris Wilson
2019-10-29 10:06     ` [Intel-gfx] " Chris Wilson
2019-10-29 21:23   ` Daniele Ceraolo Spurio
2019-10-29 21:23     ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-29 21:44     ` Chris Wilson
2019-10-29 21:44       ` [Intel-gfx] " Chris Wilson
2019-10-29 21:50       ` Daniele Ceraolo Spurio
2019-10-29 21:50         ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-29  9:58 ` [PATCH 4/7] drm/i915: error capture with no ggtt slot Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:06   ` Chris Wilson
2019-10-29 10:06     ` [Intel-gfx] " Chris Wilson
2019-10-29  9:58 ` Matthew Auld [this message]
2019-10-29  9:58   ` [Intel-gfx] [PATCH 5/7] drm/i915: Don't try to place HWS in non-existing mappable region Matthew Auld
2019-10-29 10:07   ` Chris Wilson
2019-10-29 10:07     ` [Intel-gfx] " Chris Wilson
2019-10-29  9:58 ` [PATCH 6/7] drm/i915: don't allocate the ring in stolen if we lack aperture Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:08   ` Chris Wilson
2019-10-29 10:08     ` [Intel-gfx] " Chris Wilson
2019-10-29 21:46   ` Daniele Ceraolo Spurio
2019-10-29 21:46     ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-29 21:51     ` Chris Wilson
2019-10-29 21:51       ` [Intel-gfx] " Chris Wilson
2019-10-29 21:59       ` Daniele Ceraolo Spurio
2019-10-29 21:59         ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-29  9:58 ` [PATCH 7/7] drm/i915/selftests: check for missing aperture Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:09   ` Chris Wilson
2019-10-29 10:09     ` [Intel-gfx] " Chris Wilson
2019-10-29 10:02 ` [PATCH 1/7] drm/i915: define i915_ggtt_has_aperture Chris Wilson
2019-10-29 10:02   ` [Intel-gfx] " Chris Wilson
2019-10-29 10:17 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] " Patchwork
2019-10-29 10:17   ` [Intel-gfx] " Patchwork
2019-10-29 10:20 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-10-29 10:20   ` [Intel-gfx] " Patchwork
2019-10-29 10:37 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-29 10:37   ` [Intel-gfx] " Patchwork
2019-10-29 21:16 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-29 21:16   ` [Intel-gfx] " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191029095856.25431-5-matthew.auld@intel.com \
    --to=matthew.auld@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox