From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Matthew Auld <matthew.auld@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: "Vetter, Daniel" <daniel.vetter@intel.com>
Subject: Re: [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture
Date: Tue, 29 Oct 2019 14:50:17 -0700 [thread overview]
Message-ID: <673e0a9a-939d-04cc-d4b9-b8d356920c0d@intel.com> (raw)
In-Reply-To: <157238547307.2489.1734253925833176897@skylake-alporthouse-com>
On 10/29/19 2:44 PM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-10-29 21:23:16)
>>
>>
>> On 10/29/19 2:58 AM, Matthew Auld wrote:
>>> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>>
>>> We can't fence anything without aperture.
>>>
>>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++++--
>>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> index 321189e1b0f2..71efccfde122 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> @@ -846,8 +846,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>>>
>>> detect_bit_6_swizzle(ggtt);
>>>
>>> - if (INTEL_GEN(i915) >= 7 &&
>>> - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
>>> + if (!i915_ggtt_has_aperture(ggtt))
>>
>> Daniel had mentioned that the fencing HW has been nerfed in gen12 and
>> suggested settings num_fences to zero for all gen12+. Should we go
>> directly with that?
>
> Do fences exist, yes/no? If there are literally no fences forevermore...
> tgl begs to differ though.
> -Chris
>
The registers are there in the specs and I don't see any special notes
about their usage. I'll leave it to Daniel to comment on the capability
reduction he mentioned. Not a blocker for this patch in the meantime.
Daniele
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Matthew Auld <matthew.auld@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: "Vetter, Daniel" <daniel.vetter@intel.com>
Subject: Re: [Intel-gfx] [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture
Date: Tue, 29 Oct 2019 14:50:17 -0700 [thread overview]
Message-ID: <673e0a9a-939d-04cc-d4b9-b8d356920c0d@intel.com> (raw)
Message-ID: <20191029215017.CT16JljAR2PA7jWVTJ0weft23U6L-maA29IKRfDKt5E@z> (raw)
In-Reply-To: <157238547307.2489.1734253925833176897@skylake-alporthouse-com>
On 10/29/19 2:44 PM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-10-29 21:23:16)
>>
>>
>> On 10/29/19 2:58 AM, Matthew Auld wrote:
>>> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>>
>>> We can't fence anything without aperture.
>>>
>>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++++--
>>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> index 321189e1b0f2..71efccfde122 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> @@ -846,8 +846,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>>>
>>> detect_bit_6_swizzle(ggtt);
>>>
>>> - if (INTEL_GEN(i915) >= 7 &&
>>> - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
>>> + if (!i915_ggtt_has_aperture(ggtt))
>>
>> Daniel had mentioned that the fencing HW has been nerfed in gen12 and
>> suggested settings num_fences to zero for all gen12+. Should we go
>> directly with that?
>
> Do fences exist, yes/no? If there are literally no fences forevermore...
> tgl begs to differ though.
> -Chris
>
The registers are there in the specs and I don't see any special notes
about their usage. I'll leave it to Daniel to comment on the capability
reduction he mentioned. Not a blocker for this patch in the meantime.
Daniele
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-10-29 21:50 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-29 9:58 [PATCH 1/7] drm/i915: define i915_ggtt_has_aperture Matthew Auld
2019-10-29 9:58 ` [Intel-gfx] " Matthew Auld
2019-10-29 9:58 ` [PATCH 2/7] drm/i915: do not map aperture if it is not available Matthew Auld
2019-10-29 9:58 ` [Intel-gfx] " Matthew Auld
2019-10-29 10:04 ` Chris Wilson
2019-10-29 10:04 ` [Intel-gfx] " Chris Wilson
2019-10-29 9:58 ` [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture Matthew Auld
2019-10-29 9:58 ` [Intel-gfx] " Matthew Auld
2019-10-29 10:06 ` Chris Wilson
2019-10-29 10:06 ` [Intel-gfx] " Chris Wilson
2019-10-29 21:23 ` Daniele Ceraolo Spurio
2019-10-29 21:23 ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-29 21:44 ` Chris Wilson
2019-10-29 21:44 ` [Intel-gfx] " Chris Wilson
2019-10-29 21:50 ` Daniele Ceraolo Spurio [this message]
2019-10-29 21:50 ` Daniele Ceraolo Spurio
2019-10-29 9:58 ` [PATCH 4/7] drm/i915: error capture with no ggtt slot Matthew Auld
2019-10-29 9:58 ` [Intel-gfx] " Matthew Auld
2019-10-29 10:06 ` Chris Wilson
2019-10-29 10:06 ` [Intel-gfx] " Chris Wilson
2019-10-29 9:58 ` [PATCH 5/7] drm/i915: Don't try to place HWS in non-existing mappable region Matthew Auld
2019-10-29 9:58 ` [Intel-gfx] " Matthew Auld
2019-10-29 10:07 ` Chris Wilson
2019-10-29 10:07 ` [Intel-gfx] " Chris Wilson
2019-10-29 9:58 ` [PATCH 6/7] drm/i915: don't allocate the ring in stolen if we lack aperture Matthew Auld
2019-10-29 9:58 ` [Intel-gfx] " Matthew Auld
2019-10-29 10:08 ` Chris Wilson
2019-10-29 10:08 ` [Intel-gfx] " Chris Wilson
2019-10-29 21:46 ` Daniele Ceraolo Spurio
2019-10-29 21:46 ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-29 21:51 ` Chris Wilson
2019-10-29 21:51 ` [Intel-gfx] " Chris Wilson
2019-10-29 21:59 ` Daniele Ceraolo Spurio
2019-10-29 21:59 ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-29 9:58 ` [PATCH 7/7] drm/i915/selftests: check for missing aperture Matthew Auld
2019-10-29 9:58 ` [Intel-gfx] " Matthew Auld
2019-10-29 10:09 ` Chris Wilson
2019-10-29 10:09 ` [Intel-gfx] " Chris Wilson
2019-10-29 10:02 ` [PATCH 1/7] drm/i915: define i915_ggtt_has_aperture Chris Wilson
2019-10-29 10:02 ` [Intel-gfx] " Chris Wilson
2019-10-29 10:17 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] " Patchwork
2019-10-29 10:17 ` [Intel-gfx] " Patchwork
2019-10-29 10:20 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-10-29 10:20 ` [Intel-gfx] " Patchwork
2019-10-29 10:37 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-29 10:37 ` [Intel-gfx] " Patchwork
2019-10-29 21:16 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-29 21:16 ` [Intel-gfx] " Patchwork
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