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From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org
Cc: "Vetter, Daniel" <daniel.vetter@intel.com>
Subject: Re: [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture
Date: Tue, 29 Oct 2019 14:23:16 -0700	[thread overview]
Message-ID: <4c986074-2364-5815-efde-6134a3ce741d@intel.com> (raw)
In-Reply-To: <20191029095856.25431-3-matthew.auld@intel.com>



On 10/29/19 2:58 AM, Matthew Auld wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> 
> We can't fence anything without aperture.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index 321189e1b0f2..71efccfde122 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -846,8 +846,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>   
>   	detect_bit_6_swizzle(ggtt);
>   
> -	if (INTEL_GEN(i915) >= 7 &&
> -	    !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
> +	if (!i915_ggtt_has_aperture(ggtt))

Daniel had mentioned that the fencing HW has been nerfed in gen12 and 
suggested settings num_fences to zero for all gen12+. Should we go 
directly with that?

Daniele

> +		num_fences = 0;
> +	else if (INTEL_GEN(i915) >= 7 &&
> +		 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
>   		num_fences = 32;
>   	else if (INTEL_GEN(i915) >= 4 ||
>   		 IS_I945G(i915) || IS_I945GM(i915) ||
> 
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org
Cc: "Vetter, Daniel" <daniel.vetter@intel.com>
Subject: Re: [Intel-gfx] [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture
Date: Tue, 29 Oct 2019 14:23:16 -0700	[thread overview]
Message-ID: <4c986074-2364-5815-efde-6134a3ce741d@intel.com> (raw)
Message-ID: <20191029212316.AwWU6SjF0Yj6T1jtFRxrPbyiXNPKpBzttfh8Dfqui0U@z> (raw)
In-Reply-To: <20191029095856.25431-3-matthew.auld@intel.com>



On 10/29/19 2:58 AM, Matthew Auld wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> 
> We can't fence anything without aperture.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index 321189e1b0f2..71efccfde122 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -846,8 +846,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>   
>   	detect_bit_6_swizzle(ggtt);
>   
> -	if (INTEL_GEN(i915) >= 7 &&
> -	    !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
> +	if (!i915_ggtt_has_aperture(ggtt))

Daniel had mentioned that the fencing HW has been nerfed in gen12 and 
suggested settings num_fences to zero for all gen12+. Should we go 
directly with that?

Daniele

> +		num_fences = 0;
> +	else if (INTEL_GEN(i915) >= 7 &&
> +		 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
>   		num_fences = 32;
>   	else if (INTEL_GEN(i915) >= 4 ||
>   		 IS_I945G(i915) || IS_I945GM(i915) ||
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-10-29 21:23 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-29  9:58 [PATCH 1/7] drm/i915: define i915_ggtt_has_aperture Matthew Auld
2019-10-29  9:58 ` [Intel-gfx] " Matthew Auld
2019-10-29  9:58 ` [PATCH 2/7] drm/i915: do not map aperture if it is not available Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:04   ` Chris Wilson
2019-10-29 10:04     ` [Intel-gfx] " Chris Wilson
2019-10-29  9:58 ` [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:06   ` Chris Wilson
2019-10-29 10:06     ` [Intel-gfx] " Chris Wilson
2019-10-29 21:23   ` Daniele Ceraolo Spurio [this message]
2019-10-29 21:23     ` Daniele Ceraolo Spurio
2019-10-29 21:44     ` Chris Wilson
2019-10-29 21:44       ` [Intel-gfx] " Chris Wilson
2019-10-29 21:50       ` Daniele Ceraolo Spurio
2019-10-29 21:50         ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-29  9:58 ` [PATCH 4/7] drm/i915: error capture with no ggtt slot Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:06   ` Chris Wilson
2019-10-29 10:06     ` [Intel-gfx] " Chris Wilson
2019-10-29  9:58 ` [PATCH 5/7] drm/i915: Don't try to place HWS in non-existing mappable region Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:07   ` Chris Wilson
2019-10-29 10:07     ` [Intel-gfx] " Chris Wilson
2019-10-29  9:58 ` [PATCH 6/7] drm/i915: don't allocate the ring in stolen if we lack aperture Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:08   ` Chris Wilson
2019-10-29 10:08     ` [Intel-gfx] " Chris Wilson
2019-10-29 21:46   ` Daniele Ceraolo Spurio
2019-10-29 21:46     ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-29 21:51     ` Chris Wilson
2019-10-29 21:51       ` [Intel-gfx] " Chris Wilson
2019-10-29 21:59       ` Daniele Ceraolo Spurio
2019-10-29 21:59         ` [Intel-gfx] " Daniele Ceraolo Spurio
2019-10-29  9:58 ` [PATCH 7/7] drm/i915/selftests: check for missing aperture Matthew Auld
2019-10-29  9:58   ` [Intel-gfx] " Matthew Auld
2019-10-29 10:09   ` Chris Wilson
2019-10-29 10:09     ` [Intel-gfx] " Chris Wilson
2019-10-29 10:02 ` [PATCH 1/7] drm/i915: define i915_ggtt_has_aperture Chris Wilson
2019-10-29 10:02   ` [Intel-gfx] " Chris Wilson
2019-10-29 10:17 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] " Patchwork
2019-10-29 10:17   ` [Intel-gfx] " Patchwork
2019-10-29 10:20 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-10-29 10:20   ` [Intel-gfx] " Patchwork
2019-10-29 10:37 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-29 10:37   ` [Intel-gfx] " Patchwork
2019-10-29 21:16 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-29 21:16   ` [Intel-gfx] " Patchwork

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