From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v2 06/20] drm/i915: Polish some dbuf debugs
Date: Wed, 4 Mar 2020 20:26:59 +0200 [thread overview]
Message-ID: <20200304182659.GE13686@intel.com> (raw)
In-Reply-To: <67b2f1122c23316304d0e10f57a0d356705bafc0.camel@intel.com>
On Wed, Mar 04, 2020 at 04:29:47PM +0000, Lisovskiy, Stanislav wrote:
> On Tue, 2020-02-25 at 19:11 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Polish some of the dbuf code to give more meaningful debug
> > messages and whatnot. Also we can switch over to the per-device
> > debugs/warns at the same time.
> >
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > .../drm/i915/display/intel_display_power.c | 40 +++++++++------
> > ----
> > 1 file changed, 19 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 6e25a1317161..e81e561e8ac0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -4433,11 +4433,12 @@ static void
> > intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
> > mutex_unlock(&power_domains->lock);
> > }
> >
> > -static inline
> > -bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv,
> > - i915_reg_t reg, bool enable)
> > +static void intel_dbuf_slice_set(struct drm_i915_private *dev_priv,
> > + enum dbuf_slice slice, bool enable)
> > {
> > - u32 val, status;
> > + i915_reg_t reg = DBUF_CTL_S(slice);
> > + bool state;
> > + u32 val;
> >
> > val = intel_de_read(dev_priv, reg);
> > val = enable ? (val | DBUF_POWER_REQUEST) : (val &
> > ~DBUF_POWER_REQUEST);
> > @@ -4445,13 +4446,10 @@ bool intel_dbuf_slice_set(struct
> > drm_i915_private *dev_priv,
> > intel_de_posting_read(dev_priv, reg);
> > udelay(10);
> >
> > - status = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
> > - if ((enable && !status) || (!enable && status)) {
> > - drm_err(&dev_priv->drm, "DBus power %s timeout!\n",
> > - enable ? "enable" : "disable");
> > - return false;
> > - }
> > - return true;
> > + state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
> > + drm_WARN(&dev_priv->drm, enable != state,
> > + "DBuf slice %d power %s timeout!\n",
> > + slice, enable ? "enable" : "disable");
> > }
> >
> > static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
> > @@ -4467,14 +4465,16 @@ static void gen9_dbuf_disable(struct
> > drm_i915_private *dev_priv)
> > void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
> > u8 req_slices)
> > {
> > - int i;
> > - int max_slices = INTEL_INFO(dev_priv)-
> > >num_supported_dbuf_slices;
> > + int num_slices = INTEL_INFO(dev_priv)-
> > >num_supported_dbuf_slices;
> > struct i915_power_domains *power_domains = &dev_priv-
> > >power_domains;
> > + enum dbuf_slice slice;
> >
> > - drm_WARN(&dev_priv->drm, hweight8(req_slices) > max_slices,
> > - "Invalid number of dbuf slices requested\n");
> > + drm_WARN(&dev_priv->drm, req_slices & ~(BIT(num_slices) - 1),
> > + "Invalid set of dbuf slices (0x%x) requested (num dbuf
> > slices %d)\n",
> > + req_slices, num_slices);
> >
> > - DRM_DEBUG_KMS("Updating dbuf slices to 0x%x\n", req_slices);
> > + drm_dbg_kms(&dev_priv->drm,
> > + "Updating dbuf slices to 0x%x\n", req_slices);
> >
> > /*
> > * Might be running this in parallel to
> > gen9_dc_off_power_well_enable
> > @@ -4485,11 +4485,9 @@ void icl_dbuf_slices_update(struct
> > drm_i915_private *dev_priv,
> > */
> > mutex_lock(&power_domains->lock);
> >
> > - for (i = 0; i < max_slices; i++) {
> > - intel_dbuf_slice_set(dev_priv,
> > - DBUF_CTL_S(i),
> > - (req_slices & BIT(i)) != 0);
> > - }
> > + for (slice = DBUF_S1; slice < num_slices; slice++)
> > + intel_dbuf_slice_set(dev_priv, slice,
> > + req_slices & BIT(slice));
>
> Would be cool to completely get rid of any magic numbers or
> definitions, 0 in a sense is more universal here than DBUF_S1.
>
> If we are counting slices as numbers it seems logical that we
> iterate [0..num_slices) range. If you want to name the first slice
> explicitly then it probably has to be something like iterator
> logic, i.e for (slice = FIRST_SLICE; slice != LAST_SLICE; slice++).
>
> But trying to name it at the same time with comparing to total _amount_
> looks a bit confusing.
This is the standard pattern used all over the driver.
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2020-03-04 18:27 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-25 17:11 [Intel-gfx] [PATCH v2 00/20] drm/i915: Proper dbuf global state Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 01/20] drm/i915: Handle some leftover s/intel_crtc/crtc/ Ville Syrjala
2020-02-26 9:29 ` Jani Nikula
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 02/20] drm/i915: Remove garbage WARNs Ville Syrjala
2020-02-26 9:30 ` Jani Nikula
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 03/20] drm/i915: Add missing commas to dbuf tables Ville Syrjala
2020-02-26 9:30 ` Jani Nikula
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 04/20] drm/i915: Use a sentinel to terminate the dbuf slice arrays Ville Syrjala
2020-02-26 9:32 ` Jani Nikula
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 05/20] drm/i915: Make skl_compute_dbuf_slices() behave consistently for all platforms Ville Syrjala
2020-02-25 17:30 ` Lisovskiy, Stanislav
2020-03-02 14:50 ` Ville Syrjälä
2020-03-02 15:50 ` Lisovskiy, Stanislav
2020-04-01 7:52 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 06/20] drm/i915: Polish some dbuf debugs Ville Syrjala
2020-03-04 16:29 ` Lisovskiy, Stanislav
2020-03-04 18:26 ` Ville Syrjälä [this message]
2020-03-05 9:53 ` Lisovskiy, Stanislav
2020-03-05 13:46 ` Ville Syrjälä
2020-03-05 14:56 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 07/20] drm/i915: Unify the low level dbuf code Ville Syrjala
2020-03-04 17:14 ` Lisovskiy, Stanislav
2020-03-04 17:23 ` Lisovskiy, Stanislav
2020-03-04 18:30 ` Ville Syrjälä
2020-03-05 8:28 ` Lisovskiy, Stanislav
2020-03-05 13:37 ` Ville Syrjälä
2020-03-05 14:01 ` Lisovskiy, Stanislav
2020-03-05 8:46 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 08/20] drm/i915: Introduce proper dbuf state Ville Syrjala
2020-02-25 17:43 ` Lisovskiy, Stanislav
2020-04-01 8:13 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 09/20] drm/i915: Nuke skl_ddb_get_hw_state() Ville Syrjala
2020-02-26 11:40 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 10/20] drm/i915: Move the dbuf pre/post plane update Ville Syrjala
2020-02-26 11:38 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 11/20] drm/i915: Clean up dbuf debugs during .atomic_check() Ville Syrjala
2020-02-26 11:32 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 12/20] drm/i915: Extract intel_crtc_ddb_weight() Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 13/20] drm/i915: Pass the crtc to skl_compute_dbuf_slices() Ville Syrjala
2020-02-26 8:41 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 14/20] drm/i915: Introduce intel_dbuf_slice_size() Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 15/20] drm/i915: Introduce skl_ddb_entry_for_slices() Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 16/20] drm/i915: Move pipe ddb entries into the dbuf state Ville Syrjala
2020-02-27 16:50 ` Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 17/20] drm/i915: Extract intel_crtc_dbuf_weights() Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 18/20] drm/i915: Encapsulate dbuf state handling harder Ville Syrjala
2021-01-21 12:55 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 19/20] drm/i915: Do a bit more initial readout for dbuf Ville Syrjala
2021-01-21 12:57 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 20/20] drm/i915: Check slice mask for holes Ville Syrjala
2020-02-25 17:47 ` Lisovskiy, Stanislav
2020-02-26 18:04 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Proper dbuf global state (rev2) Patchwork
2020-02-27 20:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Proper dbuf global state (rev3) Patchwork
2020-02-27 20:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-29 2:40 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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