Re: [Intel-gfx] [PATCH v2 19/20] drm/i915: Do a bit more initial readout for dbuf

["Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>]

On Tue, Feb 25, 2020 at 07:11:24PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Readout the dbuf related stuff during driver init/resume and
> stick it into our dbuf state.
> 
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  4 --
>  drivers/gpu/drm/i915/intel_pm.c              | 48 +++++++++++++++++++-
>  2 files changed, 46 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e3df43f3932d..21ad1adcc1eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17475,14 +17475,10 @@ void intel_modeset_init_hw(struct drm_i915_private *i915)
>  {
>  	struct intel_cdclk_state *cdclk_state =
>  		to_intel_cdclk_state(i915->cdclk.obj.state);
> -	struct intel_dbuf_state *dbuf_state =
> -		to_intel_dbuf_state(i915->dbuf.obj.state);
>  
>  	intel_update_cdclk(i915);
>  	intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
>  	cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
> -
> -	dbuf_state->enabled_slices = i915->dbuf.enabled_slices;
>  }
>  
>  static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c11508fb3fac..7edac506d343 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5363,6 +5363,18 @@ static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
>  	return a->start < b->end && b->start < a->end;
>  }
>  
> +static void skl_ddb_entry_union(struct skl_ddb_entry *a,
> +				const struct skl_ddb_entry *b)
> +{
> +	if (a->end && b->end) {
> +		a->start = min(a->start, b->start);
> +		a->end = max(a->end, b->end);
> +	} else if (b->end) {
> +		a->start = b->start;
> +		a->end = b->end;
> +	}
> +}
> +
>  bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
>  				 const struct skl_ddb_entry *entries,
>  				 int num_entries, int ignore_idx)
> @@ -5857,14 +5869,46 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  
>  void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  {
> +	struct intel_dbuf_state *dbuf_state =
> +		to_intel_dbuf_state(dev_priv->dbuf.obj.state);
>  	struct intel_crtc *crtc;
> -	struct intel_crtc_state *crtc_state;
>  
>  	for_each_intel_crtc(&dev_priv->drm, crtc) {
> -		crtc_state = to_intel_crtc_state(crtc->base.state);
> +		struct intel_crtc_state *crtc_state =
> +			to_intel_crtc_state(crtc->base.state);
> +		enum pipe pipe = crtc->pipe;
> +		enum plane_id plane_id;
>  
>  		skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
> +
> +		memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));
> +
> +		for_each_plane_id_on_crtc(crtc, plane_id) {
> +			struct skl_ddb_entry *ddb_y =
> +				&crtc_state->wm.skl.plane_ddb_y[plane_id];
> +			struct skl_ddb_entry *ddb_uv =
> +				&crtc_state->wm.skl.plane_ddb_uv[plane_id];
> +
> +			skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe,
> +						   plane_id, ddb_y, ddb_uv);
> +
> +			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);
> +			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv);
> +		}
> +
> +		dbuf_state->slices[pipe] =
> +			skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes);
> +
> +		dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
> +
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n",
> +			    crtc->base.base.id, crtc->base.name,
> +			    dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,
> +			    dbuf_state->ddb[pipe].end, dbuf_state->active_pipes);
>  	}
> +
> +	dbuf_state->enabled_slices = dev_priv->dbuf.enabled_slices;
>  }
>  
>  static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
> -- 
> 2.24.1
> 
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