From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 03/20] drm/i915: Add missing commas to dbuf tables
Date: Wed, 26 Feb 2020 11:30:54 +0200 [thread overview]
Message-ID: <87imjtsnjl.fsf@intel.com> (raw)
In-Reply-To: <20200225171125.28885-4-ville.syrjala@linux.intel.com>
On Tue, 25 Feb 2020, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The preferred style is to sprinkle commas after each array and
> structure initialization, whether or not it happens to be the
> last element/member (only exception being sentinel entries which
> never have anything after them). This leads to much prettier
> diffs if/when new elements/members get added to the end of the
> initialization. We're not bound by some ancient silly mandate
> to omit the final comma.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 88 ++++++++++++++++-----------------
> 1 file changed, 44 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 59fc461bc454..abeb4b19071f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4184,49 +4184,49 @@ static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] =
> {
> .active_pipes = BIT(PIPE_A),
> .dbuf_mask = {
> - [PIPE_A] = BIT(DBUF_S1)
> - }
> + [PIPE_A] = BIT(DBUF_S1),
> + },
> },
> {
> .active_pipes = BIT(PIPE_B),
> .dbuf_mask = {
> - [PIPE_B] = BIT(DBUF_S1)
> - }
> + [PIPE_B] = BIT(DBUF_S1),
> + },
> },
> {
> .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
> .dbuf_mask = {
> [PIPE_A] = BIT(DBUF_S1),
> - [PIPE_B] = BIT(DBUF_S2)
> - }
> + [PIPE_B] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_C),
> .dbuf_mask = {
> - [PIPE_C] = BIT(DBUF_S2)
> - }
> + [PIPE_C] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
> .dbuf_mask = {
> [PIPE_A] = BIT(DBUF_S1),
> - [PIPE_C] = BIT(DBUF_S2)
> - }
> + [PIPE_C] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
> .dbuf_mask = {
> [PIPE_B] = BIT(DBUF_S1),
> - [PIPE_C] = BIT(DBUF_S2)
> - }
> + [PIPE_C] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> .dbuf_mask = {
> [PIPE_A] = BIT(DBUF_S1),
> [PIPE_B] = BIT(DBUF_S1),
> - [PIPE_C] = BIT(DBUF_S2)
> - }
> + [PIPE_C] = BIT(DBUF_S2),
> + },
> },
> };
>
> @@ -4246,100 +4246,100 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
> {
> .active_pipes = BIT(PIPE_A),
> .dbuf_mask = {
> - [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2)
> - }
> + [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_B),
> .dbuf_mask = {
> - [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2)
> - }
> + [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
> .dbuf_mask = {
> [PIPE_A] = BIT(DBUF_S2),
> - [PIPE_B] = BIT(DBUF_S1)
> - }
> + [PIPE_B] = BIT(DBUF_S1),
> + },
> },
> {
> .active_pipes = BIT(PIPE_C),
> .dbuf_mask = {
> - [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1)
> - }
> + [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1),
> + },
> },
> {
> .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
> .dbuf_mask = {
> [PIPE_A] = BIT(DBUF_S1),
> - [PIPE_C] = BIT(DBUF_S2)
> - }
> + [PIPE_C] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
> .dbuf_mask = {
> [PIPE_B] = BIT(DBUF_S1),
> - [PIPE_C] = BIT(DBUF_S2)
> - }
> + [PIPE_C] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> .dbuf_mask = {
> [PIPE_A] = BIT(DBUF_S1),
> [PIPE_B] = BIT(DBUF_S1),
> - [PIPE_C] = BIT(DBUF_S2)
> - }
> + [PIPE_C] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_D),
> .dbuf_mask = {
> - [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1)
> - }
> + [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1),
> + },
> },
> {
> .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
> .dbuf_mask = {
> [PIPE_A] = BIT(DBUF_S1),
> - [PIPE_D] = BIT(DBUF_S2)
> - }
> + [PIPE_D] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
> .dbuf_mask = {
> [PIPE_B] = BIT(DBUF_S1),
> - [PIPE_D] = BIT(DBUF_S2)
> - }
> + [PIPE_D] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
> .dbuf_mask = {
> [PIPE_A] = BIT(DBUF_S1),
> [PIPE_B] = BIT(DBUF_S1),
> - [PIPE_D] = BIT(DBUF_S2)
> - }
> + [PIPE_D] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
> .dbuf_mask = {
> [PIPE_C] = BIT(DBUF_S1),
> - [PIPE_D] = BIT(DBUF_S2)
> - }
> + [PIPE_D] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
> .dbuf_mask = {
> [PIPE_A] = BIT(DBUF_S1),
> [PIPE_C] = BIT(DBUF_S2),
> - [PIPE_D] = BIT(DBUF_S2)
> - }
> + [PIPE_D] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> .dbuf_mask = {
> [PIPE_B] = BIT(DBUF_S1),
> [PIPE_C] = BIT(DBUF_S2),
> - [PIPE_D] = BIT(DBUF_S2)
> - }
> + [PIPE_D] = BIT(DBUF_S2),
> + },
> },
> {
> .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> @@ -4347,8 +4347,8 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
> [PIPE_A] = BIT(DBUF_S1),
> [PIPE_B] = BIT(DBUF_S1),
> [PIPE_C] = BIT(DBUF_S2),
> - [PIPE_D] = BIT(DBUF_S2)
> - }
> + [PIPE_D] = BIT(DBUF_S2),
> + },
> },
> };
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-02-26 9:30 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-25 17:11 [Intel-gfx] [PATCH v2 00/20] drm/i915: Proper dbuf global state Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 01/20] drm/i915: Handle some leftover s/intel_crtc/crtc/ Ville Syrjala
2020-02-26 9:29 ` Jani Nikula
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 02/20] drm/i915: Remove garbage WARNs Ville Syrjala
2020-02-26 9:30 ` Jani Nikula
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 03/20] drm/i915: Add missing commas to dbuf tables Ville Syrjala
2020-02-26 9:30 ` Jani Nikula [this message]
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 04/20] drm/i915: Use a sentinel to terminate the dbuf slice arrays Ville Syrjala
2020-02-26 9:32 ` Jani Nikula
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 05/20] drm/i915: Make skl_compute_dbuf_slices() behave consistently for all platforms Ville Syrjala
2020-02-25 17:30 ` Lisovskiy, Stanislav
2020-03-02 14:50 ` Ville Syrjälä
2020-03-02 15:50 ` Lisovskiy, Stanislav
2020-04-01 7:52 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 06/20] drm/i915: Polish some dbuf debugs Ville Syrjala
2020-03-04 16:29 ` Lisovskiy, Stanislav
2020-03-04 18:26 ` Ville Syrjälä
2020-03-05 9:53 ` Lisovskiy, Stanislav
2020-03-05 13:46 ` Ville Syrjälä
2020-03-05 14:56 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 07/20] drm/i915: Unify the low level dbuf code Ville Syrjala
2020-03-04 17:14 ` Lisovskiy, Stanislav
2020-03-04 17:23 ` Lisovskiy, Stanislav
2020-03-04 18:30 ` Ville Syrjälä
2020-03-05 8:28 ` Lisovskiy, Stanislav
2020-03-05 13:37 ` Ville Syrjälä
2020-03-05 14:01 ` Lisovskiy, Stanislav
2020-03-05 8:46 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 08/20] drm/i915: Introduce proper dbuf state Ville Syrjala
2020-02-25 17:43 ` Lisovskiy, Stanislav
2020-04-01 8:13 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 09/20] drm/i915: Nuke skl_ddb_get_hw_state() Ville Syrjala
2020-02-26 11:40 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 10/20] drm/i915: Move the dbuf pre/post plane update Ville Syrjala
2020-02-26 11:38 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 11/20] drm/i915: Clean up dbuf debugs during .atomic_check() Ville Syrjala
2020-02-26 11:32 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 12/20] drm/i915: Extract intel_crtc_ddb_weight() Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 13/20] drm/i915: Pass the crtc to skl_compute_dbuf_slices() Ville Syrjala
2020-02-26 8:41 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 14/20] drm/i915: Introduce intel_dbuf_slice_size() Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 15/20] drm/i915: Introduce skl_ddb_entry_for_slices() Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 16/20] drm/i915: Move pipe ddb entries into the dbuf state Ville Syrjala
2020-02-27 16:50 ` Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 17/20] drm/i915: Extract intel_crtc_dbuf_weights() Ville Syrjala
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 18/20] drm/i915: Encapsulate dbuf state handling harder Ville Syrjala
2021-01-21 12:55 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 19/20] drm/i915: Do a bit more initial readout for dbuf Ville Syrjala
2021-01-21 12:57 ` Lisovskiy, Stanislav
2020-02-25 17:11 ` [Intel-gfx] [PATCH v2 20/20] drm/i915: Check slice mask for holes Ville Syrjala
2020-02-25 17:47 ` Lisovskiy, Stanislav
2020-02-26 18:04 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Proper dbuf global state (rev2) Patchwork
2020-02-27 20:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Proper dbuf global state (rev3) Patchwork
2020-02-27 20:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-29 2:40 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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