From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 02/11] drm/i915/display/vrr: Create VRR file and add VRR capability check
Date: Thu, 22 Oct 2020 15:27:00 -0700 [thread overview]
Message-ID: <20201022222709.29386-3-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20201022222709.29386-1-manasi.d.navare@intel.com>
We create a new file for all VRR related helpers.
Also add a function to check vrr capability based on
platform support, DPCD bits and EDID monitor range.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 28 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 19 ++++++++++++++++
3 files changed, 48 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c
create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..3beeaf517191 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -249,6 +249,7 @@ i915-y += \
display/intel_sdvo.o \
display/intel_tv.o \
display/intel_vdsc.o \
+ display/intel_vrr.o \
display/vlv_dsi.o \
display/vlv_dsi_pll.o
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
new file mode 100644
index 000000000000..0c8a91fabb64
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Author: Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+#include "intel_vrr.h"
+
+bool intel_is_vrr_capable(struct drm_connector *connector)
+{
+ struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
+ const struct drm_display_info *info = &connector->display_info;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
+ /*
+ * DP Sink is capable of Variable refresh video timings if
+ * Ignore MSA bit is set in DPCD.
+ * EDID monitor range also should be atleast 10 for reasonable
+ * Adaptive sync/ VRR end user experience.
+ */
+ return INTEL_GEN(dev_priv) >= 12 &&
+ drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
+ info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
new file mode 100644
index 000000000000..755746c7525c
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+*/
+
+#ifndef __INTEL_VRR_H__
+#define __INTEL_VRR_H__
+
+#include <linux/types.h>
+
+struct drm_connector;
+struct drm_i915_private;
+struct intel_crtc_state;
+struct intel_encoder;
+struct intel_dp;
+
+bool intel_is_vrr_capable(struct drm_connector *connector);
+
+#endif /* __INTEL_VRR_H__ */
--
2.19.1
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next prev parent reply other threads:[~2020-10-22 22:25 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-22 22:26 [Intel-gfx] [PATCH 00/11] VRR/Adaptive Sync enabling in i915 Manasi Navare
2020-10-22 22:26 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add REG_FIELD_PREP to VRR register def Manasi Navare
2020-11-10 10:13 ` Jani Nikula
2020-12-01 22:41 ` Navare, Manasi
2020-10-22 22:27 ` Manasi Navare [this message]
2020-11-10 10:39 ` [Intel-gfx] [PATCH 02/11] drm/i915/display/vrr: Create VRR file and add VRR capability check Jani Nikula
2020-12-01 22:21 ` Navare, Manasi
2020-12-02 22:40 ` Navare, Manasi
2020-12-03 16:35 ` Jani Nikula
2020-12-03 19:38 ` Navare, Manasi
2020-11-10 16:06 ` Ville Syrjälä
2020-11-10 18:48 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 03/11] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2020-11-10 10:41 ` Jani Nikula
2020-12-01 22:46 ` Navare, Manasi
2020-12-03 16:37 ` Jani Nikula
2020-12-03 19:37 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 04/11] drm/i915/display/dp: Add VRR crtc state variables Manasi Navare
2020-11-10 10:41 ` Jani Nikula
2020-12-01 22:49 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 05/11] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2020-11-10 10:47 ` Jani Nikula
2020-12-01 22:52 ` Navare, Manasi
2020-12-02 22:38 ` Navare, Manasi
2020-12-03 16:39 ` Jani Nikula
2020-12-03 19:36 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 06/11] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2020-10-22 22:27 ` [Intel-gfx] [PATCH 07/11] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2020-11-10 10:56 ` Jani Nikula
2020-12-01 22:56 ` Navare, Manasi
2020-12-03 16:40 ` Jani Nikula
2020-10-22 22:27 ` [Intel-gfx] [PATCH 08/11] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2020-11-10 10:59 ` Jani Nikula
2020-12-01 22:57 ` Navare, Manasi
2020-12-03 19:58 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 09/11] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2020-11-10 11:01 ` Jani Nikula
2020-12-01 22:34 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 10/11] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2020-12-01 22:59 ` Navare, Manasi
2020-12-03 16:49 ` Jani Nikula
2020-12-03 19:33 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 11/11] drm/i915/display: Add HW state readout for VRR Manasi Navare
2020-10-23 17:42 ` [Intel-gfx] [PATCH v2 " Manasi Navare
2020-10-22 22:37 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for VRR/Adaptive Sync enabling in i915 Patchwork
2020-10-23 17:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync enabling in i915 (rev2) Patchwork
2020-10-23 17:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-23 18:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-23 21:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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