From: "Navare, Manasi" <manasi.d.navare@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 08/11] drm/i915/display/vrr: Send VRR push to flip the frame
Date: Tue, 1 Dec 2020 14:57:29 -0800 [thread overview]
Message-ID: <20201201225729.GD22644@labuser-Z97X-UD5H> (raw)
In-Reply-To: <87ft5hscjl.fsf@intel.com>
On Tue, Nov 10, 2020 at 12:59:10PM +0200, Jani Nikula wrote:
> On Thu, 22 Oct 2020, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > VRR achieves vblank stretching using the HW PUSH functionality.
> > So once the VRR is enabled during modeset then for each flip
> > request from userspace, in the atomic tail pipe_update_end()
> > we need to set the VRR push bit in HW for it to terminate
> > the vblank at configured flipline or anytime after flipline
> > or latest at the Vmax.
> >
> > The HW clears the PUSH bit after the double buffer updates
> > are completed.
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_sprite.c | 5 +++++
> > drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
> > 3 files changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index b6deeb338477..cb10fe462f06 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -49,6 +49,7 @@
> > #include "intel_psr.h"
> > #include "intel_dsi.h"
> > #include "intel_sprite.h"
> > +#include "intel_vrr.h"
> >
> > int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> > int usecs)
> > @@ -217,6 +218,10 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> > intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
> > icl_dsi_frame_update(new_crtc_state);
> >
> > + /* Send VRR Push to terminate Vblank */
> > + if (new_crtc_state->vrr.enable)
> > + intel_vrr_send_push(new_crtc_state);
> > +
>
> Maybe move the vrr.enable check to the function?
Yes makes sense will do
>
> > /* We're still in the vblank-evade critical section, this can't race.
> > * Would be slightly nice to just grab the vblank count and arm the
> > * event outside of the critical section - the spinlock might spin for a
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 7f1353bac583..ec1ce88e869c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -102,3 +102,20 @@ void intel_vrr_enable(struct intel_encoder *encoder,
> > trans_push);
> > }
> >
> > +void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + enum pipe pipe = crtc->pipe;
> > + u32 trans_push;
> > +
> > + trans_push = intel_de_read(dev_priv, TRANS_PUSH(pipe));
> > + WARN_ON(!(trans_push & TRANS_PUSH_EN));
>
> drm_WARN_ON, and perhaps move this below the register rmw. It doesn't
> change the flow anyway.
Yes will do
Manasi
>
> > +
> > + trans_push |= TRANS_PUSH_SEND;
> > + intel_de_write(dev_priv, TRANS_PUSH(pipe), trans_push);
> > +
> > + drm_dbg(&dev_priv->drm, "Sending VRR Push on Pipe (%c)\n",
> > + pipe_name(pipe));
>
> drm_dbg_kms
>
> > +}
> > +
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> > index 05d982d6fbae..a6b78e1676cb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> > @@ -19,5 +19,6 @@ void intel_vrr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state);
> > void intel_vrr_enable(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state);
> > +void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
> >
> > #endif /* __INTEL_VRR_H__ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2020-12-01 22:54 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-22 22:26 [Intel-gfx] [PATCH 00/11] VRR/Adaptive Sync enabling in i915 Manasi Navare
2020-10-22 22:26 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add REG_FIELD_PREP to VRR register def Manasi Navare
2020-11-10 10:13 ` Jani Nikula
2020-12-01 22:41 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 02/11] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2020-11-10 10:39 ` Jani Nikula
2020-12-01 22:21 ` Navare, Manasi
2020-12-02 22:40 ` Navare, Manasi
2020-12-03 16:35 ` Jani Nikula
2020-12-03 19:38 ` Navare, Manasi
2020-11-10 16:06 ` Ville Syrjälä
2020-11-10 18:48 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 03/11] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2020-11-10 10:41 ` Jani Nikula
2020-12-01 22:46 ` Navare, Manasi
2020-12-03 16:37 ` Jani Nikula
2020-12-03 19:37 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 04/11] drm/i915/display/dp: Add VRR crtc state variables Manasi Navare
2020-11-10 10:41 ` Jani Nikula
2020-12-01 22:49 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 05/11] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2020-11-10 10:47 ` Jani Nikula
2020-12-01 22:52 ` Navare, Manasi
2020-12-02 22:38 ` Navare, Manasi
2020-12-03 16:39 ` Jani Nikula
2020-12-03 19:36 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 06/11] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2020-10-22 22:27 ` [Intel-gfx] [PATCH 07/11] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2020-11-10 10:56 ` Jani Nikula
2020-12-01 22:56 ` Navare, Manasi
2020-12-03 16:40 ` Jani Nikula
2020-10-22 22:27 ` [Intel-gfx] [PATCH 08/11] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2020-11-10 10:59 ` Jani Nikula
2020-12-01 22:57 ` Navare, Manasi [this message]
2020-12-03 19:58 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 09/11] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2020-11-10 11:01 ` Jani Nikula
2020-12-01 22:34 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 10/11] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2020-12-01 22:59 ` Navare, Manasi
2020-12-03 16:49 ` Jani Nikula
2020-12-03 19:33 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 11/11] drm/i915/display: Add HW state readout for VRR Manasi Navare
2020-10-23 17:42 ` [Intel-gfx] [PATCH v2 " Manasi Navare
2020-10-22 22:37 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for VRR/Adaptive Sync enabling in i915 Patchwork
2020-10-23 17:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync enabling in i915 (rev2) Patchwork
2020-10-23 17:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-23 18:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-23 21:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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