From: "Navare, Manasi" <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 10/11] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
Date: Tue, 1 Dec 2020 14:59:05 -0800 [thread overview]
Message-ID: <20201201225905.GE22644@labuser-Z97X-UD5H> (raw)
In-Reply-To: <20201022222709.29386-11-manasi.d.navare@intel.com>
@Jani could you review this as well?
Manasi
On Thu, Oct 22, 2020 at 03:27:08PM -0700, Manasi Navare wrote:
> If VRR is enabled, the sink should ignore MSA parameters
> and regenerate incoming video stream without depending
> on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
> bit if VRR is enabled.
> Reset this bit on VRR disable.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 565155af3fb9..195449dfec1e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3322,6 +3322,22 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
> return DP_TP_STATUS(encoder->port);
> }
>
> +static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + bool enable)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + if (!crtc_state->vrr.enable)
> + return;
> +
> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> + enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
> + drm_dbg_kms(&i915->drm,
> + "Failed to set MSA_TIMING_PAR_IGNORE %s in the sink\n",
> + enable ? "enable" : "disable");
> +}
> +
> static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -3493,6 +3509,12 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> */
> intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
>
> + /*
> + * Sink device should ignore MSA parameters and regenerate
> + * incoming video stream in case of VRR/Adaptive Sync
> + */
> + intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, crtc_state, true);
> +
> /*
> * 7.i Follow DisplayPort specification training sequence (see notes for
> * failure handling)
> @@ -4089,6 +4111,9 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state,
> /* Disable the decompression in DP Sink */
> intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
> false);
> + /* Disable Ignore_MSA bit in DP Sink */
> + intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
> + false);
> }
>
> static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
> --
> 2.19.1
>
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next prev parent reply other threads:[~2020-12-01 22:56 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-22 22:26 [Intel-gfx] [PATCH 00/11] VRR/Adaptive Sync enabling in i915 Manasi Navare
2020-10-22 22:26 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add REG_FIELD_PREP to VRR register def Manasi Navare
2020-11-10 10:13 ` Jani Nikula
2020-12-01 22:41 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 02/11] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2020-11-10 10:39 ` Jani Nikula
2020-12-01 22:21 ` Navare, Manasi
2020-12-02 22:40 ` Navare, Manasi
2020-12-03 16:35 ` Jani Nikula
2020-12-03 19:38 ` Navare, Manasi
2020-11-10 16:06 ` Ville Syrjälä
2020-11-10 18:48 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 03/11] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2020-11-10 10:41 ` Jani Nikula
2020-12-01 22:46 ` Navare, Manasi
2020-12-03 16:37 ` Jani Nikula
2020-12-03 19:37 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 04/11] drm/i915/display/dp: Add VRR crtc state variables Manasi Navare
2020-11-10 10:41 ` Jani Nikula
2020-12-01 22:49 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 05/11] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2020-11-10 10:47 ` Jani Nikula
2020-12-01 22:52 ` Navare, Manasi
2020-12-02 22:38 ` Navare, Manasi
2020-12-03 16:39 ` Jani Nikula
2020-12-03 19:36 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 06/11] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2020-10-22 22:27 ` [Intel-gfx] [PATCH 07/11] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2020-11-10 10:56 ` Jani Nikula
2020-12-01 22:56 ` Navare, Manasi
2020-12-03 16:40 ` Jani Nikula
2020-10-22 22:27 ` [Intel-gfx] [PATCH 08/11] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2020-11-10 10:59 ` Jani Nikula
2020-12-01 22:57 ` Navare, Manasi
2020-12-03 19:58 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 09/11] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2020-11-10 11:01 ` Jani Nikula
2020-12-01 22:34 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 10/11] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2020-12-01 22:59 ` Navare, Manasi [this message]
2020-12-03 16:49 ` Jani Nikula
2020-12-03 19:33 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 11/11] drm/i915/display: Add HW state readout for VRR Manasi Navare
2020-10-23 17:42 ` [Intel-gfx] [PATCH v2 " Manasi Navare
2020-10-22 22:37 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for VRR/Adaptive Sync enabling in i915 Patchwork
2020-10-23 17:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync enabling in i915 (rev2) Patchwork
2020-10-23 17:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-23 18:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-23 21:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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