From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source()
Date: Fri, 14 May 2021 20:10:28 -0700 [thread overview]
Message-ID: <20210515031035.2561658-17-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210515031035.2561658-1-matthew.d.roper@intel.com>
From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
It removes intel_crtc_state from function argument of
intel_psr_enable_source() in order to use intel_psr_enable_source()
without intel_crtc_state on other psr internal functions.
And we can get cpu_trancoder from intel_psr, therefore we don't need to
pass intel_crtc_state to this function.
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5bafd0de6ad9..cc85083dcd28 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -969,11 +969,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
intel_dp->psr.active = true;
}
-static void intel_psr_enable_source(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+static void intel_psr_enable_source(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
u32 mask;
/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
@@ -1080,7 +1079,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
&intel_dp->psr.vsc);
intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
intel_psr_enable_sink(intel_dp);
- intel_psr_enable_source(intel_dp, crtc_state);
+ intel_psr_enable_source(intel_dp);
intel_dp->psr.enabled = true;
intel_psr_activate(intel_dp);
--
2.25.4
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next prev parent reply other threads:[~2021-05-15 3:11 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-15 3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-05-17 6:52 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-05-17 15:18 ` Jani Nikula
2021-05-18 6:33 ` Kulkarni, Vandita
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 03/23] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-05-18 18:06 ` Navare, Manasi
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 04/23] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 05/23] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-05-24 13:40 ` Aditya Swarup
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 06/23] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-05-17 6:49 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 07/23] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-05-17 18:01 ` Imre Deak
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold Matt Roper
2021-05-17 14:53 ` Imre Deak
2021-05-17 23:15 ` Souza, Jose
2021-05-17 23:22 ` Souza, Jose
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 09/23] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-05-17 15:12 ` Imre Deak
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 10/23] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-05-18 11:58 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 11/23] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-05-18 12:22 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 12/23] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-05-17 6:38 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 13/23] drm/i915/adl_p: MBUS programming Matt Roper
2023-07-17 10:32 ` Tvrtko Ursulin
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-05-17 7:36 ` Kulkarni, Vandita
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Matt Roper
2021-05-17 6:39 ` Gupta, Anshuman
2021-05-15 3:10 ` Matt Roper [this message]
2021-05-19 6:49 ` [Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() Anshuman Gupta
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 17/23] drm/i915/display: Add PSR interrupt error check function Matt Roper
2021-05-17 17:03 ` Souza, Jose
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function Matt Roper
2021-05-17 16:58 ` Souza, Jose
2021-05-18 9:33 ` Mun, Gwan-gyeong
2021-05-18 11:06 ` Ville Syrjälä
2021-05-21 10:58 ` Mun, Gwan-gyeong
2021-05-21 21:52 ` Souza, Jose
2021-06-01 10:23 ` Mun, Gwan-gyeong
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-05-17 23:02 ` Clint Taylor
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support Matt Roper
2021-05-17 21:55 ` Clint Taylor
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 21/23] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Matt Roper
2021-05-17 17:01 ` Souza, Jose
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-05-17 21:46 ` Clint Taylor
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 23/23] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-05-17 17:02 ` Souza, Jose
2021-05-15 4:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev3) Patchwork
2021-05-15 4:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-15 5:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-17 23:41 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Alder Lake-P Support (rev4) Patchwork
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