From: Clint Taylor <Clinton.A.Taylor@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables
Date: Mon, 17 May 2021 16:02:01 -0700 [thread overview]
Message-ID: <6d7ed19a-30ec-bbed-7848-ec4b5e3e9708@intel.com> (raw)
In-Reply-To: <20210515031035.2561658-20-matthew.d.roper@intel.com>
Values match current BSPEC.
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
-Clint
On 5/14/21 8:10 PM, Matt Roper wrote:
> From: Mika Kahola <mika.kahola@intel.com>
>
> Define and use DP voltage swing and pre-emphasis translation tables
> for ADL-P.
>
> v2:
> - Update according to recent bspec updates; there are now separate
> tables for RBR/HBR and HBR2/HBR3. (Anusha)
>
> BSpec: 54956
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++-
> .../drm/i915/display/intel_ddi_buf_trans.c | 53 +++++++++++++++++++
> .../drm/i915/display/intel_ddi_buf_trans.h | 4 ++
> 3 files changed, 63 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 38a4f251b9c9..e0adb14ecd0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -985,6 +985,8 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
> if (DISPLAY_VER(dev_priv) >= 12) {
> if (intel_phy_is_combo(dev_priv, phy))
> tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> + else if (IS_ALDERLAKE_P(dev_priv))
> + adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
> else
> tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
> } else if (DISPLAY_VER(dev_priv) == 11) {
> @@ -1431,7 +1433,10 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
> return;
>
> - ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
> + if (IS_ALDERLAKE_P(dev_priv))
> + ddi_translations = adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
> + else
> + ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> return;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 7bcdd5c12028..b6388d93c3ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -735,6 +735,34 @@ static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr
> { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> +static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr[] = {
> + /* VS pre-emp Non-trans mV Pre-emph dB */
> + { 0x7, 0x0, 0x01 }, /* 0 0 400mV 0 dB */
> + { 0x5, 0x0, 0x06 }, /* 0 1 400mV 3.5 dB */
> + { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
> + { 0x0, 0x0, 0x17 }, /* 0 3 400mV 9.5 dB */
> + { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
> + { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
> + { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
> + { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
> + { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
> + { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB */
> +};
> +
> +static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3[] = {
> + /* VS pre-emp Non-trans mV Pre-emph dB */
> + { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
> + { 0x5, 0x0, 0x04 }, /* 0 1 400mV 3.5 dB */
> + { 0x2, 0x0, 0x0A }, /* 0 2 400mV 6 dB */
> + { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */
> + { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
> + { 0x2, 0x0, 0x06 }, /* 1 1 600mV 3.5 dB */
> + { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
> + { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
> + { 0x0, 0x0, 0x09 }, /* 2 1 800mV 3.5 dB */
> + { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB */
> +};
> +
> bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
> {
> return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> @@ -1348,6 +1376,31 @@ tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
> return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
> }
>
> +static const struct tgl_dkl_phy_ddi_buf_trans *
> +adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + if (crtc_state->port_clock > 270000) {
> + *n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3);
> + return adlp_dkl_phy_dp_ddi_trans_hbr;
> + } else {
> + *n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr);
> + return adlp_dkl_phy_dp_ddi_trans_hbr;
> + }
> +}
> +
> +const struct tgl_dkl_phy_ddi_buf_trans *
> +adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
> + else
> + return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
> +}
> +
> int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> int *default_entry)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> index f8f0ef87e977..4c2efab38642 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> @@ -67,6 +67,10 @@ bxt_get_buf_trans(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> int *n_entries);
>
> +const struct tgl_dkl_phy_ddi_buf_trans *
> +adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries);
> const struct cnl_ddi_buf_trans *
> tgl_get_combo_buf_trans(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
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next prev parent reply other threads:[~2021-05-17 23:02 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-15 3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-05-17 6:52 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-05-17 15:18 ` Jani Nikula
2021-05-18 6:33 ` Kulkarni, Vandita
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 03/23] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-05-18 18:06 ` Navare, Manasi
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 04/23] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 05/23] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-05-24 13:40 ` Aditya Swarup
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 06/23] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-05-17 6:49 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 07/23] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-05-17 18:01 ` Imre Deak
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold Matt Roper
2021-05-17 14:53 ` Imre Deak
2021-05-17 23:15 ` Souza, Jose
2021-05-17 23:22 ` Souza, Jose
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 09/23] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-05-17 15:12 ` Imre Deak
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 10/23] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-05-18 11:58 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 11/23] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-05-18 12:22 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 12/23] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-05-17 6:38 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 13/23] drm/i915/adl_p: MBUS programming Matt Roper
2023-07-17 10:32 ` Tvrtko Ursulin
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-05-17 7:36 ` Kulkarni, Vandita
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Matt Roper
2021-05-17 6:39 ` Gupta, Anshuman
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() Matt Roper
2021-05-19 6:49 ` Anshuman Gupta
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 17/23] drm/i915/display: Add PSR interrupt error check function Matt Roper
2021-05-17 17:03 ` Souza, Jose
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function Matt Roper
2021-05-17 16:58 ` Souza, Jose
2021-05-18 9:33 ` Mun, Gwan-gyeong
2021-05-18 11:06 ` Ville Syrjälä
2021-05-21 10:58 ` Mun, Gwan-gyeong
2021-05-21 21:52 ` Souza, Jose
2021-06-01 10:23 ` Mun, Gwan-gyeong
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-05-17 23:02 ` Clint Taylor [this message]
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support Matt Roper
2021-05-17 21:55 ` Clint Taylor
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 21/23] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Matt Roper
2021-05-17 17:01 ` Souza, Jose
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-05-17 21:46 ` Clint Taylor
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 23/23] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-05-17 17:02 ` Souza, Jose
2021-05-15 4:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev3) Patchwork
2021-05-15 4:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-15 5:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-17 23:41 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Alder Lake-P Support (rev4) Patchwork
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