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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 11/13] drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll()
Date: Thu, 15 Jul 2021 12:35:28 +0300	[thread overview]
Message-ID: <20210715093530.31711-12-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210715093530.31711-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Can't think of a good reason why we'd need to program the FP
dividers so early. Let's just do it when programming the rest
of the DPLL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 -------------
 drivers/gpu/drm/i915/display/intel_dpll.c    |  3 +++
 2 files changed, 3 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5bc1e32b2ba..f54cb0521f6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3956,17 +3956,6 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 	intel_encoders_enable(state, crtc);
 }
 
-static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
-	intel_de_write(dev_priv, FP0(crtc->pipe),
-		       crtc_state->dpll_hw_state.fp0);
-	intel_de_write(dev_priv, FP1(crtc->pipe),
-		       crtc_state->dpll_hw_state.fp1);
-}
-
 static void i9xx_crtc_enable(struct intel_atomic_state *state,
 			     struct intel_crtc *crtc)
 {
@@ -3978,8 +3967,6 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
 		return;
 
-	i9xx_set_pll_dividers(new_crtc_state);
-
 	if (intel_crtc_has_dp_encoder(new_crtc_state))
 		intel_dp_set_m_n(new_crtc_state, M1_N1);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 543890050040..1776c47aa2ba 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1404,6 +1404,9 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
 	if (i9xx_has_pps(dev_priv))
 		assert_panel_unlocked(dev_priv, pipe);
 
+	intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);
+	intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);
+
 	/*
 	 * Apparently we need to have VGA mode enabled prior to changing
 	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
-- 
2.31.1

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  parent reply	other threads:[~2021-07-15  9:36 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-15  9:35 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL stuff Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 01/13] drm/i915: Set output_types to EDP for vlv/chv DPLL forcing Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 02/13] drm/i915: Clean up gen2 DPLL readout Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 03/13] drm/i915: Extract ilk_update_pll_dividers() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 04/13] drm/i915: Constify struct dpll all over Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 05/13] drm/i915: Clean dpll calling convention Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 06/13] drm/i915: Clean up variable names in old dpll functions Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 07/13] drm/i915: Remove the 'reg' local variable Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 08/13] drm/i915: Program DPLL P1 dividers consistently Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 09/13] drm/i915: Call {vlv, chv}_prepare_pll() from {vlv, chv}_enable_pll() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 10/13] drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as well Ville Syrjala
2021-07-15  9:35 ` Ville Syrjala [this message]
2021-07-15  9:35 ` [Intel-gfx] [PATCH 12/13] drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 13/13] drm/i915: Nuke intel_prepare_shared_dpll() Ville Syrjala
2021-07-16 18:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL stuff Patchwork
2021-07-16 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-17  0:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-08-25  8:53 ` [Intel-gfx] [PATCH 00/13] " Jani Nikula

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