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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 08/13] drm/i915: Program DPLL P1 dividers consistently
Date: Thu, 15 Jul 2021 12:35:25 +0300	[thread overview]
Message-ID: <20210715093530.31711-9-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210715093530.31711-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On g4x and pch the DPLL has two P1 dividers (for refresh rate
switching). Program the FPx1 P1 divider consistently to the reduced
clock P1 divider if available, otherwise just program it to the
same value as the FPx0 P1 divider.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 80 ++++++++++++-----------
 1 file changed, 41 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 2f6903ec0a9f..0df9daf4dbf2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -778,42 +778,34 @@ static u32 pnv_dpll_compute_fp(const struct dpll *dpll)
 }
 
 static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state,
+				     const struct dpll *clock,
 				     const struct dpll *reduced_clock)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct dpll *clock = &crtc_state->dpll;
-	u32 fp, fp2 = 0;
+	u32 fp, fp2;
 
 	if (IS_PINEVIEW(dev_priv)) {
 		fp = pnv_dpll_compute_fp(clock);
-		if (reduced_clock)
-			fp2 = pnv_dpll_compute_fp(reduced_clock);
+		fp2 = pnv_dpll_compute_fp(reduced_clock);
 	} else {
 		fp = i9xx_dpll_compute_fp(clock);
-		if (reduced_clock)
-			fp2 = i9xx_dpll_compute_fp(reduced_clock);
+		fp2 = i9xx_dpll_compute_fp(reduced_clock);
 	}
 
 	crtc_state->dpll_hw_state.fp0 = fp;
-
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
-	    reduced_clock) {
-		crtc_state->dpll_hw_state.fp1 = fp2;
-	} else {
-		crtc_state->dpll_hw_state.fp1 = fp;
-	}
+	crtc_state->dpll_hw_state.fp1 = fp2;
 }
 
 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
+			      const struct dpll *clock,
 			      const struct dpll *reduced_clock)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct dpll *clock = &crtc_state->dpll;
 	u32 dpll;
 
-	i9xx_update_pll_dividers(crtc_state, reduced_clock);
+	i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
 
 	dpll = DPLL_VGA_MODE_DIS;
 
@@ -836,13 +828,17 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
 		dpll |= DPLL_SDVO_HIGH_SPEED;
 
 	/* compute bitmask from p1 value */
-	if (IS_PINEVIEW(dev_priv))
+	if (IS_G4X(dev_priv)) {
+		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+		dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+	} else if (IS_PINEVIEW(dev_priv)) {
 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
-	else {
+		WARN_ON(reduced_clock->p1 != clock->p1);
+	} else {
 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-		if (IS_G4X(dev_priv) && reduced_clock)
-			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+		WARN_ON(reduced_clock->p1 != clock->p1);
 	}
+
 	switch (clock->p2) {
 	case 5:
 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
@@ -857,6 +853,8 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 		break;
 	}
+	WARN_ON(reduced_clock->p2 != clock->p2);
+
 	if (DISPLAY_VER(dev_priv) >= 4)
 		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
 
@@ -879,14 +877,14 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
 }
 
 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
+			      const struct dpll *clock,
 			      const struct dpll *reduced_clock)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct dpll *clock = &crtc_state->dpll;
 	u32 dpll;
 
-	i9xx_update_pll_dividers(crtc_state, reduced_clock);
+	i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
 
 	dpll = DPLL_VGA_MODE_DIS;
 
@@ -900,6 +898,8 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
 		if (clock->p2 == 4)
 			dpll |= PLL_P2_DIVIDE_BY_4;
 	}
+	WARN_ON(reduced_clock->p1 != clock->p1);
+	WARN_ON(reduced_clock->p2 != clock->p2);
 
 	/*
 	 * Bspec:
@@ -956,12 +956,12 @@ static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
 }
 
 static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
+				    const struct dpll *clock,
 				    const struct dpll *reduced_clock)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct dpll *clock = &crtc_state->dpll;
-	u32 fp, fp2 = 0;
+	u32 fp, fp2;
 	int factor;
 
 	/* Enable autotuning of the PLL clock (if permissible) */
@@ -977,30 +977,26 @@ static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
 	}
 
 	fp = i9xx_dpll_compute_fp(clock);
-
 	if (ilk_needs_fb_cb_tune(clock, factor))
 		fp |= FP_CB_TUNE;
 
-	if (reduced_clock) {
-		fp2 = i9xx_dpll_compute_fp(reduced_clock);
-
-		if (reduced_clock->m < factor * reduced_clock->n)
-			fp2 |= FP_CB_TUNE;
-	}
+	fp2 = i9xx_dpll_compute_fp(reduced_clock);
+	if (reduced_clock->m < factor * reduced_clock->n)
+		fp2 |= FP_CB_TUNE;
 
 	crtc_state->dpll_hw_state.fp0 = fp;
-	crtc_state->dpll_hw_state.fp1 = reduced_clock ? fp2 : fp;
+	crtc_state->dpll_hw_state.fp1 = fp2;
 }
 
 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
+			     const struct dpll *clock,
 			     const struct dpll *reduced_clock)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct dpll *clock = &crtc_state->dpll;
 	u32 dpll;
 
-	ilk_update_pll_dividers(crtc_state, reduced_clock);
+	ilk_update_pll_dividers(crtc_state, clock, reduced_clock);
 
 	dpll = 0;
 
@@ -1040,7 +1036,7 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
 	/* compute bitmask from p1 value */
 	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 	/* also FPA1 */
-	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+	dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 
 	switch (clock->p2) {
 	case 5:
@@ -1056,6 +1052,7 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 		break;
 	}
+	WARN_ON(reduced_clock->p2 != clock->p2);
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 	    intel_panel_use_ssc(dev_priv))
@@ -1115,7 +1112,8 @@ static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state)
 		return -EINVAL;
 	}
 
-	ilk_compute_dpll(crtc_state, NULL);
+	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
+			 &crtc_state->dpll);
 
 	if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
 		drm_dbg_kms(&dev_priv->drm,
@@ -1244,7 +1242,8 @@ static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state)
 		return -EINVAL;
 	}
 
-	i9xx_compute_dpll(crtc_state, NULL);
+	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
+			  &crtc_state->dpll);
 
 	return 0;
 }
@@ -1280,7 +1279,8 @@ static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
 		return -EINVAL;
 	}
 
-	i9xx_compute_dpll(crtc_state, NULL);
+	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
+			  &crtc_state->dpll);
 
 	return 0;
 }
@@ -1316,7 +1316,8 @@ static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
 		return -EINVAL;
 	}
 
-	i9xx_compute_dpll(crtc_state, NULL);
+	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
+			  &crtc_state->dpll);
 
 	return 0;
 }
@@ -1354,7 +1355,8 @@ static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
 		return -EINVAL;
 	}
 
-	i8xx_compute_dpll(crtc_state, NULL);
+	i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
+			  &crtc_state->dpll);
 
 	return 0;
 }
-- 
2.31.1

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  parent reply	other threads:[~2021-07-15  9:35 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-15  9:35 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL stuff Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 01/13] drm/i915: Set output_types to EDP for vlv/chv DPLL forcing Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 02/13] drm/i915: Clean up gen2 DPLL readout Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 03/13] drm/i915: Extract ilk_update_pll_dividers() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 04/13] drm/i915: Constify struct dpll all over Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 05/13] drm/i915: Clean dpll calling convention Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 06/13] drm/i915: Clean up variable names in old dpll functions Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 07/13] drm/i915: Remove the 'reg' local variable Ville Syrjala
2021-07-15  9:35 ` Ville Syrjala [this message]
2021-07-15  9:35 ` [Intel-gfx] [PATCH 09/13] drm/i915: Call {vlv, chv}_prepare_pll() from {vlv, chv}_enable_pll() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 10/13] drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as well Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 11/13] drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 12/13] drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 13/13] drm/i915: Nuke intel_prepare_shared_dpll() Ville Syrjala
2021-07-16 18:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL stuff Patchwork
2021-07-16 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-17  0:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-08-25  8:53 ` [Intel-gfx] [PATCH 00/13] " Jani Nikula

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