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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 04/13] drm/i915: Constify struct dpll all over
Date: Thu, 15 Jul 2021 12:35:21 +0300	[thread overview]
Message-ID: <20210715093530.31711-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210715093530.31711-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Lots of places don't need to modify the DPLL params, so make
them const.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  5 --
 drivers/gpu/drm/i915/display/intel_dpll.c     | 58 +++++++++++--------
 drivers/gpu/drm/i915/display/intel_dpll.h     |  1 +
 3 files changed, 36 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d94f361b548b..404122cfd66c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2023,11 +2023,6 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
 		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
 }
 
-static inline u32 i9xx_dpll_compute_fp(struct dpll *dpll)
-{
-	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
-}
-
 static inline u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 				      const struct intel_crtc_state *pipe_config)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index b98ef810591b..13ed2711b97a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -308,7 +308,7 @@ int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 	return clock->dot;
 }
 
-static u32 i9xx_dpll_compute_m(struct dpll *dpll)
+static u32 i9xx_dpll_compute_m(const struct dpll *dpll)
 {
 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 }
@@ -427,7 +427,8 @@ i9xx_select_p2_div(const struct intel_limit *limit,
 static bool
 i9xx_find_best_dpll(const struct intel_limit *limit,
 		    struct intel_crtc_state *crtc_state,
-		    int target, int refclk, struct dpll *match_clock,
+		    int target, int refclk,
+		    const struct dpll *match_clock,
 		    struct dpll *best_clock)
 {
 	struct drm_device *dev = crtc_state->uapi.crtc->dev;
@@ -485,7 +486,8 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
 static bool
 pnv_find_best_dpll(const struct intel_limit *limit,
 		   struct intel_crtc_state *crtc_state,
-		   int target, int refclk, struct dpll *match_clock,
+		   int target, int refclk,
+		   const struct dpll *match_clock,
 		   struct dpll *best_clock)
 {
 	struct drm_device *dev = crtc_state->uapi.crtc->dev;
@@ -541,7 +543,8 @@ pnv_find_best_dpll(const struct intel_limit *limit,
 static bool
 g4x_find_best_dpll(const struct intel_limit *limit,
 		   struct intel_crtc_state *crtc_state,
-		   int target, int refclk, struct dpll *match_clock,
+		   int target, int refclk,
+		   const struct dpll *match_clock,
 		   struct dpll *best_clock)
 {
 	struct drm_device *dev = crtc_state->uapi.crtc->dev;
@@ -635,7 +638,8 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 static bool
 vlv_find_best_dpll(const struct intel_limit *limit,
 		   struct intel_crtc_state *crtc_state,
-		   int target, int refclk, struct dpll *match_clock,
+		   int target, int refclk,
+		   const struct dpll *match_clock,
 		   struct dpll *best_clock)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -695,7 +699,8 @@ vlv_find_best_dpll(const struct intel_limit *limit,
 static bool
 chv_find_best_dpll(const struct intel_limit *limit,
 		   struct intel_crtc_state *crtc_state,
-		   int target, int refclk, struct dpll *match_clock,
+		   int target, int refclk,
+		   const struct dpll *match_clock,
 		   struct dpll *best_clock)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -762,24 +767,30 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 				  NULL, best_clock);
 }
 
-static u32 pnv_dpll_compute_fp(struct dpll *dpll)
+u32 i9xx_dpll_compute_fp(const struct dpll *dpll)
+{
+	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
+}
+
+static u32 pnv_dpll_compute_fp(const struct dpll *dpll)
 {
 	return (1 << dpll->n) << 16 | dpll->m2;
 }
 
 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
 				     struct intel_crtc_state *crtc_state,
-				     struct dpll *reduced_clock)
+				     const struct dpll *reduced_clock)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct dpll *clock = &crtc_state->dpll;
 	u32 fp, fp2 = 0;
 
 	if (IS_PINEVIEW(dev_priv)) {
-		fp = pnv_dpll_compute_fp(&crtc_state->dpll);
+		fp = pnv_dpll_compute_fp(clock);
 		if (reduced_clock)
 			fp2 = pnv_dpll_compute_fp(reduced_clock);
 	} else {
-		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
+		fp = i9xx_dpll_compute_fp(clock);
 		if (reduced_clock)
 			fp2 = i9xx_dpll_compute_fp(reduced_clock);
 	}
@@ -796,11 +807,11 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
 
 static void i9xx_compute_dpll(struct intel_crtc *crtc,
 			      struct intel_crtc_state *crtc_state,
-			      struct dpll *reduced_clock)
+			      const struct dpll *reduced_clock)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct dpll *clock = &crtc_state->dpll;
 	u32 dpll;
-	struct dpll *clock = &crtc_state->dpll;
 
 	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
 
@@ -869,12 +880,12 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
 
 static void i8xx_compute_dpll(struct intel_crtc *crtc,
 			      struct intel_crtc_state *crtc_state,
-			      struct dpll *reduced_clock)
+			      const struct dpll *reduced_clock)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	const struct dpll *clock = &crtc_state->dpll;
 	u32 dpll;
-	struct dpll *clock = &crtc_state->dpll;
 
 	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
 
@@ -940,17 +951,17 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
 	return 0;
 }
 
-static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
+static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
 {
 	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
 }
 
-
 static void ilk_update_pll_dividers(struct intel_crtc *crtc,
 				    struct intel_crtc_state *crtc_state,
-				    struct dpll *reduced_clock)
+				    const struct dpll *reduced_clock)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct dpll *clock = &crtc_state->dpll;
 	u32 fp, fp2 = 0;
 	int factor;
 
@@ -966,9 +977,9 @@ static void ilk_update_pll_dividers(struct intel_crtc *crtc,
 		factor = 20;
 	}
 
-	fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
+	fp = i9xx_dpll_compute_fp(clock);
 
-	if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
+	if (ilk_needs_fb_cb_tune(clock, factor))
 		fp |= FP_CB_TUNE;
 
 	if (reduced_clock) {
@@ -984,9 +995,10 @@ static void ilk_update_pll_dividers(struct intel_crtc *crtc,
 
 static void ilk_compute_dpll(struct intel_crtc *crtc,
 			     struct intel_crtc_state *crtc_state,
-			     struct dpll *reduced_clock)
+			     const struct dpll *reduced_clock)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct dpll *clock = &crtc_state->dpll;
 	u32 dpll;
 
 	ilk_update_pll_dividers(crtc, crtc_state, reduced_clock);
@@ -1027,11 +1039,11 @@ static void ilk_compute_dpll(struct intel_crtc *crtc,
 		dpll |= DPLL_SDVO_HIGH_SPEED;
 
 	/* compute bitmask from p1 value */
-	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 	/* also FPA1 */
-	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 
-	switch (crtc_state->dpll.p2) {
+	switch (clock->p2) {
 	case 5:
 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index 88247027fd5a..e2f845902abf 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -18,6 +18,7 @@ void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
+u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
 void vlv_compute_dpll(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
 void chv_compute_dpll(struct intel_crtc *crtc,
-- 
2.31.1

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  parent reply	other threads:[~2021-07-15  9:35 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-15  9:35 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL stuff Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 01/13] drm/i915: Set output_types to EDP for vlv/chv DPLL forcing Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 02/13] drm/i915: Clean up gen2 DPLL readout Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 03/13] drm/i915: Extract ilk_update_pll_dividers() Ville Syrjala
2021-07-15  9:35 ` Ville Syrjala [this message]
2021-07-15  9:35 ` [Intel-gfx] [PATCH 05/13] drm/i915: Clean dpll calling convention Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 06/13] drm/i915: Clean up variable names in old dpll functions Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 07/13] drm/i915: Remove the 'reg' local variable Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 08/13] drm/i915: Program DPLL P1 dividers consistently Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 09/13] drm/i915: Call {vlv, chv}_prepare_pll() from {vlv, chv}_enable_pll() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 10/13] drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as well Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 11/13] drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 12/13] drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 13/13] drm/i915: Nuke intel_prepare_shared_dpll() Ville Syrjala
2021-07-16 18:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL stuff Patchwork
2021-07-16 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-17  0:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-08-25  8:53 ` [Intel-gfx] [PATCH 00/13] " Jani Nikula

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