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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 07/13] drm/i915: Remove the 'reg' local variable
Date: Thu, 15 Jul 2021 12:35:24 +0300	[thread overview]
Message-ID: <20210715093530.31711-8-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210715093530.31711-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of the local 'reg' variable for the DPLL control register
in i9xx_enable_pll(). We have other registers in there too so this
is just making things more confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 10d5519626a4..2f6903ec0a9f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1392,30 +1392,30 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	i915_reg_t reg = DPLL(crtc->pipe);
 	u32 dpll = crtc_state->dpll_hw_state.dpll;
+	enum pipe pipe = crtc->pipe;
 	int i;
 
 	assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
 
 	/* PLL is protected by panel, make sure we can write it */
 	if (i9xx_has_pps(dev_priv))
-		assert_panel_unlocked(dev_priv, crtc->pipe);
+		assert_panel_unlocked(dev_priv, pipe);
 
 	/*
 	 * Apparently we need to have VGA mode enabled prior to changing
 	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
 	 * dividers, even though the register value does change.
 	 */
-	intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
-	intel_de_write(dev_priv, reg, dpll);
+	intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
+	intel_de_write(dev_priv, DPLL(pipe), dpll);
 
 	/* Wait for the clocks to stabilize. */
-	intel_de_posting_read(dev_priv, reg);
+	intel_de_posting_read(dev_priv, DPLL(pipe));
 	udelay(150);
 
 	if (DISPLAY_VER(dev_priv) >= 4) {
-		intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
+		intel_de_write(dev_priv, DPLL_MD(pipe),
 			       crtc_state->dpll_hw_state.dpll_md);
 	} else {
 		/* The pixel multiplier can only be updated once the
@@ -1423,13 +1423,13 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
 		 *
 		 * So write it again.
 		 */
-		intel_de_write(dev_priv, reg, dpll);
+		intel_de_write(dev_priv, DPLL(pipe), dpll);
 	}
 
 	/* We do this three times for luck */
 	for (i = 0; i < 3; i++) {
-		intel_de_write(dev_priv, reg, dpll);
-		intel_de_posting_read(dev_priv, reg);
+		intel_de_write(dev_priv, DPLL(pipe), dpll);
+		intel_de_posting_read(dev_priv, DPLL(pipe));
 		udelay(150); /* wait for warmup */
 	}
 }
-- 
2.31.1

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  parent reply	other threads:[~2021-07-15  9:35 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-15  9:35 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL stuff Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 01/13] drm/i915: Set output_types to EDP for vlv/chv DPLL forcing Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 02/13] drm/i915: Clean up gen2 DPLL readout Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 03/13] drm/i915: Extract ilk_update_pll_dividers() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 04/13] drm/i915: Constify struct dpll all over Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 05/13] drm/i915: Clean dpll calling convention Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 06/13] drm/i915: Clean up variable names in old dpll functions Ville Syrjala
2021-07-15  9:35 ` Ville Syrjala [this message]
2021-07-15  9:35 ` [Intel-gfx] [PATCH 08/13] drm/i915: Program DPLL P1 dividers consistently Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 09/13] drm/i915: Call {vlv, chv}_prepare_pll() from {vlv, chv}_enable_pll() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 10/13] drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as well Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 11/13] drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 12/13] drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable() Ville Syrjala
2021-07-15  9:35 ` [Intel-gfx] [PATCH 13/13] drm/i915: Nuke intel_prepare_shared_dpll() Ville Syrjala
2021-07-16 18:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL stuff Patchwork
2021-07-16 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-17  0:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-08-25  8:53 ` [Intel-gfx] [PATCH 00/13] " Jani Nikula

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