From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 13/13] drm/i915: Nuke intel_prepare_shared_dpll()
Date: Thu, 15 Jul 2021 12:35:30 +0300 [thread overview]
Message-ID: <20210715093530.31711-14-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210715093530.31711-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_prepare_shared_dpll() is now useless, so get rid of it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 --
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 28 -------------------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 11 --------
3 files changed, 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f54cb0521f6a..df95b2fd2a87 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3312,9 +3312,6 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- if (new_crtc_state->has_pch_encoder)
- intel_prepare_shared_dpll(new_crtc_state);
-
if (intel_crtc_has_dp_encoder(new_crtc_state))
intel_dp_set_m_n(new_crtc_state, M1_N1);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 041171dede85..539e048fa7c4 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -184,34 +184,6 @@ intel_tc_pll_enable_reg(struct drm_i915_private *i915,
return MG_PLL_ENABLE(tc_port);
}
-/**
- * intel_prepare_shared_dpll - call a dpll's prepare hook
- * @crtc_state: CRTC, and its state, which has a shared dpll
- *
- * This calls the PLL's prepare hook if it has one and if the PLL is not
- * already enabled. The prepare hook is platform specific.
- */
-void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
-
- if (drm_WARN_ON(&dev_priv->drm, pll == NULL))
- return;
-
- mutex_lock(&dev_priv->dpll.lock);
- drm_WARN_ON(&dev_priv->drm, !pll->state.pipe_mask);
- if (!pll->active_mask) {
- drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info->name);
- drm_WARN_ON(&dev_priv->drm, pll->on);
- assert_shared_dpll_disabled(dev_priv, pll);
-
- pll->info->funcs->prepare(dev_priv, pll);
- }
- mutex_unlock(&dev_priv->dpll.lock);
-}
-
/**
* intel_enable_shared_dpll - enable a CRTC's shared DPLL
* @crtc_state: CRTC, and its state, which has a shared DPLL
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 7fd031a70cfd..5a6a7b74d5f9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -256,16 +256,6 @@ struct intel_shared_dpll_state {
* struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
*/
struct intel_shared_dpll_funcs {
- /**
- * @prepare:
- *
- * Optional hook to perform operations prior to enabling the PLL.
- * Called from intel_prepare_shared_dpll() function unless the PLL
- * is already enabled.
- */
- void (*prepare)(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll);
-
/**
* @enable:
*
@@ -405,7 +395,6 @@ int intel_dpll_get_freq(struct drm_i915_private *i915,
bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state);
-void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
--
2.31.1
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next prev parent reply other threads:[~2021-07-15 9:36 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 9:35 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL stuff Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 01/13] drm/i915: Set output_types to EDP for vlv/chv DPLL forcing Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 02/13] drm/i915: Clean up gen2 DPLL readout Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 03/13] drm/i915: Extract ilk_update_pll_dividers() Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 04/13] drm/i915: Constify struct dpll all over Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 05/13] drm/i915: Clean dpll calling convention Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 06/13] drm/i915: Clean up variable names in old dpll functions Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 07/13] drm/i915: Remove the 'reg' local variable Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 08/13] drm/i915: Program DPLL P1 dividers consistently Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 09/13] drm/i915: Call {vlv, chv}_prepare_pll() from {vlv, chv}_enable_pll() Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 10/13] drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as well Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 11/13] drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll() Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 12/13] drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable() Ville Syrjala
2021-07-15 9:35 ` Ville Syrjala [this message]
2021-07-16 18:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL stuff Patchwork
2021-07-16 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-17 0:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-08-25 8:53 ` [Intel-gfx] [PATCH 00/13] " Jani Nikula
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