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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 10/11] drm/i915: Populate bxt/glk DPLL clock limits a bit more
Date: Tue,  1 Mar 2022 19:31:27 +0200	[thread overview]
Message-ID: <20220301173128.6988-11-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220301173128.6988-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Set the bxt/glk DPLL min dotclock to 25MHz (HDMI minimum)
and the max to 594 MHz (HDMI max). The supported DP frequencies
(162MHz-540MHz) fit within the same range.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 693e07a6db80..fee3e2e3a4b7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -284,8 +284,7 @@ static const struct intel_limit intel_limits_chv = {
 };
 
 static const struct intel_limit intel_limits_bxt = {
-	/* FIXME: find real dot limits */
-	.dot = { .min = 0, .max = INT_MAX },
+	.dot = { .min = 25000, .max = 594000 },
 	.vco = { .min = 4800000, .max = 6700000 },
 	.n = { .min = 1, .max = 1 },
 	.m1 = { .min = 2, .max = 2 },
-- 
2.34.1


  parent reply	other threads:[~2022-03-01 17:32 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-01 17:31 [Intel-gfx] [PATCH 00/11] drm/i915: Clean up some dpll stuff Ville Syrjala
2022-03-01 17:31 ` [Intel-gfx] [PATCH 01/11] drm/i915: Nuke skl_wrpll_context_init() Ville Syrjala
2022-03-04 11:10   ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 02/11] drm/i915: Move a bunch of stuff into rodata from the stack Ville Syrjala
2022-03-04 11:13   ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 03/11] drm/i915: Clean up some struct/array initializers Ville Syrjala
2022-03-04 11:14   ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 04/11] drm/i915: Store the /5 target clock in sturct dpll on vlv/chv Ville Syrjala
2022-03-01 17:31 ` [Intel-gfx] [PATCH 05/11] drm/i915: Remove bxt m2_frac_en Ville Syrjala
2022-03-04 11:19   ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 06/11] drm/i915: Use designated initializers for bxt_dp_clk_val[] Ville Syrjala
2022-03-04 11:20   ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 07/11] drm/i915: Store the m2 divider as a whole in bxt_clk_div Ville Syrjala
2022-03-04 11:36   ` Jani Nikula
2022-03-07 18:02     ` Ville Syrjälä
2022-03-01 17:31 ` [Intel-gfx] [PATCH 08/11] drm/i915: Replace bxt_clk_div with struct dpll Ville Syrjala
2022-03-04 11:41   ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 09/11] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params() Ville Syrjala
2022-03-01 17:44   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-03-01 17:31 ` Ville Syrjala [this message]
2022-03-01 17:31 ` [Intel-gfx] [PATCH 11/11] drm/i915: Remove struct dp_link_dpll Ville Syrjala
2022-03-01 23:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clean up some dpll stuff (rev2) Patchwork
2022-03-02  3:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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