From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 03/11] drm/i915: Clean up some struct/array initializers
Date: Fri, 04 Mar 2022 13:14:47 +0200 [thread overview]
Message-ID: <871qzi3r6g.fsf@intel.com> (raw)
In-Reply-To: <20220301173128.6988-4-ville.syrjala@linux.intel.com>
On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use the simple '= {}' form to initialize empty arrays/structs.
> Also add some missing whitespace.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 4e06c8203aca..bc26ebacae12 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -832,7 +832,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
> {
> u64 freq2k;
> unsigned p, n2, r2;
> - struct hsw_wrpll_rnp best = { 0, 0, 0 };
> + struct hsw_wrpll_rnp best = {};
> unsigned budget;
>
> freq2k = clock / 100;
> @@ -1567,8 +1567,8 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
> static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + struct skl_wrpll_params wrpll_params = {};
> u32 ctrl1, cfgcr1, cfgcr2;
> - struct skl_wrpll_params wrpll_params = { 0, };
>
> /*
> * See comment in intel_dpll_hw_state to understand why we always use 0
> @@ -2095,13 +2095,13 @@ struct bxt_clk_div {
>
> /* pre-calculated values for DP linkrates */
> static const struct bxt_clk_div bxt_dp_clk_val[] = {
> - {162000, 4, 2, 32, 1677722, 1, 1},
> - {270000, 4, 1, 27, 0, 0, 1},
> - {540000, 2, 1, 27, 0, 0, 1},
> - {216000, 3, 2, 32, 1677722, 1, 1},
> - {243000, 4, 1, 24, 1258291, 1, 1},
> - {324000, 4, 1, 32, 1677722, 1, 1},
> - {432000, 3, 1, 32, 1677722, 1, 1}
> + { 162000, 4, 2, 32, 1677722, 1, 1 },
> + { 270000, 4, 1, 27, 0, 0, 1 },
> + { 540000, 2, 1, 27, 0, 0, 1 },
> + { 216000, 3, 2, 32, 1677722, 1, 1 },
> + { 243000, 4, 1, 24, 1258291, 1, 1 },
> + { 324000, 4, 1, 32, 1677722, 1, 1 },
> + { 432000, 3, 1, 32, 1677722, 1, 1 }
> };
>
> static bool
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2022-03-04 11:14 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-01 17:31 [Intel-gfx] [PATCH 00/11] drm/i915: Clean up some dpll stuff Ville Syrjala
2022-03-01 17:31 ` [Intel-gfx] [PATCH 01/11] drm/i915: Nuke skl_wrpll_context_init() Ville Syrjala
2022-03-04 11:10 ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 02/11] drm/i915: Move a bunch of stuff into rodata from the stack Ville Syrjala
2022-03-04 11:13 ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 03/11] drm/i915: Clean up some struct/array initializers Ville Syrjala
2022-03-04 11:14 ` Jani Nikula [this message]
2022-03-01 17:31 ` [Intel-gfx] [PATCH 04/11] drm/i915: Store the /5 target clock in sturct dpll on vlv/chv Ville Syrjala
2022-03-01 17:31 ` [Intel-gfx] [PATCH 05/11] drm/i915: Remove bxt m2_frac_en Ville Syrjala
2022-03-04 11:19 ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 06/11] drm/i915: Use designated initializers for bxt_dp_clk_val[] Ville Syrjala
2022-03-04 11:20 ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 07/11] drm/i915: Store the m2 divider as a whole in bxt_clk_div Ville Syrjala
2022-03-04 11:36 ` Jani Nikula
2022-03-07 18:02 ` Ville Syrjälä
2022-03-01 17:31 ` [Intel-gfx] [PATCH 08/11] drm/i915: Replace bxt_clk_div with struct dpll Ville Syrjala
2022-03-04 11:41 ` Jani Nikula
2022-03-01 17:31 ` [Intel-gfx] [PATCH 09/11] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params() Ville Syrjala
2022-03-01 17:44 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-03-01 17:31 ` [Intel-gfx] [PATCH 10/11] drm/i915: Populate bxt/glk DPLL clock limits a bit more Ville Syrjala
2022-03-01 17:31 ` [Intel-gfx] [PATCH 11/11] drm/i915: Remove struct dp_link_dpll Ville Syrjala
2022-03-01 23:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clean up some dpll stuff (rev2) Patchwork
2022-03-02 3:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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