Re: [Intel-gfx] [PATCH 01/11] drm/i915: Nuke skl_wrpll_context_init()

[Jani Nikula <jani.nikula@linux.intel.com>]

On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We can trivially replace skl_wrpll_context_init() with a single
> designated initializer.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++----------
>  1 file changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 569903d47aea..1b1b70f0ff93 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1330,13 +1330,6 @@ struct skl_wrpll_context {
>  	unsigned int p;			/* chosen divider */
>  };
>  
> -static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
> -{
> -	memset(ctx, 0, sizeof(*ctx));
> -
> -	ctx->min_deviation = U64_MAX;
> -}
> -
>  /* DCO freq must be within +1%/-6%  of the DCO central freq */
>  #define SKL_DCO_MAX_PDEVIATION	100
>  #define SKL_DCO_MAX_NDEVIATION	600
> @@ -1519,12 +1512,12 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
>  		{ even_dividers, ARRAY_SIZE(even_dividers) },
>  		{ odd_dividers, ARRAY_SIZE(odd_dividers) },
>  	};
> -	struct skl_wrpll_context ctx;
> +	struct skl_wrpll_context ctx = {
> +		.min_deviation = U64_MAX,
> +	};
>  	unsigned int dco, d, i;
>  	unsigned int p0, p1, p2;
>  
> -	skl_wrpll_context_init(&ctx);
> -
>  	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
>  		for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
>  			for (i = 0; i < dividers[d].n_dividers; i++) {

-- 
Jani Nikula, Intel Open Source Graphics Center