* [Intel-gfx] [PATCH v2 1/9] drm/i915: Tweak plane ddb allocation tracking
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
@ 2022-03-03 19:11 ` Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 2/9] drm/i915: Split plane data_rate into data_rate+data_rate_y Ville Syrjala
` (11 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2022-03-03 19:11 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's store the plane allocation in a manner which more closely
matches how the hw operates. That is, we store the packed/CbCr
ddb in one struct, and the Y ddb in another. Currently we're
storing packed/Y in one struct, CbCr in the other.
This also works pretty well for icl+ where the UV plane is
the main plane and the Y plane is subservient to it. Although
in this case we do not even use ddb_y as we do the ddb allocation
in terms of hw planes.
v2: Rebase
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 32 +++---
drivers/gpu/drm/i915/display/intel_bw.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_types.h | 7 +-
drivers/gpu/drm/i915/intel_pm.c | 108 ++++++++----------
6 files changed, 74 insertions(+), 91 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 5712688232fb..0da9e2fa79eb 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -616,8 +616,8 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
static struct intel_plane *
skl_next_plane_to_commit(struct intel_atomic_state *state,
struct intel_crtc *crtc,
- struct skl_ddb_entry entries_y[I915_MAX_PLANES],
- struct skl_ddb_entry entries_uv[I915_MAX_PLANES],
+ struct skl_ddb_entry ddb[I915_MAX_PLANES],
+ struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
unsigned int *update_mask)
{
struct intel_crtc_state *crtc_state =
@@ -636,17 +636,15 @@ skl_next_plane_to_commit(struct intel_atomic_state *state,
!(*update_mask & BIT(plane_id)))
continue;
- if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
- entries_y,
- I915_MAX_PLANES, plane_id) ||
- skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
- entries_uv,
- I915_MAX_PLANES, plane_id))
+ if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
+ ddb, I915_MAX_PLANES, plane_id) ||
+ skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
+ ddb_y, I915_MAX_PLANES, plane_id))
continue;
*update_mask &= ~BIT(plane_id);
- entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
- entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
+ ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
+ ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
return plane;
}
@@ -728,19 +726,17 @@ static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct skl_ddb_entry entries_y[I915_MAX_PLANES];
- struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
+ struct skl_ddb_entry ddb[I915_MAX_PLANES];
+ struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
u32 update_mask = new_crtc_state->update_planes;
struct intel_plane *plane;
- memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
+ memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
+ sizeof(old_crtc_state->wm.skl.plane_ddb));
+ memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
sizeof(old_crtc_state->wm.skl.plane_ddb_y));
- memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
- sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
- while ((plane = skl_next_plane_to_commit(state, crtc,
- entries_y, entries_uv,
- &update_mask))) {
+ while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index ad1564ca7269..e8fc14ff133f 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -688,16 +688,16 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
return;
for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb[plane_id];
const struct skl_ddb_entry *ddb_y =
&crtc_state->wm.skl.plane_ddb_y[plane_id];
- const struct skl_ddb_entry *ddb_uv =
- &crtc_state->wm.skl.plane_ddb_uv[plane_id];
unsigned int data_rate = crtc_state->data_rate[plane_id];
unsigned int dbuf_mask = 0;
enum dbuf_slice slice;
+ dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb);
dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
- dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_uv);
/*
* FIXME: To calculate that more properly we probably
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 10d483ce04a7..165e8f1ad14a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6433,8 +6433,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct skl_hw_state {
+ struct skl_ddb_entry ddb[I915_MAX_PLANES];
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
- struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
struct skl_pipe_wm wm;
} *hw;
const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
@@ -6451,7 +6451,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
skl_pipe_wm_get_hw_state(crtc, &hw->wm);
- skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
+ skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);
hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
@@ -6533,8 +6533,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
}
/* DDB */
- hw_ddb_entry = &hw->ddb_y[plane->id];
- sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
+ hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
+ sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
drm_err(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index ac141c911685..415dc77abfe8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1127,13 +1127,13 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
seq_printf(m, "Pipe %c\n", pipe_name(pipe));
for_each_plane_id_on_crtc(crtc, plane_id) {
- entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ entry = &crtc_state->wm.skl.plane_ddb[plane_id];
seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1,
entry->start, entry->end,
skl_ddb_entry_size(entry));
}
- entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
+ entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
entry->end, skl_ddb_entry_size(entry));
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 776b3e6662f2..e35002ecdcf8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -847,8 +847,13 @@ struct intel_crtc_wm_state {
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
struct skl_ddb_entry ddb;
+ /*
+ * pre-icl: for packed/planar CbCr
+ * icl+: for everything
+ */
+ struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
+ /* pre-icl: for planar Y */
struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
- struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
} skl;
struct {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f70eb10ab24d..191ef54a2f00 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4327,46 +4327,31 @@ static void
skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
const enum pipe pipe,
const enum plane_id plane_id,
- struct skl_ddb_entry *ddb_y,
- struct skl_ddb_entry *ddb_uv)
+ struct skl_ddb_entry *ddb,
+ struct skl_ddb_entry *ddb_y)
{
- u32 val, val2;
- u32 fourcc = 0;
+ u32 val;
/* Cursor doesn't support NV12/planar, so no extra calculation needed */
if (plane_id == PLANE_CURSOR) {
val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
- skl_ddb_entry_init_from_hw(ddb_y, val);
+ skl_ddb_entry_init_from_hw(ddb, val);
return;
}
- val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id));
+ val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
+ skl_ddb_entry_init_from_hw(ddb, val);
- /* No DDB allocated for disabled planes */
- if (val & PLANE_CTL_ENABLE)
- fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL,
- val & PLANE_CTL_ORDER_RGBX,
- val & PLANE_CTL_ALPHA_MASK);
-
- if (DISPLAY_VER(dev_priv) >= 11) {
- val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
- skl_ddb_entry_init_from_hw(ddb_y, val);
- } else {
- val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
- val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
-
- if (fourcc &&
- drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
- swap(val, val2);
+ if (DISPLAY_VER(dev_priv) >= 11)
+ return;
- skl_ddb_entry_init_from_hw(ddb_y, val);
- skl_ddb_entry_init_from_hw(ddb_uv, val2);
- }
+ val = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
+ skl_ddb_entry_init_from_hw(ddb_y, val);
}
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
- struct skl_ddb_entry *ddb_y,
- struct skl_ddb_entry *ddb_uv)
+ struct skl_ddb_entry *ddb,
+ struct skl_ddb_entry *ddb_y)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum intel_display_power_domain power_domain;
@@ -4382,8 +4367,8 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
for_each_plane_id_on_crtc(crtc, plane_id)
skl_ddb_get_hw_plane_state(dev_priv, pipe,
plane_id,
- &ddb_y[plane_id],
- &ddb_uv[plane_id]);
+ &ddb[plane_id],
+ &ddb_y[plane_id]);
intel_display_power_put(dev_priv, power_domain, wakeref);
}
@@ -5176,8 +5161,8 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
int level;
/* Clear the partitioning for disabled planes. */
+ memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb));
memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
- memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
if (!crtc_state->hw.active)
return 0;
@@ -5194,7 +5179,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
/* Allocate fixed number of blocks for cursor. */
iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
iter.size -= iter.total[PLANE_CURSOR];
- skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
+ skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
alloc->end - iter.total[PLANE_CURSOR], alloc->end);
/*
@@ -5264,10 +5249,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
/* Set the actual DDB start/end points for each plane */
iter.start = alloc->start;
for_each_plane_id_on_crtc(crtc, plane_id) {
- struct skl_ddb_entry *plane_alloc =
+ struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb[plane_id];
+ struct skl_ddb_entry *ddb_y =
&crtc_state->wm.skl.plane_ddb_y[plane_id];
- struct skl_ddb_entry *uv_plane_alloc =
- &crtc_state->wm.skl.plane_ddb_uv[plane_id];
if (plane_id == PLANE_CURSOR)
continue;
@@ -5278,12 +5263,15 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
/* Leave disabled planes at (0,0) */
if (iter.total[plane_id])
- iter.start = skl_ddb_entry_init(plane_alloc, iter.start,
+ iter.start = skl_ddb_entry_init(ddb, iter.start,
iter.start + iter.total[plane_id]);
- if (iter.uv_total[plane_id])
- iter.start = skl_ddb_entry_init(uv_plane_alloc, iter.start,
+ if (iter.uv_total[plane_id]) {
+ /* hardware wants these swapped */
+ *ddb_y = *ddb;
+ iter.start = skl_ddb_entry_init(ddb, iter.start,
iter.start + iter.uv_total[plane_id]);
+ }
}
/*
@@ -5940,11 +5928,10 @@ void skl_write_plane_wm(struct intel_plane *plane,
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
- const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+ const struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb[plane_id];
const struct skl_ddb_entry *ddb_y =
&crtc_state->wm.skl.plane_ddb_y[plane_id];
- const struct skl_ddb_entry *ddb_uv =
- &crtc_state->wm.skl.plane_ddb_uv[plane_id];
for (level = 0; level <= max_level; level++)
skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
@@ -5954,25 +5941,20 @@ void skl_write_plane_wm(struct intel_plane *plane,
skl_plane_trans_wm(pipe_wm, plane_id));
if (HAS_HW_SAGV_WM(dev_priv)) {
+ const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id),
&wm->sagv.wm0);
skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id),
&wm->sagv.trans_wm);
}
- if (DISPLAY_VER(dev_priv) >= 11) {
+ skl_ddb_entry_write(dev_priv,
+ PLANE_BUF_CFG(pipe, plane_id), ddb);
+
+ if (DISPLAY_VER(dev_priv) < 11)
skl_ddb_entry_write(dev_priv,
- PLANE_BUF_CFG(pipe, plane_id), ddb_y);
- return;
- }
-
- if (wm->is_planar)
- swap(ddb_y, ddb_uv);
-
- skl_ddb_entry_write(dev_priv,
- PLANE_BUF_CFG(pipe, plane_id), ddb_y);
- skl_ddb_entry_write(dev_priv,
- PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
+ PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
}
void skl_write_cursor_wm(struct intel_plane *plane,
@@ -5984,7 +5966,7 @@ void skl_write_cursor_wm(struct intel_plane *plane,
enum pipe pipe = plane->pipe;
const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
const struct skl_ddb_entry *ddb =
- &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ &crtc_state->wm.skl.plane_ddb[plane_id];
for (level = 0; level <= max_level; level++)
skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
@@ -6081,10 +6063,10 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
struct intel_plane_state *plane_state;
enum plane_id plane_id = plane->id;
- if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
- &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
- skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
- &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
+ if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id],
+ &new_crtc_state->wm.skl.plane_ddb[plane_id]) &&
+ skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
+ &new_crtc_state->wm.skl.plane_ddb_y[plane_id]))
continue;
plane_state = intel_atomic_get_plane_state(state, plane);
@@ -6253,8 +6235,8 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enum plane_id plane_id = plane->id;
const struct skl_ddb_entry *old, *new;
- old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
- new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
+ old = &old_crtc_state->wm.skl.plane_ddb[plane_id];
+ new = &new_crtc_state->wm.skl.plane_ddb[plane_id];
if (skl_ddb_entry_equal(old, new))
continue;
@@ -6656,16 +6638,16 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));
for_each_plane_id_on_crtc(crtc, plane_id) {
+ struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb[plane_id];
struct skl_ddb_entry *ddb_y =
&crtc_state->wm.skl.plane_ddb_y[plane_id];
- struct skl_ddb_entry *ddb_uv =
- &crtc_state->wm.skl.plane_ddb_uv[plane_id];
skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe,
- plane_id, ddb_y, ddb_uv);
+ plane_id, ddb, ddb_y);
+ skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb);
skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);
- skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv);
}
dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH v2 2/9] drm/i915: Split plane data_rate into data_rate+data_rate_y
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
2022-03-03 19:11 ` [Intel-gfx] [PATCH v2 1/9] drm/i915: Tweak plane ddb allocation tracking Ville Syrjala
@ 2022-03-03 19:12 ` Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 3/9] drm/i915: Pre-calculate plane relative data rate Ville Syrjala
` (10 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2022-03-03 19:12 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Split the currently combined plane data_rate into the proper
Y vs. CbCr components. This matches how we now track the
plane dbuf allocations, and thus will make the dbuf bandwidth
calculations actually produce the correct numbers for each
dbuf slice.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 34 ++++++++----------
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
drivers/gpu/drm/i915/display/intel_bw.c | 36 +++++++++----------
drivers/gpu/drm/i915/display/intel_display.c | 4 +++
.../drm/i915/display/intel_display_types.h | 3 ++
5 files changed, 42 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 0da9e2fa79eb..b0aa65845f90 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -181,29 +181,16 @@ unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
}
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+ const struct intel_plane_state *plane_state,
+ int color_plane)
{
const struct drm_framebuffer *fb = plane_state->hw.fb;
- unsigned int cpp;
- unsigned int pixel_rate;
if (!plane_state->uapi.visible)
return 0;
- pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
-
- cpp = fb->format->cpp[0];
-
- /*
- * Based on HSD#:1408715493
- * NV12 cpp == 4, P010 cpp == 8
- *
- * FIXME what is the logic behind this?
- */
- if (fb->format->is_yuv && fb->format->num_planes > 1)
- cpp *= 4;
-
- return pixel_rate * cpp;
+ return intel_plane_pixel_rate(crtc_state, plane_state) *
+ fb->format->cpp[color_plane];
}
int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
@@ -326,6 +313,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
crtc_state->nv12_planes &= ~BIT(plane->id);
crtc_state->c8_planes &= ~BIT(plane->id);
crtc_state->data_rate[plane->id] = 0;
+ crtc_state->data_rate_y[plane->id] = 0;
crtc_state->min_cdclk[plane->id] = 0;
plane_state->uapi.visible = false;
@@ -551,8 +539,16 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
new_crtc_state->update_planes |= BIT(plane->id);
- new_crtc_state->data_rate[plane->id] =
- intel_plane_data_rate(new_crtc_state, new_plane_state);
+ if (new_plane_state->uapi.visible &&
+ intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+ new_crtc_state->data_rate_y[plane->id] =
+ intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
+ new_crtc_state->data_rate[plane->id] =
+ intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
+ } else if (new_plane_state->uapi.visible) {
+ new_crtc_state->data_rate[plane->id] =
+ intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
+ }
return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
old_plane_state, new_plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index f4763a53541e..74b6d3b169a7 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -25,7 +25,8 @@ unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state);
+ const struct intel_plane_state *plane_state,
+ int color_plane);
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
const struct intel_plane_state *from_plane_state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index e8fc14ff133f..fa51fa85e431 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -578,6 +578,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_stat
static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
unsigned int data_rate = 0;
enum plane_id plane_id;
@@ -590,6 +591,9 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
continue;
data_rate += crtc_state->data_rate[plane_id];
+
+ if (DISPLAY_VER(i915) < 11)
+ data_rate += crtc_state->data_rate_y[plane_id];
}
return data_rate;
@@ -690,28 +694,24 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
for_each_plane_id_on_crtc(crtc, plane_id) {
const struct skl_ddb_entry *ddb =
&crtc_state->wm.skl.plane_ddb[plane_id];
- const struct skl_ddb_entry *ddb_y =
- &crtc_state->wm.skl.plane_ddb_y[plane_id];
unsigned int data_rate = crtc_state->data_rate[plane_id];
- unsigned int dbuf_mask = 0;
+ unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
enum dbuf_slice slice;
- dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb);
- dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
+ for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
+ crtc_bw->used_bw[slice] += data_rate;
+ }
+
+ if (DISPLAY_VER(i915) >= 11)
+ return;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ unsigned int data_rate = crtc_state->data_rate_y[plane_id];
+ unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
+ enum dbuf_slice slice;
- /*
- * FIXME: To calculate that more properly we probably
- * need to split per plane data_rate into data_rate_y
- * and data_rate_uv for multiplanar formats in order not
- * to get accounted those twice if they happen to reside
- * on different slices.
- * However for pre-icl this would work anyway because
- * we have only single slice and for icl+ uv plane has
- * non-zero data rate.
- * So in worst case those calculation are a bit
- * pessimistic, which shouldn't pose any significant
- * problem anyway.
- */
for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
crtc_bw->used_bw[slice] += data_rate;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 165e8f1ad14a..5e3174dde876 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -785,6 +785,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
intel_set_plane_visible(crtc_state, plane_state, false);
fixup_plane_bitmasks(crtc_state);
crtc_state->data_rate[plane->id] = 0;
+ crtc_state->data_rate_y[plane->id] = 0;
crtc_state->min_cdclk[plane->id] = 0;
if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
@@ -4762,6 +4763,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
crtc_state->enabled_planes &= ~BIT(plane->id);
crtc_state->active_planes &= ~BIT(plane->id);
crtc_state->update_planes |= BIT(plane->id);
+ crtc_state->data_rate[plane->id] = 0;
}
plane_state->planar_slave = false;
@@ -4806,6 +4808,8 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
crtc_state->enabled_planes |= BIT(linked->id);
crtc_state->active_planes |= BIT(linked->id);
crtc_state->update_planes |= BIT(linked->id);
+ crtc_state->data_rate[linked->id] =
+ crtc_state->data_rate_y[plane->id];
drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
linked->base.name, plane->base.name);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e35002ecdcf8..ad48509119ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1130,7 +1130,10 @@ struct intel_crtc_state {
int min_cdclk[I915_MAX_PLANES];
+ /* for packed/planar CbCr */
u32 data_rate[I915_MAX_PLANES];
+ /* for planar Y */
+ u32 data_rate_y[I915_MAX_PLANES];
/* FIXME unify with data_rate[] */
u64 plane_data_rate[I915_MAX_PLANES];
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH v2 3/9] drm/i915: Pre-calculate plane relative data rate
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
2022-03-03 19:11 ` [Intel-gfx] [PATCH v2 1/9] drm/i915: Tweak plane ddb allocation tracking Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 2/9] drm/i915: Split plane data_rate into data_rate+data_rate_y Ville Syrjala
@ 2022-03-03 19:12 ` Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 4/9] drm/i915: Remove total[] and uv_total[] from ddb allocation Ville Syrjala
` (9 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2022-03-03 19:12 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Handle the plane relative data rate in exactly the same
way as we already handle the real data rate. Ie. pre-calculate
it during intel_plane_atomic_check_with_state(), and assign/clear
it for the Y plane as needed. This should guarantee that the
tracking is 100% consistent, and makes me have to think less
when the same apporach is used by both types of data rate.
We might even want to consider replacing the relative
data rate with the real data rate entirely, but it's not
clear if that will produce less optimal plane ddb
allocations. So for now lets keep using the current approach.
v2: Rebase due to async flip wm optimization
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 64 ++++++
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/intel_pm.c | 187 ++++--------------
4 files changed, 108 insertions(+), 154 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index b0aa65845f90..6ed2bf5b3942 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -193,6 +193,57 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
fb->format->cpp[color_plane];
}
+static bool
+use_min_ddb(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
+static unsigned int
+intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ int color_plane)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ int width, height;
+
+ if (plane->id == PLANE_CURSOR)
+ return 0;
+
+ if (!plane_state->uapi.visible)
+ return 0;
+
+ /*
+ * We calculate extra ddb based on ratio plane rate/total data rate
+ * in case, in some cases we should not allocate extra ddb for the plane,
+ * so do not count its data rate, if this is the case.
+ */
+ if (use_min_ddb(crtc_state, plane))
+ return 0;
+
+ /*
+ * Src coordinates are already rotated by 270 degrees for
+ * the 90/270 degree plane rotation cases (to match the
+ * GTT mapping), hence no need to account for rotation here.
+ */
+ width = drm_rect_width(&plane_state->uapi.src) >> 16;
+ height = drm_rect_height(&plane_state->uapi.src) >> 16;
+
+ /* UV plane does 1/2 pixel sub-sampling */
+ if (color_plane == 1) {
+ width /= 2;
+ height /= 2;
+ }
+
+ return width * height * fb->format->cpp[color_plane];
+}
+
int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
struct intel_plane *plane,
bool *need_cdclk_calc)
@@ -314,6 +365,8 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
crtc_state->c8_planes &= ~BIT(plane->id);
crtc_state->data_rate[plane->id] = 0;
crtc_state->data_rate_y[plane->id] = 0;
+ crtc_state->rel_data_rate[plane->id] = 0;
+ crtc_state->rel_data_rate_y[plane->id] = 0;
crtc_state->min_cdclk[plane->id] = 0;
plane_state->uapi.visible = false;
@@ -545,9 +598,20 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
new_crtc_state->data_rate[plane->id] =
intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
+
+ new_crtc_state->rel_data_rate_y[plane->id] =
+ intel_plane_relative_data_rate(new_crtc_state,
+ new_plane_state, 0);
+ new_crtc_state->rel_data_rate[plane->id] =
+ intel_plane_relative_data_rate(new_crtc_state,
+ new_plane_state, 1);
} else if (new_plane_state->uapi.visible) {
new_crtc_state->data_rate[plane->id] =
intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
+
+ new_crtc_state->rel_data_rate[plane->id] =
+ intel_plane_relative_data_rate(new_crtc_state,
+ new_plane_state, 0);
}
return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5e3174dde876..45f05a9ea03e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -786,6 +786,8 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
fixup_plane_bitmasks(crtc_state);
crtc_state->data_rate[plane->id] = 0;
crtc_state->data_rate_y[plane->id] = 0;
+ crtc_state->rel_data_rate[plane->id] = 0;
+ crtc_state->rel_data_rate_y[plane->id] = 0;
crtc_state->min_cdclk[plane->id] = 0;
if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
@@ -4764,6 +4766,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
crtc_state->active_planes &= ~BIT(plane->id);
crtc_state->update_planes |= BIT(plane->id);
crtc_state->data_rate[plane->id] = 0;
+ crtc_state->rel_data_rate[plane->id] = 0;
}
plane_state->planar_slave = false;
@@ -4810,6 +4813,8 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
crtc_state->update_planes |= BIT(linked->id);
crtc_state->data_rate[linked->id] =
crtc_state->data_rate_y[plane->id];
+ crtc_state->rel_data_rate[linked->id] =
+ crtc_state->rel_data_rate_y[plane->id];
drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
linked->base.name, plane->base.name);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ad48509119ff..fb4a8dfd07dd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1135,9 +1135,9 @@ struct intel_crtc_state {
/* for planar Y */
u32 data_rate_y[I915_MAX_PLANES];
- /* FIXME unify with data_rate[] */
- u64 plane_data_rate[I915_MAX_PLANES];
- u64 uv_plane_data_rate[I915_MAX_PLANES];
+ /* FIXME unify with data_rate[]? */
+ u64 rel_data_rate[I915_MAX_PLANES];
+ u64 rel_data_rate_y[I915_MAX_PLANES];
/* Gamma mode programmed on the pipe */
u32 gamma_mode;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 191ef54a2f00..d292a9e65e3f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4899,17 +4899,6 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool
return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
}
-static bool
-use_min_ddb(const struct intel_crtc_state *crtc_state,
- struct intel_plane *plane)
-{
- struct drm_i915_private *i915 = to_i915(plane->base.dev);
-
- return DISPLAY_VER(i915) >= 13 &&
- crtc_state->uapi.async_flip &&
- plane->async_flip;
-}
-
static bool
use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane)
@@ -4922,134 +4911,24 @@ use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
}
static u64
-skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state,
- int color_plane)
+skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- const struct drm_framebuffer *fb = plane_state->hw.fb;
- int width, height;
-
- if (!plane_state->uapi.visible)
- return 0;
-
- if (plane->id == PLANE_CURSOR)
- return 0;
-
- /*
- * We calculate extra ddb based on ratio plane rate/total data rate
- * in case, in some cases we should not allocate extra ddb for the plane,
- * so do not count its data rate, if this is the case.
- */
- if (use_min_ddb(crtc_state, plane))
- return 0;
-
- if (color_plane == 1 &&
- !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
- return 0;
-
- /*
- * Src coordinates are already rotated by 270 degrees for
- * the 90/270 degree plane rotation cases (to match the
- * GTT mapping), hence no need to account for rotation here.
- */
- width = drm_rect_width(&plane_state->uapi.src) >> 16;
- height = drm_rect_height(&plane_state->uapi.src) >> 16;
-
- /* UV plane does 1/2 pixel sub-sampling */
- if (color_plane == 1) {
- width /= 2;
- height /= 2;
- }
-
- return width * height * fb->format->cpp[color_plane];
-}
-
-static u64
-skl_get_total_relative_data_rate(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- const struct intel_plane_state *plane_state;
- struct intel_plane *plane;
- u64 total_data_rate = 0;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum plane_id plane_id;
- int i;
-
- /* Calculate and cache data rate for each plane */
- for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
- if (plane->pipe != crtc->pipe)
- continue;
-
- plane_id = plane->id;
-
- /* packed/y */
- crtc_state->plane_data_rate[plane_id] =
- skl_plane_relative_data_rate(crtc_state, plane_state, 0);
-
- /* uv-plane */
- crtc_state->uv_plane_data_rate[plane_id] =
- skl_plane_relative_data_rate(crtc_state, plane_state, 1);
- }
+ u64 data_rate = 0;
for_each_plane_id_on_crtc(crtc, plane_id) {
- total_data_rate += crtc_state->plane_data_rate[plane_id];
- total_data_rate += crtc_state->uv_plane_data_rate[plane_id];
- }
-
- return total_data_rate;
-}
-
-static u64
-icl_get_total_relative_data_rate(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- const struct intel_plane_state *plane_state;
- struct intel_plane *plane;
- u64 total_data_rate = 0;
- enum plane_id plane_id;
- int i;
-
- /* Calculate and cache data rate for each plane */
- for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
- if (plane->pipe != crtc->pipe)
+ if (plane_id == PLANE_CURSOR)
continue;
- plane_id = plane->id;
+ data_rate += crtc_state->rel_data_rate[plane_id];
- if (!plane_state->planar_linked_plane) {
- crtc_state->plane_data_rate[plane_id] =
- skl_plane_relative_data_rate(crtc_state, plane_state, 0);
- } else {
- enum plane_id y_plane_id;
-
- /*
- * The slave plane might not iterate in
- * intel_atomic_crtc_state_for_each_plane_state(),
- * and needs the master plane state which may be
- * NULL if we try get_new_plane_state(), so we
- * always calculate from the master.
- */
- if (plane_state->planar_slave)
- continue;
-
- /* Y plane rate is calculated on the slave */
- y_plane_id = plane_state->planar_linked_plane->id;
- crtc_state->plane_data_rate[y_plane_id] =
- skl_plane_relative_data_rate(crtc_state, plane_state, 0);
-
- crtc_state->plane_data_rate[plane_id] =
- skl_plane_relative_data_rate(crtc_state, plane_state, 1);
- }
+ if (DISPLAY_VER(i915) < 11)
+ data_rate += crtc_state->rel_data_rate_y[plane_id];
}
- for_each_plane_id_on_crtc(crtc, plane_id)
- total_data_rate += crtc_state->plane_data_rate[plane_id];
-
- return total_data_rate;
+ return data_rate;
}
const struct skl_wm_level *
@@ -5167,11 +5046,6 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
if (!crtc_state->hw.active)
return 0;
- if (DISPLAY_VER(dev_priv) >= 11)
- iter.data_rate = icl_get_total_relative_data_rate(state, crtc);
- else
- iter.data_rate = skl_get_total_relative_data_rate(state, crtc);
-
iter.size = skl_ddb_entry_size(alloc);
if (iter.size == 0)
return 0;
@@ -5182,6 +5056,8 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
alloc->end - iter.total[PLANE_CURSOR], alloc->end);
+ iter.data_rate = skl_total_relative_data_rate(crtc_state);
+
/*
* Find the highest watermark level for which we can satisfy the block
* requirement of active planes.
@@ -5236,13 +5112,19 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
if (plane_id == PLANE_CURSOR)
continue;
- iter.total[plane_id] =
- skl_allocate_plane_ddb(&iter, &wm->wm[level],
- crtc_state->plane_data_rate[plane_id]);
-
- iter.uv_total[plane_id] =
- skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
- crtc_state->uv_plane_data_rate[plane_id]);
+ if (DISPLAY_VER(dev_priv) < 11 &&
+ crtc_state->nv12_planes & BIT(plane_id)) {
+ iter.total[plane_id] =
+ skl_allocate_plane_ddb(&iter, &wm->wm[level],
+ crtc_state->rel_data_rate_y[plane_id]);
+ iter.uv_total[plane_id] =
+ skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
+ crtc_state->rel_data_rate[plane_id]);
+ } else {
+ iter.total[plane_id] =
+ skl_allocate_plane_ddb(&iter, &wm->wm[level],
+ crtc_state->rel_data_rate[plane_id]);
+ }
}
drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
@@ -5262,15 +5144,18 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
DISPLAY_VER(dev_priv) >= 11 && iter.uv_total[plane_id]);
/* Leave disabled planes at (0,0) */
- if (iter.total[plane_id])
- iter.start = skl_ddb_entry_init(ddb, iter.start,
- iter.start + iter.total[plane_id]);
-
- if (iter.uv_total[plane_id]) {
- /* hardware wants these swapped */
- *ddb_y = *ddb;
- iter.start = skl_ddb_entry_init(ddb, iter.start,
- iter.start + iter.uv_total[plane_id]);
+ if (DISPLAY_VER(dev_priv) < 11 &&
+ crtc_state->nv12_planes & BIT(plane_id)) {
+ if (iter.total[plane_id])
+ iter.start = skl_ddb_entry_init(ddb_y, iter.start,
+ iter.start + iter.total[plane_id]);
+ if (iter.uv_total[plane_id])
+ iter.start = skl_ddb_entry_init(ddb, iter.start,
+ iter.start + iter.uv_total[plane_id]);
+ } else {
+ if (iter.total[plane_id])
+ iter.start = skl_ddb_entry_init(ddb, iter.start,
+ iter.start + iter.total[plane_id]);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH v2 4/9] drm/i915: Remove total[] and uv_total[] from ddb allocation
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
` (2 preceding siblings ...)
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 3/9] drm/i915: Pre-calculate plane relative data rate Ville Syrjala
@ 2022-03-03 19:12 ` Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 5/9] drm/i915: Nuke intel_bw_calc_min_cdclk() Ville Syrjala
` (8 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2022-03-03 19:12 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
There's really no need to maintain these total[] arrays to
track the size of each plane's ddb allocation. We just stick
the results straight into the crtc_state ddb tracking structures.
The main annoyance with all this is the mismatch between
wm_uv vs. ddb_y on pre-icl. If only the hw was consistent in
what it considers the primary source of information we could
avoid some of the uglyness. But since that is not the case
we need a bit of special casing for planar formats.
v2: Keep the ddb entry zeroed when the plane is disabled
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 122 ++++++++++++++++----------------
1 file changed, 62 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d292a9e65e3f..641624937029 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4969,18 +4969,18 @@ skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
* So this is actually safe to do.
*/
static void
-skl_check_wm_level(struct skl_wm_level *wm, u64 total)
+skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)
{
- if (wm->min_ddb_alloc > total)
+ if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb))
memset(wm, 0, sizeof(*wm));
}
static void
skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
- u64 total, u64 uv_total)
+ const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)
{
- if (wm->min_ddb_alloc > total ||
- uv_wm->min_ddb_alloc > uv_total) {
+ if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) ||
+ uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) {
memset(wm, 0, sizeof(*wm));
memset(uv_wm, 0, sizeof(*uv_wm));
}
@@ -5000,17 +5000,16 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
struct skl_plane_ddb_iter {
u64 data_rate;
- u16 total[I915_MAX_PLANES];
- u16 uv_total[I915_MAX_PLANES];
u16 start, size;
};
-static u16
+static void
skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
+ struct skl_ddb_entry *ddb,
const struct skl_wm_level *wm,
u64 data_rate)
{
- u16 extra = 0;
+ u16 size, extra = 0;
if (data_rate) {
extra = min_t(u16, iter->size,
@@ -5020,7 +5019,15 @@ skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
iter->data_rate -= data_rate;
}
- return wm->min_ddb_alloc + extra;
+ /*
+ * Keep ddb entry of all disabled planes explicitly zeroed
+ * to avoid skl_ddb_add_affected_planes() adding them to
+ * the state when other planes change their allocations.
+ */
+ size = wm->min_ddb_alloc + extra;
+ if (size)
+ iter->start = skl_ddb_entry_init(ddb, iter->start,
+ iter->start + size);
}
static int
@@ -5034,8 +5041,9 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
intel_atomic_get_new_dbuf_state(state);
const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
int num_active = hweight8(dbuf_state->active_pipes);
- struct skl_plane_ddb_iter iter = {};
+ struct skl_plane_ddb_iter iter;
enum plane_id plane_id;
+ u16 cursor_size;
u32 blocks;
int level;
@@ -5046,15 +5054,16 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
if (!crtc_state->hw.active)
return 0;
+ iter.start = alloc->start;
iter.size = skl_ddb_entry_size(alloc);
if (iter.size == 0)
return 0;
/* Allocate fixed number of blocks for cursor. */
- iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
- iter.size -= iter.total[PLANE_CURSOR];
+ cursor_size = skl_cursor_allocation(crtc_state, num_active);
+ iter.size -= cursor_size;
skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
- alloc->end - iter.total[PLANE_CURSOR], alloc->end);
+ alloc->end - cursor_size, alloc->end);
iter.data_rate = skl_total_relative_data_rate(crtc_state);
@@ -5069,7 +5078,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
&crtc_state->wm.skl.optimal.planes[plane_id];
if (plane_id == PLANE_CURSOR) {
- if (wm->wm[level].min_ddb_alloc > iter.total[PLANE_CURSOR]) {
+ const struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb[plane_id];
+
+ if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) {
drm_WARN_ON(&dev_priv->drm,
wm->wm[level].min_ddb_alloc != U16_MAX);
blocks = U32_MAX;
@@ -5105,59 +5117,29 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
* watermark level, plus an extra share of the leftover blocks
* proportional to its relative data rate.
*/
- for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
-
- if (plane_id == PLANE_CURSOR)
- continue;
-
- if (DISPLAY_VER(dev_priv) < 11 &&
- crtc_state->nv12_planes & BIT(plane_id)) {
- iter.total[plane_id] =
- skl_allocate_plane_ddb(&iter, &wm->wm[level],
- crtc_state->rel_data_rate_y[plane_id]);
- iter.uv_total[plane_id] =
- skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
- crtc_state->rel_data_rate[plane_id]);
- } else {
- iter.total[plane_id] =
- skl_allocate_plane_ddb(&iter, &wm->wm[level],
- crtc_state->rel_data_rate[plane_id]);
- }
- }
- drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
-
- /* Set the actual DDB start/end points for each plane */
- iter.start = alloc->start;
for_each_plane_id_on_crtc(crtc, plane_id) {
struct skl_ddb_entry *ddb =
&crtc_state->wm.skl.plane_ddb[plane_id];
struct skl_ddb_entry *ddb_y =
&crtc_state->wm.skl.plane_ddb_y[plane_id];
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
if (plane_id == PLANE_CURSOR)
continue;
- /* Gen11+ uses a separate plane for UV watermarks */
- drm_WARN_ON(&dev_priv->drm,
- DISPLAY_VER(dev_priv) >= 11 && iter.uv_total[plane_id]);
-
- /* Leave disabled planes at (0,0) */
if (DISPLAY_VER(dev_priv) < 11 &&
crtc_state->nv12_planes & BIT(plane_id)) {
- if (iter.total[plane_id])
- iter.start = skl_ddb_entry_init(ddb_y, iter.start,
- iter.start + iter.total[plane_id]);
- if (iter.uv_total[plane_id])
- iter.start = skl_ddb_entry_init(ddb, iter.start,
- iter.start + iter.uv_total[plane_id]);
+ skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level],
+ crtc_state->rel_data_rate_y[plane_id]);
+ skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level],
+ crtc_state->rel_data_rate[plane_id]);
} else {
- if (iter.total[plane_id])
- iter.start = skl_ddb_entry_init(ddb, iter.start,
- iter.start + iter.total[plane_id]);
+ skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level],
+ crtc_state->rel_data_rate[plane_id]);
}
}
+ drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
/*
* When we calculated watermark values we didn't know how high
@@ -5167,12 +5149,20 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
*/
for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb[plane_id];
+ const struct skl_ddb_entry *ddb_y =
+ &crtc_state->wm.skl.plane_ddb_y[plane_id];
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
- iter.total[plane_id],
- iter.uv_total[plane_id]);
+ if (DISPLAY_VER(dev_priv) < 11 &&
+ crtc_state->nv12_planes & BIT(plane_id))
+ skl_check_nv12_wm_level(&wm->wm[level],
+ &wm->uv_wm[level],
+ ddb_y, ddb);
+ else
+ skl_check_wm_level(&wm->wm[level], ddb);
if (icl_need_wm1_wa(dev_priv, plane_id) &&
level == 1 && wm->wm[0].enable) {
@@ -5188,12 +5178,24 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
* if it turns out we don't have enough DDB blocks for them.
*/
for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb[plane_id];
+ const struct skl_ddb_entry *ddb_y =
+ &crtc_state->wm.skl.plane_ddb_y[plane_id];
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- skl_check_wm_level(&wm->trans_wm, iter.total[plane_id]);
- skl_check_wm_level(&wm->sagv.wm0, iter.total[plane_id]);
- skl_check_wm_level(&wm->sagv.trans_wm, iter.total[plane_id]);
+ if (DISPLAY_VER(dev_priv) < 11 &&
+ crtc_state->nv12_planes & BIT(plane_id)) {
+ skl_check_wm_level(&wm->trans_wm, ddb_y);
+ } else {
+ WARN_ON(skl_ddb_entry_size(ddb_y));
+
+ skl_check_wm_level(&wm->trans_wm, ddb);
+ }
+
+ skl_check_wm_level(&wm->sagv.wm0, ddb);
+ skl_check_wm_level(&wm->sagv.trans_wm, ddb);
}
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH v2 5/9] drm/i915: Nuke intel_bw_calc_min_cdclk()
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
` (3 preceding siblings ...)
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 4/9] drm/i915: Remove total[] and uv_total[] from ddb allocation Ville Syrjala
@ 2022-03-03 19:12 ` Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 6/9] drm/i915: Round up when calculating display bandwidth requirements Ville Syrjala
` (7 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2022-03-03 19:12 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_bw_calc_min_cdclk() is entirely pointless. All it manages to do is
somehow conflate the per-pipe min cdclk with dbuf min cdclk. There is no
(at least documented) dbuf min cdclk limit on pre-skl so let's just get
rid of all this confusion.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 49 ++--------------------
drivers/gpu/drm/i915/display/intel_bw.h | 1 -
drivers/gpu/drm/i915/display/intel_cdclk.c | 31 +-------------
3 files changed, 5 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index fa51fa85e431..df98b1d7a6f7 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -717,7 +717,7 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
}
}
-int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
+int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_bw_state *new_bw_state = NULL;
@@ -728,6 +728,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
enum pipe pipe;
int i;
+ if (DISPLAY_VER(dev_priv) < 9)
+ return 0;
+
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
new_bw_state = intel_atomic_get_bw_state(state);
if (IS_ERR(new_bw_state))
@@ -772,50 +775,6 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
return 0;
}
-int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_bw_state *new_bw_state = NULL;
- struct intel_bw_state *old_bw_state = NULL;
- const struct intel_crtc_state *crtc_state;
- struct intel_crtc *crtc;
- int min_cdclk = 0;
- enum pipe pipe;
- int i;
-
- for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- new_bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(new_bw_state))
- return PTR_ERR(new_bw_state);
-
- old_bw_state = intel_atomic_get_old_bw_state(state);
- }
-
- if (!old_bw_state)
- return 0;
-
- for_each_pipe(dev_priv, pipe) {
- struct intel_cdclk_state *cdclk_state;
-
- cdclk_state = intel_atomic_get_new_cdclk_state(state);
- if (!cdclk_state)
- return 0;
-
- min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
- }
-
- new_bw_state->min_cdclk = min_cdclk;
-
- if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
- int ret = intel_atomic_lock_global_state(&new_bw_state->base);
-
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
{
unsigned int num_psf_gv_points = i915->max_bw[0].num_psf_gv_points;
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 0ceaed1c9656..6acdf1245b3a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -65,6 +65,5 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask);
int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
-int skl_bw_calc_min_cdclk(struct intel_atomic_state *state);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 8888fda8b701..5d0c2f8b0533 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -72,7 +72,6 @@ struct intel_cdclk_funcs {
void (*set_cdclk)(struct drm_i915_private *i915,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe);
- int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
u8 (*calc_voltage_level)(int cdclk);
};
@@ -83,12 +82,6 @@ void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
}
-static int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
-}
-
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
@@ -2683,7 +2676,7 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state,
old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
*need_cdclk_calc = true;
- ret = intel_cdclk_bw_calc_min_cdclk(state);
+ ret = intel_bw_calc_min_cdclk(state);
if (ret)
return ret;
@@ -3072,7 +3065,6 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
- .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
.calc_voltage_level = tgl_calc_voltage_level,
};
@@ -3080,7 +3072,6 @@ static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
- .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
.calc_voltage_level = ehl_calc_voltage_level,
};
@@ -3088,7 +3079,6 @@ static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
static const struct intel_cdclk_funcs icl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
- .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
.calc_voltage_level = icl_calc_voltage_level,
};
@@ -3096,7 +3086,6 @@ static const struct intel_cdclk_funcs icl_cdclk_funcs = {
static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
- .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
.calc_voltage_level = bxt_calc_voltage_level,
};
@@ -3104,53 +3093,45 @@ static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
static const struct intel_cdclk_funcs skl_cdclk_funcs = {
.get_cdclk = skl_get_cdclk,
.set_cdclk = skl_set_cdclk,
- .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
.modeset_calc_cdclk = skl_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
.get_cdclk = bdw_get_cdclk,
.set_cdclk = bdw_set_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs chv_cdclk_funcs = {
.get_cdclk = vlv_get_cdclk,
.set_cdclk = chv_set_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
.get_cdclk = vlv_get_cdclk,
.set_cdclk = vlv_set_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
.get_cdclk = hsw_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
/* SNB, IVB, 965G, 945G */
static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
.get_cdclk = fixed_400mhz_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
.get_cdclk = fixed_450mhz_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
.get_cdclk = gm45_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
@@ -3158,7 +3139,6 @@ static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
.get_cdclk = i965gm_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
@@ -3166,19 +3146,16 @@ static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
.get_cdclk = pnv_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs g33_cdclk_funcs = {
.get_cdclk = g33_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
.get_cdclk = i945gm_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
@@ -3186,37 +3163,31 @@ static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
.get_cdclk = i915gm_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
.get_cdclk = fixed_333mhz_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
.get_cdclk = fixed_266mhz_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
.get_cdclk = i85x_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
.get_cdclk = fixed_200mhz_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
static const struct intel_cdclk_funcs i830_cdclk_funcs = {
.get_cdclk = fixed_133mhz_get_cdclk,
- .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH v2 6/9] drm/i915: Round up when calculating display bandwidth requirements
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
` (4 preceding siblings ...)
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 5/9] drm/i915: Nuke intel_bw_calc_min_cdclk() Ville Syrjala
@ 2022-03-03 19:12 ` Ville Syrjala
2022-03-10 7:46 ` Lisovskiy, Stanislav
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 7/9] drm/i915: Properly write lock bw_state when it changes Ville Syrjala
` (6 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2022-03-03 19:12 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We should round up when doing bandwidth calculations to make sure
our estimates don't fall short of the actual number.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index df98b1d7a6f7..0759bb95ea4b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -638,7 +638,7 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
data_rate += bw_state->data_rate[pipe];
if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv))
- data_rate = data_rate * 105 / 100;
+ data_rate = DIV_ROUND_UP(data_rate * 105, 100);
return data_rate;
}
@@ -763,7 +763,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
}
}
- new_bw_state->min_cdclk = max_bw / 64;
+ new_bw_state->min_cdclk = DIV_ROUND_UP(max_bw, 64);
if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
int ret = intel_atomic_lock_global_state(&new_bw_state->base);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH v2 6/9] drm/i915: Round up when calculating display bandwidth requirements
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 6/9] drm/i915: Round up when calculating display bandwidth requirements Ville Syrjala
@ 2022-03-10 7:46 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 20+ messages in thread
From: Lisovskiy, Stanislav @ 2022-03-10 7:46 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Mar 03, 2022 at 09:12:04PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We should round up when doing bandwidth calculations to make sure
> our estimates don't fall short of the actual number.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index df98b1d7a6f7..0759bb95ea4b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -638,7 +638,7 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> data_rate += bw_state->data_rate[pipe];
>
> if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv))
> - data_rate = data_rate * 105 / 100;
> + data_rate = DIV_ROUND_UP(data_rate * 105, 100);
>
> return data_rate;
> }
> @@ -763,7 +763,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
> }
> }
>
> - new_bw_state->min_cdclk = max_bw / 64;
> + new_bw_state->min_cdclk = DIV_ROUND_UP(max_bw, 64);
>
> if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
> int ret = intel_atomic_lock_global_state(&new_bw_state->base);
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 7/9] drm/i915: Properly write lock bw_state when it changes
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
` (5 preceding siblings ...)
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 6/9] drm/i915: Round up when calculating display bandwidth requirements Ville Syrjala
@ 2022-03-03 19:12 ` Ville Syrjala
2022-03-10 7:47 ` Lisovskiy, Stanislav
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix DBUF bandwidth vs. cdclk handling Ville Syrjala
` (5 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2022-03-03 19:12 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The current code also forgets to call intel_atomic_lock_global_state()
when other stuff besides the final min_cdlck changes in the state.
That means we may throw away data which actually has changed, and
thus we can't be at all sure what the code ends up doing during
subsequent commits. Do the write lock properly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 0759bb95ea4b..56eebccd16e2 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -678,6 +678,28 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
return to_intel_bw_state(bw_state);
}
+static bool intel_bw_state_changed(struct drm_i915_private *i915,
+ const struct intel_bw_state *old_bw_state,
+ const struct intel_bw_state *new_bw_state)
+{
+ enum pipe pipe;
+
+ for_each_pipe(i915, pipe) {
+ const struct intel_dbuf_bw *old_crtc_bw =
+ &old_bw_state->dbuf_bw[pipe];
+ const struct intel_dbuf_bw *new_crtc_bw =
+ &new_bw_state->dbuf_bw[pipe];
+ enum dbuf_slice slice;
+
+ for_each_dbuf_slice(i915, slice) {
+ if (old_crtc_bw->used_bw[slice] != new_crtc_bw->used_bw[slice])
+ return true;
+ }
+ }
+
+ return old_bw_state->min_cdclk != new_bw_state->min_cdclk;
+}
+
static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state)
{
@@ -765,7 +787,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
new_bw_state->min_cdclk = DIV_ROUND_UP(max_bw, 64);
- if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
+ if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
int ret = intel_atomic_lock_global_state(&new_bw_state->base);
if (ret)
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH v2 7/9] drm/i915: Properly write lock bw_state when it changes
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 7/9] drm/i915: Properly write lock bw_state when it changes Ville Syrjala
@ 2022-03-10 7:47 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 20+ messages in thread
From: Lisovskiy, Stanislav @ 2022-03-10 7:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Mar 03, 2022 at 09:12:05PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The current code also forgets to call intel_atomic_lock_global_state()
> when other stuff besides the final min_cdlck changes in the state.
> That means we may throw away data which actually has changed, and
> thus we can't be at all sure what the code ends up doing during
> subsequent commits. Do the write lock properly.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 0759bb95ea4b..56eebccd16e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -678,6 +678,28 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
> return to_intel_bw_state(bw_state);
> }
>
> +static bool intel_bw_state_changed(struct drm_i915_private *i915,
> + const struct intel_bw_state *old_bw_state,
> + const struct intel_bw_state *new_bw_state)
> +{
> + enum pipe pipe;
> +
> + for_each_pipe(i915, pipe) {
> + const struct intel_dbuf_bw *old_crtc_bw =
> + &old_bw_state->dbuf_bw[pipe];
> + const struct intel_dbuf_bw *new_crtc_bw =
> + &new_bw_state->dbuf_bw[pipe];
> + enum dbuf_slice slice;
> +
> + for_each_dbuf_slice(i915, slice) {
> + if (old_crtc_bw->used_bw[slice] != new_crtc_bw->used_bw[slice])
> + return true;
> + }
> + }
> +
> + return old_bw_state->min_cdclk != new_bw_state->min_cdclk;
> +}
> +
> static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -765,7 +787,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
>
> new_bw_state->min_cdclk = DIV_ROUND_UP(max_bw, 64);
>
> - if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
> + if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
> int ret = intel_atomic_lock_global_state(&new_bw_state->base);
>
> if (ret)
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix DBUF bandwidth vs. cdclk handling
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
` (6 preceding siblings ...)
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 7/9] drm/i915: Properly write lock bw_state when it changes Ville Syrjala
@ 2022-03-03 19:12 ` Ville Syrjala
2022-03-10 8:22 ` Lisovskiy, Stanislav
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 9/9] drm/i915: Add "maximum pipe read bandwidth" checks Ville Syrjala
` (4 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2022-03-03 19:12 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the dbuf bandwidth min cdclk calculations match the spec
more closely. Supposedly the arbiter can only guarantee an equal
share of the total bandwidth of the slice to each active plane
on that slice. So we take the max bandwidth of any of the planes
on each slice and multiply that by the number of active planes
on the slice to get a worst case estimate on how much bandwidth
we require.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 159 +++++++++++++++------
drivers/gpu/drm/i915/display/intel_bw.h | 10 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 67 ++++-----
drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +
4 files changed, 148 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 56eebccd16e2..ed86f3e3c66c 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -692,12 +692,34 @@ static bool intel_bw_state_changed(struct drm_i915_private *i915,
enum dbuf_slice slice;
for_each_dbuf_slice(i915, slice) {
- if (old_crtc_bw->used_bw[slice] != new_crtc_bw->used_bw[slice])
+ if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
+ old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
return true;
}
}
- return old_bw_state->min_cdclk != new_bw_state->min_cdclk;
+ return false;
+}
+
+static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
+ struct intel_crtc *crtc,
+ enum plane_id plane_id,
+ const struct skl_ddb_entry *ddb,
+ unsigned int data_rate)
+{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
+ unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
+ enum dbuf_slice slice;
+
+ /*
+ * The arbiter can only really guarantee an
+ * equal share of the total bw to each plane.
+ */
+ for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
+ crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
+ crtc_bw->active_planes[slice] |= BIT(plane_id);
+ }
}
static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
@@ -708,46 +730,77 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
enum plane_id plane_id;
- memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
+ memset(crtc_bw, 0, sizeof(*crtc_bw));
if (!crtc_state->hw.active)
return;
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_ddb_entry *ddb =
- &crtc_state->wm.skl.plane_ddb[plane_id];
- unsigned int data_rate = crtc_state->data_rate[plane_id];
- unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
- enum dbuf_slice slice;
-
- for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
- crtc_bw->used_bw[slice] += data_rate;
+ /*
+ * We assume cursors are small enough
+ * to not cause bandwidth problems.
+ */
+ if (plane_id == PLANE_CURSOR)
+ continue;
+
+ skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
+ &crtc_state->wm.skl.plane_ddb[plane_id],
+ crtc_state->data_rate[plane_id]);
+
+ if (DISPLAY_VER(i915) < 11)
+ skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
+ &crtc_state->wm.skl.plane_ddb_y[plane_id],
+ crtc_state->data_rate[plane_id]);
}
+}
+
+/* "Maximum Data Buffer Bandwidth" */
+static int
+intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
+ const struct intel_bw_state *bw_state)
+{
+ unsigned int total_max_bw = 0;
+ enum dbuf_slice slice;
- if (DISPLAY_VER(i915) >= 11)
- return;
+ for_each_dbuf_slice(i915, slice) {
+ int num_active_planes = 0;
+ unsigned int max_bw = 0;
+ enum pipe pipe;
- for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_ddb_entry *ddb =
- &crtc_state->wm.skl.plane_ddb_y[plane_id];
- unsigned int data_rate = crtc_state->data_rate_y[plane_id];
- unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
- enum dbuf_slice slice;
+ /*
+ * The arbiter can only really guarantee an
+ * equal share of the total bw to each plane.
+ */
+ for_each_pipe(i915, pipe) {
+ const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
- for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
- crtc_bw->used_bw[slice] += data_rate;
+ max_bw = max(crtc_bw->max_bw[slice], max_bw);
+ num_active_planes += hweight8(crtc_bw->active_planes[slice]);
+ }
+ max_bw *= num_active_planes;
+
+ total_max_bw = max(total_max_bw, max_bw);
}
+
+ return DIV_ROUND_UP(total_max_bw, 64);
+}
+
+int intel_bw_min_cdclk(struct drm_i915_private *i915,
+ const struct intel_bw_state *bw_state)
+{
+ return intel_bw_dbuf_min_cdclk(i915, bw_state);
}
-int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
+int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
+ bool *need_cdclk_calc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_bw_state *new_bw_state = NULL;
- struct intel_bw_state *old_bw_state = NULL;
+ const struct intel_bw_state *old_bw_state = NULL;
+ const struct intel_cdclk_state *cdclk_state;
const struct intel_crtc_state *crtc_state;
+ int old_min_cdclk, new_min_cdclk;
struct intel_crtc *crtc;
- int max_bw = 0;
- enum pipe pipe;
int i;
if (DISPLAY_VER(dev_priv) < 9)
@@ -766,34 +819,46 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
if (!old_bw_state)
return 0;
- for_each_pipe(dev_priv, pipe) {
- struct intel_dbuf_bw *crtc_bw;
- enum dbuf_slice slice;
-
- crtc_bw = &new_bw_state->dbuf_bw[pipe];
-
- for_each_dbuf_slice(dev_priv, slice) {
- /*
- * Current experimental observations show that contrary
- * to BSpec we get underruns once we exceed 64 * CDCLK
- * for slices in total.
- * As a temporary measure in order not to keep CDCLK
- * bumped up all the time we calculate CDCLK according
- * to this formula for overall bw consumed by slices.
- */
- max_bw += crtc_bw->used_bw[slice];
- }
- }
-
- new_bw_state->min_cdclk = DIV_ROUND_UP(max_bw, 64);
-
if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
int ret = intel_atomic_lock_global_state(&new_bw_state->base);
-
if (ret)
return ret;
}
+ old_min_cdclk = intel_bw_min_cdclk(dev_priv, old_bw_state);
+ new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
+
+ /*
+ * No need to check against the cdclk state if
+ * the min cdclk for the dbuf doesn't increase.
+ *
+ * Ie. we only ever increase the cdclk due to dbuf
+ * requirements. This can reduce back and forth
+ * display blinking due to constant cdclk changes.
+ */
+ if (new_min_cdclk <= old_min_cdclk)
+ return 0;
+
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
+
+ /*
+ * No need to recalculate the cdclk state if
+ * the min cdclk for the dbuf doesn't increase.
+ *
+ * Ie. we only ever increase the cdclk due to dbuf
+ * requirements. This can reduce back and forth
+ * display blinking due to constant cdclk changes.
+ */
+ if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
+ return 0;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
+ new_min_cdclk, cdclk_state->bw_min_cdclk);
+ *need_cdclk_calc = true;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 6acdf1245b3a..92fc09a8c824 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -17,7 +17,8 @@ struct intel_atomic_state;
struct intel_crtc_state;
struct intel_dbuf_bw {
- int used_bw[I915_MAX_DBUF_SLICES];
+ unsigned int max_bw[I915_MAX_DBUF_SLICES];
+ u8 active_planes[I915_MAX_DBUF_SLICES];
};
struct intel_bw_state {
@@ -42,8 +43,6 @@ struct intel_bw_state {
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
-
- int min_cdclk;
};
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
@@ -64,6 +63,9 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask);
-int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
+int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
+ bool *need_cdclk_calc);
+int intel_bw_min_cdclk(struct drm_i915_private *i915,
+ const struct intel_bw_state *bw_state);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 5d0c2f8b0533..b2017d8161b4 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2318,13 +2318,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
dev_priv->max_cdclk_freq));
}
- if (min_cdclk > dev_priv->max_cdclk_freq) {
- drm_dbg_kms(&dev_priv->drm,
- "required cdclk (%d kHz) exceeds max (%d kHz)\n",
- min_cdclk, dev_priv->max_cdclk_freq);
- return -EINVAL;
- }
-
return min_cdclk;
}
@@ -2332,7 +2325,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
{
struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_bw_state *bw_state = NULL;
+ const struct intel_bw_state *bw_state;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
int min_cdclk, i;
@@ -2345,10 +2338,6 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
if (min_cdclk < 0)
return min_cdclk;
- bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
-
if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
continue;
@@ -2359,14 +2348,31 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
return ret;
}
- min_cdclk = cdclk_state->force_min_cdclk;
- for_each_pipe(dev_priv, pipe) {
+ bw_state = intel_atomic_get_new_bw_state(state);
+ if (bw_state) {
+ min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state);
+
+ if (cdclk_state->bw_min_cdclk != min_cdclk) {
+ int ret;
+
+ cdclk_state->bw_min_cdclk = min_cdclk;
+
+ ret = intel_atomic_lock_global_state(&cdclk_state->base);
+ if (ret)
+ return ret;
+ }
+ }
+
+ min_cdclk = max(cdclk_state->force_min_cdclk,
+ cdclk_state->bw_min_cdclk);
+ for_each_pipe(dev_priv, pipe)
min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
- if (!bw_state)
- continue;
-
- min_cdclk = max(bw_state->min_cdclk, min_cdclk);
+ if (min_cdclk > dev_priv->max_cdclk_freq) {
+ drm_dbg_kms(&dev_priv->drm,
+ "required cdclk (%d kHz) exceeds max (%d kHz)\n",
+ min_cdclk, dev_priv->max_cdclk_freq);
+ return -EINVAL;
}
return min_cdclk;
@@ -2647,14 +2653,10 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
int intel_cdclk_atomic_check(struct intel_atomic_state *state,
bool *need_cdclk_calc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_cdclk_state *old_cdclk_state;
const struct intel_cdclk_state *new_cdclk_state;
struct intel_plane_state *plane_state;
- struct intel_bw_state *new_bw_state;
struct intel_plane *plane;
- int min_cdclk = 0;
- enum pipe pipe;
int ret;
int i;
@@ -2669,6 +2671,10 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state,
return ret;
}
+ ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc);
+ if (ret)
+ return ret;
+
old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
@@ -2676,23 +2682,6 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state,
old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
*need_cdclk_calc = true;
- ret = intel_bw_calc_min_cdclk(state);
- if (ret)
- return ret;
-
- new_bw_state = intel_atomic_get_new_bw_state(state);
-
- if (!new_cdclk_state || !new_bw_state)
- return 0;
-
- for_each_pipe(i915, pipe) {
- min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
-
- /* Currently do this change only if we need to increase */
- if (new_bw_state->min_cdclk > min_cdclk)
- *need_cdclk_calc = true;
- }
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index df66f66fbad0..b535cf6a7d9e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -36,6 +36,8 @@ struct intel_cdclk_state {
*/
struct intel_cdclk_config actual;
+ /* minimum acceptable cdclk to satisfy bandwidth requirements */
+ int bw_min_cdclk;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
/* minimum acceptable voltage level for each pipe */
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix DBUF bandwidth vs. cdclk handling
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix DBUF bandwidth vs. cdclk handling Ville Syrjala
@ 2022-03-10 8:22 ` Lisovskiy, Stanislav
2022-03-10 8:59 ` Ville Syrjälä
0 siblings, 1 reply; 20+ messages in thread
From: Lisovskiy, Stanislav @ 2022-03-10 8:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Mar 03, 2022 at 09:12:06PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make the dbuf bandwidth min cdclk calculations match the spec
> more closely. Supposedly the arbiter can only guarantee an equal
> share of the total bandwidth of the slice to each active plane
> on that slice.
So are we assuming or really know this? May be we should ask
Arthur(or may be you did already) because could be it works
somehow differently yet again.
> So we take the max bandwidth of any of the planes
> on each slice and multiply that by the number of active planes
> on the slice to get a worst case estimate on how much bandwidth
> we require.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 159 +++++++++++++++------
> drivers/gpu/drm/i915/display/intel_bw.h | 10 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 67 ++++-----
> drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +
> 4 files changed, 148 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 56eebccd16e2..ed86f3e3c66c 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -692,12 +692,34 @@ static bool intel_bw_state_changed(struct drm_i915_private *i915,
> enum dbuf_slice slice;
>
> for_each_dbuf_slice(i915, slice) {
> - if (old_crtc_bw->used_bw[slice] != new_crtc_bw->used_bw[slice])
> + if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
> + old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
> return true;
> }
> }
>
> - return old_bw_state->min_cdclk != new_bw_state->min_cdclk;
> + return false;
> +}
> +
> +static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
> + struct intel_crtc *crtc,
> + enum plane_id plane_id,
> + const struct skl_ddb_entry *ddb,
> + unsigned int data_rate)
> +{
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
> + unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
> + enum dbuf_slice slice;
> +
> + /*
> + * The arbiter can only really guarantee an
> + * equal share of the total bw to each plane.
> + */
> + for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
> + crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
So does the crtc_bw->max_bw[slice] not store plane data rate which consumes
the most, I guess? Wondering should we name it bit somewhat differently.
Like max_plane_bw or smth, because crtc_bw->max_bw[slice] sounds more like
total bw consumed by slice, but not plane.
> + crtc_bw->active_planes[slice] |= BIT(plane_id);
> + }
> }
>
> static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
> @@ -708,46 +730,77 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
> struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
> enum plane_id plane_id;
>
> - memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
> + memset(crtc_bw, 0, sizeof(*crtc_bw));
>
> if (!crtc_state->hw.active)
> return;
>
> for_each_plane_id_on_crtc(crtc, plane_id) {
> - const struct skl_ddb_entry *ddb =
> - &crtc_state->wm.skl.plane_ddb[plane_id];
> - unsigned int data_rate = crtc_state->data_rate[plane_id];
> - unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
> - enum dbuf_slice slice;
> -
> - for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
> - crtc_bw->used_bw[slice] += data_rate;
> + /*
> + * We assume cursors are small enough
> + * to not cause bandwidth problems.
> + */
> + if (plane_id == PLANE_CURSOR)
> + continue;
> +
> + skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
> + &crtc_state->wm.skl.plane_ddb[plane_id],
> + crtc_state->data_rate[plane_id]);
> +
> + if (DISPLAY_VER(i915) < 11)
> + skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
> + &crtc_state->wm.skl.plane_ddb_y[plane_id],
> + crtc_state->data_rate[plane_id]);
> }
> +}
> +
> +/* "Maximum Data Buffer Bandwidth" */
> +static int
> +intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
> + const struct intel_bw_state *bw_state)
> +{
> + unsigned int total_max_bw = 0;
> + enum dbuf_slice slice;
>
> - if (DISPLAY_VER(i915) >= 11)
> - return;
> + for_each_dbuf_slice(i915, slice) {
> + int num_active_planes = 0;
> + unsigned int max_bw = 0;
> + enum pipe pipe;
>
> - for_each_plane_id_on_crtc(crtc, plane_id) {
> - const struct skl_ddb_entry *ddb =
> - &crtc_state->wm.skl.plane_ddb_y[plane_id];
> - unsigned int data_rate = crtc_state->data_rate_y[plane_id];
> - unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
> - enum dbuf_slice slice;
> + /*
> + * The arbiter can only really guarantee an
> + * equal share of the total bw to each plane.
> + */
> + for_each_pipe(i915, pipe) {
> + const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
>
> - for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
> - crtc_bw->used_bw[slice] += data_rate;
> + max_bw = max(crtc_bw->max_bw[slice], max_bw);
> + num_active_planes += hweight8(crtc_bw->active_planes[slice]);
> + }
> + max_bw *= num_active_planes;
So we are now putting much more strict limitation here. I.e assuming that if there are
lets say planes 1,2,3. Plane 1 consumes 3000, Plane 2 consumes 1000, Plane 3 consumes 1000.
All together they consume 5000 so we kinda derive CDCLK from there(i.e 5000/64)
This is basically what formula also says in the BSpec, i.e it just instruct us
to add all those planes and check that we don't exceed CDCLK * 64 in total.
However now we are going to take plane 1, since it consumes the most and multiply that 3000
by 3, i.e get 9000 instead of 5000, which would result in a way higher CDCLK.
I think you got this assumption from that place in BSpec:
DBUF maximum plane bandwidth MB/s = DBUF maximum pipe bandwidth / number of enabled planes
In fact sounds just about right, would be probably still nice to clarify that from HW
team. I remember we even discussed that long time back in the office days.
Stan
> +
> + total_max_bw = max(total_max_bw, max_bw);
> }
> +
> + return DIV_ROUND_UP(total_max_bw, 64);
> +}
> +
> +int intel_bw_min_cdclk(struct drm_i915_private *i915,
> + const struct intel_bw_state *bw_state)
> +{
> + return intel_bw_dbuf_min_cdclk(i915, bw_state);
> }
>
> -int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
> +int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> + bool *need_cdclk_calc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_bw_state *new_bw_state = NULL;
> - struct intel_bw_state *old_bw_state = NULL;
> + const struct intel_bw_state *old_bw_state = NULL;
> + const struct intel_cdclk_state *cdclk_state;
> const struct intel_crtc_state *crtc_state;
> + int old_min_cdclk, new_min_cdclk;
> struct intel_crtc *crtc;
> - int max_bw = 0;
> - enum pipe pipe;
> int i;
>
> if (DISPLAY_VER(dev_priv) < 9)
> @@ -766,34 +819,46 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
> if (!old_bw_state)
> return 0;
>
> - for_each_pipe(dev_priv, pipe) {
> - struct intel_dbuf_bw *crtc_bw;
> - enum dbuf_slice slice;
> -
> - crtc_bw = &new_bw_state->dbuf_bw[pipe];
> -
> - for_each_dbuf_slice(dev_priv, slice) {
> - /*
> - * Current experimental observations show that contrary
> - * to BSpec we get underruns once we exceed 64 * CDCLK
> - * for slices in total.
> - * As a temporary measure in order not to keep CDCLK
> - * bumped up all the time we calculate CDCLK according
> - * to this formula for overall bw consumed by slices.
> - */
> - max_bw += crtc_bw->used_bw[slice];
> - }
> - }
> -
> - new_bw_state->min_cdclk = DIV_ROUND_UP(max_bw, 64);
> -
> if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
> int ret = intel_atomic_lock_global_state(&new_bw_state->base);
> -
> if (ret)
> return ret;
> }
>
> + old_min_cdclk = intel_bw_min_cdclk(dev_priv, old_bw_state);
> + new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
> +
> + /*
> + * No need to check against the cdclk state if
> + * the min cdclk for the dbuf doesn't increase.
> + *
> + * Ie. we only ever increase the cdclk due to dbuf
> + * requirements. This can reduce back and forth
> + * display blinking due to constant cdclk changes.
> + */
> + if (new_min_cdclk <= old_min_cdclk)
> + return 0;
> +
> + cdclk_state = intel_atomic_get_cdclk_state(state);
> + if (IS_ERR(cdclk_state))
> + return PTR_ERR(cdclk_state);
> +
> + /*
> + * No need to recalculate the cdclk state if
> + * the min cdclk for the dbuf doesn't increase.
> + *
> + * Ie. we only ever increase the cdclk due to dbuf
> + * requirements. This can reduce back and forth
> + * display blinking due to constant cdclk changes.
> + */
> + if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
> + return 0;
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
> + new_min_cdclk, cdclk_state->bw_min_cdclk);
> + *need_cdclk_calc = true;
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 6acdf1245b3a..92fc09a8c824 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -17,7 +17,8 @@ struct intel_atomic_state;
> struct intel_crtc_state;
>
> struct intel_dbuf_bw {
> - int used_bw[I915_MAX_DBUF_SLICES];
> + unsigned int max_bw[I915_MAX_DBUF_SLICES];
> + u8 active_planes[I915_MAX_DBUF_SLICES];
> };
>
> struct intel_bw_state {
> @@ -42,8 +43,6 @@ struct intel_bw_state {
>
> unsigned int data_rate[I915_MAX_PIPES];
> u8 num_active_planes[I915_MAX_PIPES];
> -
> - int min_cdclk;
> };
>
> #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> @@ -64,6 +63,9 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> u32 points_mask);
> -int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
> +int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> + bool *need_cdclk_calc);
> +int intel_bw_min_cdclk(struct drm_i915_private *i915,
> + const struct intel_bw_state *bw_state);
>
> #endif /* __INTEL_BW_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 5d0c2f8b0533..b2017d8161b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2318,13 +2318,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> dev_priv->max_cdclk_freq));
> }
>
> - if (min_cdclk > dev_priv->max_cdclk_freq) {
> - drm_dbg_kms(&dev_priv->drm,
> - "required cdclk (%d kHz) exceeds max (%d kHz)\n",
> - min_cdclk, dev_priv->max_cdclk_freq);
> - return -EINVAL;
> - }
> -
> return min_cdclk;
> }
>
> @@ -2332,7 +2325,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> struct intel_atomic_state *state = cdclk_state->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct intel_bw_state *bw_state = NULL;
> + const struct intel_bw_state *bw_state;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> int min_cdclk, i;
> @@ -2345,10 +2338,6 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> if (min_cdclk < 0)
> return min_cdclk;
>
> - bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> -
> if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
> continue;
>
> @@ -2359,14 +2348,31 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> return ret;
> }
>
> - min_cdclk = cdclk_state->force_min_cdclk;
> - for_each_pipe(dev_priv, pipe) {
> + bw_state = intel_atomic_get_new_bw_state(state);
> + if (bw_state) {
> + min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state);
> +
> + if (cdclk_state->bw_min_cdclk != min_cdclk) {
> + int ret;
> +
> + cdclk_state->bw_min_cdclk = min_cdclk;
> +
> + ret = intel_atomic_lock_global_state(&cdclk_state->base);
> + if (ret)
> + return ret;
> + }
> + }
> +
> + min_cdclk = max(cdclk_state->force_min_cdclk,
> + cdclk_state->bw_min_cdclk);
> + for_each_pipe(dev_priv, pipe)
> min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
>
> - if (!bw_state)
> - continue;
> -
> - min_cdclk = max(bw_state->min_cdclk, min_cdclk);
> + if (min_cdclk > dev_priv->max_cdclk_freq) {
> + drm_dbg_kms(&dev_priv->drm,
> + "required cdclk (%d kHz) exceeds max (%d kHz)\n",
> + min_cdclk, dev_priv->max_cdclk_freq);
> + return -EINVAL;
> }
>
> return min_cdclk;
> @@ -2647,14 +2653,10 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
> int intel_cdclk_atomic_check(struct intel_atomic_state *state,
> bool *need_cdclk_calc)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> const struct intel_cdclk_state *old_cdclk_state;
> const struct intel_cdclk_state *new_cdclk_state;
> struct intel_plane_state *plane_state;
> - struct intel_bw_state *new_bw_state;
> struct intel_plane *plane;
> - int min_cdclk = 0;
> - enum pipe pipe;
> int ret;
> int i;
>
> @@ -2669,6 +2671,10 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state,
> return ret;
> }
>
> + ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc);
> + if (ret)
> + return ret;
> +
> old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
> new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
>
> @@ -2676,23 +2682,6 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state,
> old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
> *need_cdclk_calc = true;
>
> - ret = intel_bw_calc_min_cdclk(state);
> - if (ret)
> - return ret;
> -
> - new_bw_state = intel_atomic_get_new_bw_state(state);
> -
> - if (!new_cdclk_state || !new_bw_state)
> - return 0;
> -
> - for_each_pipe(i915, pipe) {
> - min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
> -
> - /* Currently do this change only if we need to increase */
> - if (new_bw_state->min_cdclk > min_cdclk)
> - *need_cdclk_calc = true;
> - }
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index df66f66fbad0..b535cf6a7d9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -36,6 +36,8 @@ struct intel_cdclk_state {
> */
> struct intel_cdclk_config actual;
>
> + /* minimum acceptable cdclk to satisfy bandwidth requirements */
> + int bw_min_cdclk;
> /* minimum acceptable cdclk for each pipe */
> int min_cdclk[I915_MAX_PIPES];
> /* minimum acceptable voltage level for each pipe */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix DBUF bandwidth vs. cdclk handling
2022-03-10 8:22 ` Lisovskiy, Stanislav
@ 2022-03-10 8:59 ` Ville Syrjälä
2022-03-10 12:37 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjälä @ 2022-03-10 8:59 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Mar 10, 2022 at 10:22:56AM +0200, Lisovskiy, Stanislav wrote:
> On Thu, Mar 03, 2022 at 09:12:06PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Make the dbuf bandwidth min cdclk calculations match the spec
> > more closely. Supposedly the arbiter can only guarantee an equal
> > share of the total bandwidth of the slice to each active plane
> > on that slice.
>
> So are we assuming or really know this? May be we should ask
> Arthur(or may be you did already) because could be it works
> somehow differently yet again.
It's what the spec formula says atm. Also IIRC when I asked Art
about this and he said it's like that to account for the worst
case behaviour of the arbiter.
>
> > So we take the max bandwidth of any of the planes
> > on each slice and multiply that by the number of active planes
> > on the slice to get a worst case estimate on how much bandwidth
> > we require.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 159 +++++++++++++++------
> > drivers/gpu/drm/i915/display/intel_bw.h | 10 +-
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 67 ++++-----
> > drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +
> > 4 files changed, 148 insertions(+), 90 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 56eebccd16e2..ed86f3e3c66c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -692,12 +692,34 @@ static bool intel_bw_state_changed(struct drm_i915_private *i915,
> > enum dbuf_slice slice;
> >
> > for_each_dbuf_slice(i915, slice) {
> > - if (old_crtc_bw->used_bw[slice] != new_crtc_bw->used_bw[slice])
> > + if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
> > + old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
> > return true;
> > }
> > }
> >
> > - return old_bw_state->min_cdclk != new_bw_state->min_cdclk;
> > + return false;
> > +}
> > +
> > +static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
> > + struct intel_crtc *crtc,
> > + enum plane_id plane_id,
> > + const struct skl_ddb_entry *ddb,
> > + unsigned int data_rate)
> > +{
> > + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
> > + unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
> > + enum dbuf_slice slice;
> > +
> > + /*
> > + * The arbiter can only really guarantee an
> > + * equal share of the total bw to each plane.
> > + */
> > + for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
> > + crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
>
> So does the crtc_bw->max_bw[slice] not store plane data rate which consumes
> the most, I guess? Wondering should we name it bit somewhat differently.
> Like max_plane_bw or smth, because crtc_bw->max_bw[slice] sounds more like
> total bw consumed by slice, but not plane.
Naming is hard.
>
> > + crtc_bw->active_planes[slice] |= BIT(plane_id);
> > + }
> > }
> >
> > static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
> > @@ -708,46 +730,77 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
> > struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
> > enum plane_id plane_id;
> >
> > - memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
> > + memset(crtc_bw, 0, sizeof(*crtc_bw));
> >
> > if (!crtc_state->hw.active)
> > return;
> >
> > for_each_plane_id_on_crtc(crtc, plane_id) {
> > - const struct skl_ddb_entry *ddb =
> > - &crtc_state->wm.skl.plane_ddb[plane_id];
> > - unsigned int data_rate = crtc_state->data_rate[plane_id];
> > - unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
> > - enum dbuf_slice slice;
> > -
> > - for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
> > - crtc_bw->used_bw[slice] += data_rate;
> > + /*
> > + * We assume cursors are small enough
> > + * to not cause bandwidth problems.
> > + */
> > + if (plane_id == PLANE_CURSOR)
> > + continue;
> > +
> > + skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
> > + &crtc_state->wm.skl.plane_ddb[plane_id],
> > + crtc_state->data_rate[plane_id]);
> > +
> > + if (DISPLAY_VER(i915) < 11)
> > + skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
> > + &crtc_state->wm.skl.plane_ddb_y[plane_id],
> > + crtc_state->data_rate[plane_id]);
> > }
> > +}
> > +
> > +/* "Maximum Data Buffer Bandwidth" */
> > +static int
> > +intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
> > + const struct intel_bw_state *bw_state)
> > +{
> > + unsigned int total_max_bw = 0;
> > + enum dbuf_slice slice;
> >
> > - if (DISPLAY_VER(i915) >= 11)
> > - return;
> > + for_each_dbuf_slice(i915, slice) {
> > + int num_active_planes = 0;
> > + unsigned int max_bw = 0;
> > + enum pipe pipe;
> >
> > - for_each_plane_id_on_crtc(crtc, plane_id) {
> > - const struct skl_ddb_entry *ddb =
> > - &crtc_state->wm.skl.plane_ddb_y[plane_id];
> > - unsigned int data_rate = crtc_state->data_rate_y[plane_id];
> > - unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
> > - enum dbuf_slice slice;
> > + /*
> > + * The arbiter can only really guarantee an
> > + * equal share of the total bw to each plane.
> > + */
> > + for_each_pipe(i915, pipe) {
> > + const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
> >
> > - for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
> > - crtc_bw->used_bw[slice] += data_rate;
> > + max_bw = max(crtc_bw->max_bw[slice], max_bw);
> > + num_active_planes += hweight8(crtc_bw->active_planes[slice]);
> > + }
> > + max_bw *= num_active_planes;
>
> So we are now putting much more strict limitation here. I.e assuming that if there are
> lets say planes 1,2,3. Plane 1 consumes 3000, Plane 2 consumes 1000, Plane 3 consumes 1000.
>
> All together they consume 5000 so we kinda derive CDCLK from there(i.e 5000/64)
> This is basically what formula also says in the BSpec, i.e it just instruct us
> to add all those planes and check that we don't exceed CDCLK * 64 in total.
>
> However now we are going to take plane 1, since it consumes the most and multiply that 3000
> by 3, i.e get 9000 instead of 5000, which would result in a way higher CDCLK.
>
> I think you got this assumption from that place in BSpec:
>
> DBUF maximum plane bandwidth MB/s = DBUF maximum pipe bandwidth / number of enabled planes
>
> In fact sounds just about right, would be probably still nice to clarify that from HW
> team. I remember we even discussed that long time back in the office days.
Yeah, that bspec formula takes the total available bandwidth for the DBUF
slice, divides that by the number of active planes using the slice, and
checks each plane against that. So should be exactly what I do here,
except in reverse.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix DBUF bandwidth vs. cdclk handling
2022-03-10 8:59 ` Ville Syrjälä
@ 2022-03-10 12:37 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 20+ messages in thread
From: Lisovskiy, Stanislav @ 2022-03-10 12:37 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Mar 10, 2022 at 10:59:16AM +0200, Ville Syrjälä wrote:
> On Thu, Mar 10, 2022 at 10:22:56AM +0200, Lisovskiy, Stanislav wrote:
> > On Thu, Mar 03, 2022 at 09:12:06PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Make the dbuf bandwidth min cdclk calculations match the spec
> > > more closely. Supposedly the arbiter can only guarantee an equal
> > > share of the total bandwidth of the slice to each active plane
> > > on that slice.
> >
> > So are we assuming or really know this? May be we should ask
> > Arthur(or may be you did already) because could be it works
> > somehow differently yet again.
>
> It's what the spec formula says atm. Also IIRC when I asked Art
> about this and he said it's like that to account for the worst
> case behaviour of the arbiter.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> >
> > > So we take the max bandwidth of any of the planes
> > > on each slice and multiply that by the number of active planes
> > > on the slice to get a worst case estimate on how much bandwidth
> > > we require.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_bw.c | 159 +++++++++++++++------
> > > drivers/gpu/drm/i915/display/intel_bw.h | 10 +-
> > > drivers/gpu/drm/i915/display/intel_cdclk.c | 67 ++++-----
> > > drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +
> > > 4 files changed, 148 insertions(+), 90 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> > > index 56eebccd16e2..ed86f3e3c66c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > > @@ -692,12 +692,34 @@ static bool intel_bw_state_changed(struct drm_i915_private *i915,
> > > enum dbuf_slice slice;
> > >
> > > for_each_dbuf_slice(i915, slice) {
> > > - if (old_crtc_bw->used_bw[slice] != new_crtc_bw->used_bw[slice])
> > > + if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
> > > + old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
> > > return true;
> > > }
> > > }
> > >
> > > - return old_bw_state->min_cdclk != new_bw_state->min_cdclk;
> > > + return false;
> > > +}
> > > +
> > > +static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
> > > + struct intel_crtc *crtc,
> > > + enum plane_id plane_id,
> > > + const struct skl_ddb_entry *ddb,
> > > + unsigned int data_rate)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > + struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
> > > + unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
> > > + enum dbuf_slice slice;
> > > +
> > > + /*
> > > + * The arbiter can only really guarantee an
> > > + * equal share of the total bw to each plane.
> > > + */
> > > + for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
> > > + crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
> >
> > So does the crtc_bw->max_bw[slice] not store plane data rate which consumes
> > the most, I guess? Wondering should we name it bit somewhat differently.
> > Like max_plane_bw or smth, because crtc_bw->max_bw[slice] sounds more like
> > total bw consumed by slice, but not plane.
>
> Naming is hard.
>
> >
> > > + crtc_bw->active_planes[slice] |= BIT(plane_id);
> > > + }
> > > }
> > >
> > > static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
> > > @@ -708,46 +730,77 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
> > > struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
> > > enum plane_id plane_id;
> > >
> > > - memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
> > > + memset(crtc_bw, 0, sizeof(*crtc_bw));
> > >
> > > if (!crtc_state->hw.active)
> > > return;
> > >
> > > for_each_plane_id_on_crtc(crtc, plane_id) {
> > > - const struct skl_ddb_entry *ddb =
> > > - &crtc_state->wm.skl.plane_ddb[plane_id];
> > > - unsigned int data_rate = crtc_state->data_rate[plane_id];
> > > - unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
> > > - enum dbuf_slice slice;
> > > -
> > > - for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
> > > - crtc_bw->used_bw[slice] += data_rate;
> > > + /*
> > > + * We assume cursors are small enough
> > > + * to not cause bandwidth problems.
> > > + */
> > > + if (plane_id == PLANE_CURSOR)
> > > + continue;
> > > +
> > > + skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
> > > + &crtc_state->wm.skl.plane_ddb[plane_id],
> > > + crtc_state->data_rate[plane_id]);
> > > +
> > > + if (DISPLAY_VER(i915) < 11)
> > > + skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
> > > + &crtc_state->wm.skl.plane_ddb_y[plane_id],
> > > + crtc_state->data_rate[plane_id]);
> > > }
> > > +}
> > > +
> > > +/* "Maximum Data Buffer Bandwidth" */
> > > +static int
> > > +intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
> > > + const struct intel_bw_state *bw_state)
> > > +{
> > > + unsigned int total_max_bw = 0;
> > > + enum dbuf_slice slice;
> > >
> > > - if (DISPLAY_VER(i915) >= 11)
> > > - return;
> > > + for_each_dbuf_slice(i915, slice) {
> > > + int num_active_planes = 0;
> > > + unsigned int max_bw = 0;
> > > + enum pipe pipe;
> > >
> > > - for_each_plane_id_on_crtc(crtc, plane_id) {
> > > - const struct skl_ddb_entry *ddb =
> > > - &crtc_state->wm.skl.plane_ddb_y[plane_id];
> > > - unsigned int data_rate = crtc_state->data_rate_y[plane_id];
> > > - unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
> > > - enum dbuf_slice slice;
> > > + /*
> > > + * The arbiter can only really guarantee an
> > > + * equal share of the total bw to each plane.
> > > + */
> > > + for_each_pipe(i915, pipe) {
> > > + const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
> > >
> > > - for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
> > > - crtc_bw->used_bw[slice] += data_rate;
> > > + max_bw = max(crtc_bw->max_bw[slice], max_bw);
> > > + num_active_planes += hweight8(crtc_bw->active_planes[slice]);
> > > + }
> > > + max_bw *= num_active_planes;
> >
> > So we are now putting much more strict limitation here. I.e assuming that if there are
> > lets say planes 1,2,3. Plane 1 consumes 3000, Plane 2 consumes 1000, Plane 3 consumes 1000.
> >
> > All together they consume 5000 so we kinda derive CDCLK from there(i.e 5000/64)
> > This is basically what formula also says in the BSpec, i.e it just instruct us
> > to add all those planes and check that we don't exceed CDCLK * 64 in total.
> >
> > However now we are going to take plane 1, since it consumes the most and multiply that 3000
> > by 3, i.e get 9000 instead of 5000, which would result in a way higher CDCLK.
> >
> > I think you got this assumption from that place in BSpec:
> >
> > DBUF maximum plane bandwidth MB/s = DBUF maximum pipe bandwidth / number of enabled planes
> >
> > In fact sounds just about right, would be probably still nice to clarify that from HW
> > team. I remember we even discussed that long time back in the office days.
>
> Yeah, that bspec formula takes the total available bandwidth for the DBUF
> slice, divides that by the number of active planes using the slice, and
> checks each plane against that. So should be exactly what I do here,
> except in reverse.
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 9/9] drm/i915: Add "maximum pipe read bandwidth" checks
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
` (7 preceding siblings ...)
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix DBUF bandwidth vs. cdclk handling Ville Syrjala
@ 2022-03-03 19:12 ` Ville Syrjala
2022-03-10 14:06 ` Lisovskiy, Stanislav
2022-03-03 20:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix bandwith related cdclk calculations (rev2) Patchwork
` (3 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2022-03-03 19:12 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make sure the CDCLK is high enough to support the so called
"maximum pipe read bandwidth" limitation. Specified as
51.2 x CDCLK.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 36 +++++++++++++++++++++----
drivers/gpu/drm/i915/display/intel_bw.h | 1 +
2 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index ed86f3e3c66c..e5e772c4fcfb 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -599,6 +599,18 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
return data_rate;
}
+/* "Maximum Pipe Read Bandwidth" */
+static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ if (DISPLAY_VER(i915) < 12)
+ return 0;
+
+ return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
+}
+
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state)
{
@@ -696,6 +708,9 @@ static bool intel_bw_state_changed(struct drm_i915_private *i915,
old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
return true;
}
+
+ if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])
+ return true;
}
return false;
@@ -788,7 +803,15 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
int intel_bw_min_cdclk(struct drm_i915_private *i915,
const struct intel_bw_state *bw_state)
{
- return intel_bw_dbuf_min_cdclk(i915, bw_state);
+ enum pipe pipe;
+ int min_cdclk;
+
+ min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
+
+ for_each_pipe(i915, pipe)
+ min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
+
+ return min_cdclk;
}
int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
@@ -814,6 +837,9 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
old_bw_state = intel_atomic_get_old_bw_state(state);
skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
+
+ new_bw_state->min_cdclk[crtc->pipe] =
+ intel_bw_crtc_min_cdclk(crtc_state);
}
if (!old_bw_state)
@@ -830,9 +856,9 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
/*
* No need to check against the cdclk state if
- * the min cdclk for the dbuf doesn't increase.
+ * the min cdclk doesn't increase.
*
- * Ie. we only ever increase the cdclk due to dbuf
+ * Ie. we only ever increase the cdclk due to bandwidth
* requirements. This can reduce back and forth
* display blinking due to constant cdclk changes.
*/
@@ -845,9 +871,9 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
/*
* No need to recalculate the cdclk state if
- * the min cdclk for the dbuf doesn't increase.
+ * the min cdclk doesn't increase.
*
- * Ie. we only ever increase the cdclk due to dbuf
+ * Ie. we only ever increase the cdclk due to bandwidth
* requirements. This can reduce back and forth
* display blinking due to constant cdclk changes.
*/
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 92fc09a8c824..cb7ee3a24a58 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -41,6 +41,7 @@ struct intel_bw_state {
*/
u16 qgv_points_mask;
+ int min_cdclk[I915_MAX_PIPES];
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Add "maximum pipe read bandwidth" checks
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 9/9] drm/i915: Add "maximum pipe read bandwidth" checks Ville Syrjala
@ 2022-03-10 14:06 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 20+ messages in thread
From: Lisovskiy, Stanislav @ 2022-03-10 14:06 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Mar 03, 2022 at 09:12:07PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make sure the CDCLK is high enough to support the so called
> "maximum pipe read bandwidth" limitation. Specified as
> 51.2 x CDCLK.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 36 +++++++++++++++++++++----
> drivers/gpu/drm/i915/display/intel_bw.h | 1 +
> 2 files changed, 32 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index ed86f3e3c66c..e5e772c4fcfb 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -599,6 +599,18 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
> return data_rate;
> }
>
> +/* "Maximum Pipe Read Bandwidth" */
> +static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> + if (DISPLAY_VER(i915) < 12)
> + return 0;
> +
> + return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
> +}
> +
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -696,6 +708,9 @@ static bool intel_bw_state_changed(struct drm_i915_private *i915,
> old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
> return true;
> }
> +
> + if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])
> + return true;
> }
>
> return false;
> @@ -788,7 +803,15 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
> int intel_bw_min_cdclk(struct drm_i915_private *i915,
> const struct intel_bw_state *bw_state)
> {
> - return intel_bw_dbuf_min_cdclk(i915, bw_state);
> + enum pipe pipe;
> + int min_cdclk;
> +
> + min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
> +
> + for_each_pipe(i915, pipe)
> + min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
> +
> + return min_cdclk;
> }
>
> int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> @@ -814,6 +837,9 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> old_bw_state = intel_atomic_get_old_bw_state(state);
>
> skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
> +
> + new_bw_state->min_cdclk[crtc->pipe] =
> + intel_bw_crtc_min_cdclk(crtc_state);
> }
>
> if (!old_bw_state)
> @@ -830,9 +856,9 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
>
> /*
> * No need to check against the cdclk state if
> - * the min cdclk for the dbuf doesn't increase.
> + * the min cdclk doesn't increase.
> *
> - * Ie. we only ever increase the cdclk due to dbuf
> + * Ie. we only ever increase the cdclk due to bandwidth
> * requirements. This can reduce back and forth
> * display blinking due to constant cdclk changes.
> */
> @@ -845,9 +871,9 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
>
> /*
> * No need to recalculate the cdclk state if
> - * the min cdclk for the dbuf doesn't increase.
> + * the min cdclk doesn't increase.
> *
> - * Ie. we only ever increase the cdclk due to dbuf
> + * Ie. we only ever increase the cdclk due to bandwidth
> * requirements. This can reduce back and forth
> * display blinking due to constant cdclk changes.
> */
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 92fc09a8c824..cb7ee3a24a58 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -41,6 +41,7 @@ struct intel_bw_state {
> */
> u16 qgv_points_mask;
>
> + int min_cdclk[I915_MAX_PIPES];
> unsigned int data_rate[I915_MAX_PIPES];
> u8 num_active_planes[I915_MAX_PIPES];
> };
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix bandwith related cdclk calculations (rev2)
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
` (8 preceding siblings ...)
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 9/9] drm/i915: Add "maximum pipe read bandwidth" checks Ville Syrjala
@ 2022-03-03 20:00 ` Patchwork
2022-03-03 20:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-03-03 20:00 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Fix bandwith related cdclk calculations (rev2)
URL : https://patchwork.freedesktop.org/series/98975/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c60dc5b8150b drm/i915: Tweak plane ddb allocation tracking
f73e140093bf drm/i915: Split plane data_rate into data_rate+data_rate_y
bf50385f5dac drm/i915: Pre-calculate plane relative data rate
-:399: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#399: FILE: drivers/gpu/drm/i915/intel_pm.c:5154:
+ iter.start + iter.uv_total[plane_id]);
total: 0 errors, 1 warnings, 0 checks, 352 lines checked
3d55cf48c60c drm/i915: Remove total[] and uv_total[] from ddb allocation
a20ee8c5b4c8 drm/i915: Nuke intel_bw_calc_min_cdclk()
fd80e1100608 drm/i915: Round up when calculating display bandwidth requirements
600f71268f91 drm/i915: Properly write lock bw_state when it changes
bf90a2f0ae6e drm/i915: Fix DBUF bandwidth vs. cdclk handling
9ce73d6df0c4 drm/i915: Add "maximum pipe read bandwidth" checks
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix bandwith related cdclk calculations (rev2)
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
` (9 preceding siblings ...)
2022-03-03 20:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix bandwith related cdclk calculations (rev2) Patchwork
@ 2022-03-03 20:01 ` Patchwork
2022-03-03 20:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-04 9:14 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
12 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-03-03 20:01 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Fix bandwith related cdclk calculations (rev2)
URL : https://patchwork.freedesktop.org/series/98975/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix bandwith related cdclk calculations (rev2)
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
` (10 preceding siblings ...)
2022-03-03 20:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-03-03 20:29 ` Patchwork
2022-03-04 9:14 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
12 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-03-03 20:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7452 bytes --]
== Series Details ==
Series: drm/i915: Fix bandwith related cdclk calculations (rev2)
URL : https://patchwork.freedesktop.org/series/98975/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11320 -> Patchwork_22477
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/index.html
Participating hosts (46 -> 42)
------------------------------
Additional (1): fi-icl-u2
Missing (5): fi-bdw-5557u shard-tglu shard-rkl shard-dg1 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22477 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770: NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: [PASS][5] -> [FAIL][6] ([i915#4032])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/bat-dg1-5/igt@i915_pm_rps@basic-api.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/bat-dg1-5/igt@i915_pm_rps@basic-api.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: NOTRUN -> [SKIP][8] ([fdo#109278]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#109285])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([i915#3301])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/fi-icl-u2/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][11] ([i915#4785]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@hugepages:
- {bat-rpls-2}: [DMESG-WARN][13] -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/bat-rpls-2/igt@i915_selftest@live@hugepages.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/bat-rpls-2/igt@i915_selftest@live@hugepages.html
* igt@i915_selftest@live@reset:
- {bat-rpls-2}: [INCOMPLETE][15] ([i915#4983]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/bat-rpls-2/igt@i915_selftest@live@reset.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/bat-rpls-2/igt@i915_selftest@live@reset.html
* igt@i915_selftest@live@vma:
- {bat-rpls-2}: [DMESG-WARN][17] ([i915#4391]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/bat-rpls-2/igt@i915_selftest@live@vma.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/bat-rpls-2/igt@i915_selftest@live@vma.html
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [DMESG-WARN][19] ([i915#5068]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/bat-adlp-6/igt@i915_selftest@live@workarounds.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][21] ([i915#4957]) -> [DMESG-FAIL][22] ([i915#4494] / [i915#4957])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
Build changes
-------------
* Linux: CI_DRM_11320 -> Patchwork_22477
CI-20190529: 20190529
CI_DRM_11320: 6be340ee8f5beae574dae6f5e17a22e67beeff3e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6362: 698695136f8ade2391f2d8f45300eae2df02e947 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22477: 9ce73d6df0c4b85e8af3c732869e744b8342ff23 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9ce73d6df0c4 drm/i915: Add "maximum pipe read bandwidth" checks
bf90a2f0ae6e drm/i915: Fix DBUF bandwidth vs. cdclk handling
600f71268f91 drm/i915: Properly write lock bw_state when it changes
fd80e1100608 drm/i915: Round up when calculating display bandwidth requirements
a20ee8c5b4c8 drm/i915: Nuke intel_bw_calc_min_cdclk()
3d55cf48c60c drm/i915: Remove total[] and uv_total[] from ddb allocation
bf50385f5dac drm/i915: Pre-calculate plane relative data rate
f73e140093bf drm/i915: Split plane data_rate into data_rate+data_rate_y
c60dc5b8150b drm/i915: Tweak plane ddb allocation tracking
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/index.html
[-- Attachment #2: Type: text/html, Size: 8481 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix bandwith related cdclk calculations (rev2)
2022-03-03 19:11 [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
` (11 preceding siblings ...)
2022-03-03 20:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-03-04 9:14 ` Patchwork
12 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-03-04 9:14 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30279 bytes --]
== Series Details ==
Series: drm/i915: Fix bandwith related cdclk calculations (rev2)
URL : https://patchwork.freedesktop.org/series/98975/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11320_full -> Patchwork_22477_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22477_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_schedule@smoketest-all:
- {shard-rkl}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-rkl-2/igt@gem_exec_schedule@smoketest-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-rkl-5/igt@gem_exec_schedule@smoketest-all.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
- {shard-rkl}: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
* {igt@kms_plane_scaling@planes-scaling-unity-scaling}:
- {shard-rkl}: NOTRUN -> [SKIP][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-rkl-5/igt@kms_plane_scaling@planes-scaling-unity-scaling.html
* {igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale}:
- shard-iclb: [PASS][5] -> [SKIP][6] +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-iclb7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
* igt@prime_mmap@test_forked:
- {shard-dg1}: NOTRUN -> [SKIP][7] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-dg1-15/igt@prime_mmap@test_forked.html
Known issues
------------
Here are the changes found in Patchwork_22477_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-apl: ([PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [FAIL][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32]) ([i915#4386]) -> ([PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl8/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl8/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl8/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl1/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl1/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl1/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl1/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl2/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl2/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl7/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl2/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl3/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl3/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl3/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl4/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl4/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl4/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl4/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl6/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl6/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl4/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl6/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl1/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl1/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl1/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl2/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl2/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl2/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl2/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl3/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl3/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl3/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl3/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl4/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl4/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl6/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl6/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl6/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl6/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl6/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl7/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl7/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl7/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl8/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl8/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl8/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl8/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [PASS][58] -> [DMESG-WARN][59] ([i915#180]) +5 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl4/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl2/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109314])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_ctx_sseu@engines:
- shard-snb: NOTRUN -> [SKIP][61] ([fdo#109271]) +5 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-snb5/igt@gem_ctx_sseu@engines.html
* igt@gem_exec_balancer@parallel:
- shard-iclb: NOTRUN -> [SKIP][62] ([i915#4525])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb3/igt@gem_exec_balancer@parallel.html
- shard-tglb: NOTRUN -> [DMESG-WARN][63] ([i915#5076])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-tglb2/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-kbl: NOTRUN -> [DMESG-WARN][64] ([i915#5076])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl3/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: NOTRUN -> [FAIL][65] ([i915#2846])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][66] -> [FAIL][67] ([i915#2842])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-glk: [PASS][68] -> [FAIL][69] ([i915#2842]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][70] -> [FAIL][71] ([i915#2842])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-apl8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [PASS][72] -> [FAIL][73] ([i915#2842])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2190])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl7/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#4613])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl6/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@verify-random:
- shard-skl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#4613])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pxp@fail-invalid-protected-context:
- shard-iclb: NOTRUN -> [SKIP][77] ([i915#4270])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@gem_pxp@fail-invalid-protected-context.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#768])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271]) +102 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl3/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [PASS][80] -> [DMESG-WARN][81] ([i915#1436] / [i915#716])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-skl10/igt@gen9_exec_parse@allowed-all.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl7/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][82] ([i915#2856])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@gen9_exec_parse@batch-without-end.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][83] -> [FAIL][84] ([i915#454])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][85] -> [SKIP][86] ([i915#4281])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-iclb8/igt@i915_pm_dc@dc9-dpms.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#110892])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-iclb: NOTRUN -> [SKIP][88] ([fdo#109303])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@i915_query@query-topology-known-pci-ids.html
* igt@i915_selftest@live@execlists:
- shard-skl: [PASS][89] -> [INCOMPLETE][90] ([i915#4547])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-skl4/igt@i915_selftest@live@execlists.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl1/igt@i915_selftest@live@execlists.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][91] -> [FAIL][92] ([i915#2521])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [PASS][93] -> [DMESG-WARN][94] ([i915#118])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-glk6/igt@kms_big_fb@linear-32bpp-rotate-0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-glk6/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#110725] / [fdo#111614]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb3/igt@kms_big_fb@linear-64bpp-rotate-270.html
- shard-tglb: NOTRUN -> [SKIP][96] ([fdo#111614])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-tglb2/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-kbl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#3777]) +2 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][98] ([fdo#110723])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271]) +111 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#3886]) +6 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl6/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#3886]) +8 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109278] / [i915#3886]) +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#3886]) +4 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][104] ([i915#3689]) +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-tglb5/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html
* igt@kms_chamelium@dp-crc-fast:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109284] / [fdo#111827]) +4 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb3/igt@kms_chamelium@dp-crc-fast.html
- shard-tglb: NOTRUN -> [SKIP][106] ([fdo#109284] / [fdo#111827])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-tglb2/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-skl: NOTRUN -> [SKIP][107] ([fdo#109271] / [fdo#111827]) +7 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@vga-edid-read:
- shard-apl: NOTRUN -> [SKIP][108] ([fdo#109271] / [fdo#111827]) +9 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl3/igt@kms_chamelium@vga-edid-read.html
* igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-kbl: NOTRUN -> [SKIP][109] ([fdo#109271] / [fdo#111827]) +8 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl3/igt@kms_color_chamelium@pipe-d-ctm-max.html
* igt@kms_content_protection@content_type_change:
- shard-iclb: NOTRUN -> [SKIP][110] ([fdo#109300] / [fdo#111066])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][111] ([i915#1319])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl7/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][112] ([i915#2105])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl4/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][113] ([fdo#109278] / [fdo#109279])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: [PASS][114] -> [DMESG-WARN][115] ([i915#180])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-top-edge:
- shard-iclb: NOTRUN -> [SKIP][116] ([fdo#109278]) +12 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@kms_cursor_edge_walk@pipe-d-128x128-top-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [FAIL][117] ([i915#2346] / [i915#533])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-iclb: NOTRUN -> [SKIP][118] ([fdo#109274]) +2 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][119] -> [FAIL][120] ([i915#2122])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-glk6/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-glk6/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@b-vga1:
- shard-snb: [PASS][121] -> [DMESG-WARN][122] ([i915#5090])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-snb5/igt@kms_flip@flip-vs-suspend@b-vga1.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-snb4/igt@kms_flip@flip-vs-suspend@b-vga1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-glk: [PASS][123] -> [FAIL][124] ([i915#4911])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-glk4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][125] ([fdo#109271]) +84 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render:
- shard-iclb: NOTRUN -> [SKIP][126] ([fdo#109280]) +11 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move:
- shard-tglb: NOTRUN -> [SKIP][127] ([fdo#109280] / [fdo#111825]) +2 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-tglb5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-tglb: NOTRUN -> [SKIP][128] ([fdo#109289])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-tglb3/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][129] ([fdo#109271] / [i915#533])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl3/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#533])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
- shard-kbl: NOTRUN -> [SKIP][131] ([fdo#109271] / [i915#533])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: NOTRUN -> [FAIL][132] ([fdo#108145] / [i915#265])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][133] ([fdo#108145] / [i915#265])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][134] -> [FAIL][135] ([fdo#108145] / [i915#265])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][136] ([fdo#108145] / [i915#265]) +1 similar issue
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][137] ([i915#265])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl3/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-b-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][138] ([i915#3536])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@kms_plane_lowres@pipe-b-tiling-x.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-skl: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#658]) +1 similar issue
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][140] ([fdo#109271] / [i915#658]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-kbl: NOTRUN -> [SKIP][141] ([fdo#109271] / [i915#658])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl1/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: NOTRUN -> [SKIP][142] ([fdo#109642] / [fdo#111068] / [i915#658])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> [FAIL][143] ([IGT#2])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl3/igt@kms_sysfs_edid_timing.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][144] ([fdo#109271] / [i915#2437])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl6/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-skl: NOTRUN -> [SKIP][145] ([fdo#109271] / [i915#2437])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][146] ([fdo#109271] / [i915#2437]) +1 similar issue
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl3/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-b-ctx-flip-detection:
- shard-iclb: NOTRUN -> [SKIP][147] ([i915#2530])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@nouveau_crc@pipe-b-ctx-flip-detection.html
* igt@nouveau_crc@pipe-c-source-outp-complete:
- shard-tglb: NOTRUN -> [SKIP][148] ([i915#2530])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-tglb3/igt@nouveau_crc@pipe-c-source-outp-complete.html
* igt@sysfs_clients@fair-3:
- shard-skl: NOTRUN -> [SKIP][149] ([fdo#109271] / [i915#2994]) +1 similar issue
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-skl6/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@fair-7:
- shard-kbl: NOTRUN -> [SKIP][150] ([fdo#109271] / [i915#2994])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-kbl3/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@sema-25:
- shard-iclb: NOTRUN -> [SKIP][151] ([i915#2994])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb7/igt@sysfs_clients@sema-25.html
* igt@sysfs_clients@split-50:
- shard-apl: NOTRUN -> [SKIP][152] ([fdo#109271] / [i915#2994])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-apl3/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@fbdev@unaligned-read:
- {shard-rkl}: [SKIP][153] ([i915#2582]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-rkl-5/igt@fbdev@unaligned-read.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-rkl-6/igt@fbdev@unaligned-read.html
* igt@gem_eio@in-flight-contexts-10ms:
- {shard-tglu}: [TIMEOUT][155] ([i915#3063]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-tglu-2/igt@gem_eio@in-flight-contexts-10ms.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-tglu-5/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][157] ([i915#2481] / [i915#3070]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-iclb6/igt@gem_eio@unwedge-stress.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/shard-iclb8/igt@gem_eio@unwedge-stress.html
- {shard-rkl}: [TIMEOUT][159] ([i915#3063]) -> [PASS][160]
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11320/shard-rkl-4/igt@gem_eio@unwedge-stress.html
[160]: https://intel-gfx-ci.01
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22477/index.html
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