[Intel-gfx] [PATCH v6 0/6] High refresh rate PSR fixes

[Intel-gfx] [PATCH v6 0/6] High refresh rate PSR fixes

[Jouni Högander]

Fix/adjust Wa_16013835468 and implement Wa_14015648006. Implement Wa_1136 and
check for vblank being long enough for psr2.

v6:
 - Handle mode change in psr enable/disable
 - Handle wm_level_disable changes separately in pre plane hook
 - Handle WA #1136 in pre/post plane hooks
v5:
 - Add missing patch
v4:
 - Keep/fix Wa_16013835468
 - Use calculated block count number instead of fixed 12
v3:
 - apply Wa_16013835468 for icl as well
 - set/clear chicken bit in post plane update
 - Unify pre/post hooks
v2: Implement Wa_1136

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>

Jouni Högander (6):
  drm/i915/psr: Unify pre/post hooks
  drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006
  drm/i915/psr: Implement Wa_14015648006
  drm/i915/psr: Add helpers for block count number handling
  drm/i915/psr: Check that vblank is long enough for psr2
  drm/i915/psr: Implement Display WA #1136

 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 88 +++++++++++++++----
 drivers/gpu/drm/i915/display/skl_watermark.c  |  6 +-
 3 files changed, 72 insertions(+), 23 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH v6 1/6] drm/i915/psr: Unify pre/post hooks

[Jouni Högander]

pre/post hooks are doing things differently. Unify them.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 31084d95711d..8dbf452d63c2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1954,23 +1954,22 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
 					     crtc_state->uapi.encoder_mask) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 		struct intel_psr *psr = &intel_dp->psr;
+		bool keep_disabled = false;
 
 		mutex_lock(&psr->lock);
 
-		if (psr->sink_not_reliable)
-			goto exit;
-
 		drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes);
 
-		/* Only enable if there is active planes */
-		if (!psr->enabled && crtc_state->active_planes)
+		keep_disabled |= psr->sink_not_reliable;
+		keep_disabled |= !crtc_state->active_planes;
+
+		if (!psr->enabled && !keep_disabled)
 			intel_psr_enable_locked(intel_dp, crtc_state);
 
 		/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
 		if (crtc_state->crc_enabled && psr->enabled)
 			psr_force_hw_tracking_exit(intel_dp);
 
-exit:
 		mutex_unlock(&psr->lock);
 	}
 }
-- 
2.34.1

[Intel-gfx] [PATCH v6 2/6] drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006

[Jouni Högander]

Wa_16013835468 is a separate from Wa_14015648006 and needs to be
applied for TGL onwards. Fix this by removing all the references to
Wa_14015648006 and apply Wa_16013835468 according to Bspec.

Also move workaround into separate function as a preparation for
Wa_14015648006 implementation.

Bspec: 55378

v2:
 - keep applying the wa in intel_psr_enable_source

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 35 ++++++++++++++++--------
 1 file changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8dbf452d63c2..26ad4365960f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1134,6 +1134,28 @@ static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
 	}
 }
 
+/*
+ * Wa_16013835468
+ */
+static void wm_optimization_wa(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	bool set_wa_bit = false;
+
+	/* Wa_16013835468 */
+	if (DISPLAY_VER(dev_priv) >= 12)
+		set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start !=
+			crtc_state->hw.adjusted_mode.crtc_vdisplay;
+
+	if (set_wa_bit)
+		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
+			     wa_16013835468_bit_get(intel_dp));
+	else
+		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
+			     wa_16013835468_bit_get(intel_dp), 0);
+}
+
 static void intel_psr_enable_source(struct intel_dp *intel_dp,
 				    const struct intel_crtc_state *crtc_state)
 {
@@ -1175,15 +1197,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 
 	/*
 	 * Wa_16013835468
-	 * Wa_14015648006
 	 */
-	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
-	    IS_DISPLAY_VER(dev_priv, 12, 13)) {
-		if (crtc_state->hw.adjusted_mode.crtc_vblank_start !=
-		    crtc_state->hw.adjusted_mode.crtc_vdisplay)
-			intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
-				     wa_16013835468_bit_get(intel_dp));
-	}
+	wm_optimization_wa(intel_dp, crtc_state);
 
 	if (intel_dp->psr.psr2_enabled) {
 		if (DISPLAY_VER(dev_priv) == 9)
@@ -1359,10 +1374,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	/*
 	 * Wa_16013835468
-	 * Wa_14015648006
 	 */
-	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
-	    IS_DISPLAY_VER(dev_priv, 12, 13))
+	if (DISPLAY_VER(dev_priv) >= 12)
 		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
 			     wa_16013835468_bit_get(intel_dp), 0);
 
-- 
2.34.1

[Intel-gfx] [PATCH v6 3/6] drm/i915/psr: Implement Wa_14015648006

[Jouni Högander]

PSR WM optimization should be disabled based on any wm level being
disabled. Also same WA should be applied for ICL as well.

Bspec: 71580

v4:
 - Handle mode change in psr enable/disable
 - Handle wm_level_disable changes separately in pre plane hook
v3:
 - Split patch
v2:
 - set/clear chicken bit in post_plane_update
 - apply for ICL as well

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c           | 14 +++++++++++++-
 drivers/gpu/drm/i915/display/skl_watermark.c       |  7 +++++--
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ab146b5b68bd..4236ad751c2c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1157,6 +1157,7 @@ struct intel_crtc_state {
 	bool has_psr2;
 	bool enable_psr2_sel_fetch;
 	bool req_psr2_sdp_prior_scanline;
+	bool wm_level_disabled;
 	u32 dc3co_exitline;
 	u16 su_y_granularity;
 	struct drm_dp_vsc_sdp psr_vsc;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 26ad4365960f..9c416b301555 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1136,6 +1136,7 @@ static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
 
 /*
  * Wa_16013835468
+ * Wa_14015648006
  */
 static void wm_optimization_wa(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state)
@@ -1143,6 +1144,11 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	bool set_wa_bit = false;
 
+	/* Wa_14015648006 */
+	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	    IS_DISPLAY_VER(dev_priv, 11, 13))
+		set_wa_bit |= crtc_state->wm_level_disabled;
+
 	/* Wa_16013835468 */
 	if (DISPLAY_VER(dev_priv) >= 12)
 		set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start !=
@@ -1197,6 +1203,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 
 	/*
 	 * Wa_16013835468
+	 * Wa_14015648006
 	 */
 	wm_optimization_wa(intel_dp, crtc_state);
 
@@ -1374,8 +1381,9 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	/*
 	 * Wa_16013835468
+	 * Wa_14015648006
 	 */
-	if (DISPLAY_VER(dev_priv) >= 12)
+	if (DISPLAY_VER(dev_priv) >= 11)
 		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
 			     wa_16013835468_bit_get(intel_dp), 0);
 
@@ -1949,6 +1957,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 
 		if (psr->enabled && needs_to_disable)
 			intel_psr_disable_locked(intel_dp);
+		else if (psr->enabled && old_crtc_state->wm_level_disabled !=
+			 new_crtc_state->wm_level_disabled)
+			/* Wa_14015648006 */
+			wm_optimization_wa(intel_dp, new_crtc_state);
 
 		mutex_unlock(&psr->lock);
 	}
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index ff70225c0263..7e2e76afbf2a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2276,9 +2276,12 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 		return level;
 
 	/*
-	 * FIXME PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
+	 * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
 	 * based on whether we're limited by the vblank duration.
-	 *
+	 */
+	crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
+
+	/*
 	 * FIXME also related to skl+ w/a 1136 (also unimplemented as of
 	 * now) perhaps?
 	 */
-- 
2.34.1

[Intel-gfx] [PATCH v6 4/6] drm/i915/psr: Add helpers for block count number handling

[Jouni Högander]

Add helpers to make it more clear how PSR2_CTL[Block Count Number]
is configured.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9c416b301555..28d06e347fe6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -519,6 +519,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 	return val;
 }
 
+static int psr2_block_count_lines(struct intel_dp *intel_dp)
+{
+	return intel_dp->psr.io_wake_lines < 9 &&
+		intel_dp->psr.fast_wake_lines < 9 ? 8 : 12;
+}
+
+static int psr2_block_count(struct intel_dp *intel_dp)
+{
+	return psr2_block_count_lines(intel_dp) / 4;
+}
+
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -536,11 +547,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	val |= intel_psr2_get_tp_time(intel_dp);
 
 	if (DISPLAY_VER(dev_priv) >= 12) {
-		if (intel_dp->psr.io_wake_lines < 9 &&
-		    intel_dp->psr.fast_wake_lines < 9)
-			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
-		else
+		if (psr2_block_count(intel_dp) > 2)
 			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3;
+		else
+			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
 	}
 
 	/* Wa_22012278275:adl-p */
-- 
2.34.1

[Intel-gfx] [PATCH v6 5/6] drm/i915/psr: Check that vblank is long enough for psr2

[Jouni Högander]

Ensure vblank >= psr2 vblank
where
Psr2 vblank = PSR2_CTL Block Count Number maximum line count.

Bspec: 71580, 49274

v2: Use calculated block count number maximum line count

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 28d06e347fe6..f86d9f83429f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -968,6 +968,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	/* Vblank >= PSR2_CTL Block Count Number maximum line count */
+	if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
+	    crtc_state->hw.adjusted_mode.crtc_vblank_start <
+	    psr2_block_count_lines(intel_dp)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "PSR2 not enabled, too short vblank time\n");
+		return false;
+	}
+
 	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 		if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
 		    !HAS_PSR_HW_TRACKING(dev_priv)) {
-- 
2.34.1

[Intel-gfx] [PATCH v6 6/6] drm/i915/psr: Implement Display WA #1136

[Jouni Högander]

Implement Display WA #1136 for SKL/BXT.

Bspec: 21664

v2: Handle disable psr in pre/post plane hooks

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c     | 7 +++++++
 drivers/gpu/drm/i915/display/skl_watermark.c | 5 -----
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f86d9f83429f..52f73c65d365 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1968,11 +1968,14 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 		 * - PSR disabled in new state
 		 * - All planes will go inactive
 		 * - Changing between PSR versions
+		 * - Display WA #1136: skl, bxt
 		 */
 		needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
 		needs_to_disable |= !new_crtc_state->has_psr;
 		needs_to_disable |= !new_crtc_state->active_planes;
 		needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;
+		needs_to_disable |= DISPLAY_VER(i915) < 11 &&
+			new_crtc_state->wm_level_disabled;
 
 		if (psr->enabled && needs_to_disable)
 			intel_psr_disable_locked(intel_dp);
@@ -2007,6 +2010,10 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
 		keep_disabled |= psr->sink_not_reliable;
 		keep_disabled |= !crtc_state->active_planes;
 
+		/* Display WA #1136: skl, bxt */
+		keep_disabled |= DISPLAY_VER(dev_priv) < 11 &&
+			crtc_state->wm_level_disabled;
+
 		if (!psr->enabled && !keep_disabled)
 			intel_psr_enable_locked(intel_dp, crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 7e2e76afbf2a..5296a20d62d3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2281,11 +2281,6 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 	 */
 	crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
 
-	/*
-	 * FIXME also related to skl+ w/a 1136 (also unimplemented as of
-	 * now) perhaps?
-	 */
-
 	for (level++; level < i915->display.wm.num_levels; level++) {
 		enum plane_id plane_id;
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH v6 2/6] drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006

[Ville Syrjälä]

On Wed, Mar 29, 2023 at 12:45:28PM +0300, Jouni Högander wrote:
> Wa_16013835468 is a separate from Wa_14015648006 and needs to be
> applied for TGL onwards. Fix this by removing all the references to
> Wa_14015648006 and apply Wa_16013835468 according to Bspec.
> 
> Also move workaround into separate function as a preparation for
> Wa_14015648006 implementation.
> 
> Bspec: 55378
> 
> v2:
>  - keep applying the wa in intel_psr_enable_source
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 35 ++++++++++++++++--------
>  1 file changed, 24 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8dbf452d63c2..26ad4365960f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1134,6 +1134,28 @@ static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
>  	}
>  }
>  
> +/*
> + * Wa_16013835468
> + */
> +static void wm_optimization_wa(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	bool set_wa_bit = false;
> +
> +	/* Wa_16013835468 */
> +	if (DISPLAY_VER(dev_priv) >= 12)

Looks like this should actually be == 12

> +		set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start !=
> +			crtc_state->hw.adjusted_mode.crtc_vdisplay;
> +
> +	if (set_wa_bit)
> +		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,

Can you drop that 0 to the next line so the two branches
at least looks a bit more alike?

Alternatively
intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
	     wa_16013835468_bit_get(intel_dp),
	     set_wa_bit ? wa_16013835468_bit_get(intel_dp) : 0);
or something along those lines.

> +			     wa_16013835468_bit_get(intel_dp));
> +	else
> +		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> +			     wa_16013835468_bit_get(intel_dp), 0);
> +}
> +
>  static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  				    const struct intel_crtc_state *crtc_state)
>  {
> @@ -1175,15 +1197,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  
>  	/*
>  	 * Wa_16013835468
> -	 * Wa_14015648006
>  	 */
> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> -	    IS_DISPLAY_VER(dev_priv, 12, 13)) {
> -		if (crtc_state->hw.adjusted_mode.crtc_vblank_start !=
> -		    crtc_state->hw.adjusted_mode.crtc_vdisplay)
> -			intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> -				     wa_16013835468_bit_get(intel_dp));
> -	}
> +	wm_optimization_wa(intel_dp, crtc_state);
>  
>  	if (intel_dp->psr.psr2_enabled) {
>  		if (DISPLAY_VER(dev_priv) == 9)
> @@ -1359,10 +1374,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  
>  	/*
>  	 * Wa_16013835468
> -	 * Wa_14015648006
>  	 */
> -	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> -	    IS_DISPLAY_VER(dev_priv, 12, 13))
> +	if (DISPLAY_VER(dev_priv) >= 12)
>  		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
>  			     wa_16013835468_bit_get(intel_dp), 0);
>  
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v6 3/6] drm/i915/psr: Implement Wa_14015648006

[Ville Syrjälä]

On Wed, Mar 29, 2023 at 12:45:29PM +0300, Jouni Högander wrote:
> PSR WM optimization should be disabled based on any wm level being
> disabled. Also same WA should be applied for ICL as well.
> 
> Bspec: 71580
> 
> v4:
>  - Handle mode change in psr enable/disable
>  - Handle wm_level_disable changes separately in pre plane hook
> v3:
>  - Split patch
> v2:
>  - set/clear chicken bit in post_plane_update
>  - apply for ICL as well
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c           | 14 +++++++++++++-
>  drivers/gpu/drm/i915/display/skl_watermark.c       |  7 +++++--
>  3 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ab146b5b68bd..4236ad751c2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1157,6 +1157,7 @@ struct intel_crtc_state {
>  	bool has_psr2;
>  	bool enable_psr2_sel_fetch;
>  	bool req_psr2_sdp_prior_scanline;
> +	bool wm_level_disabled;
>  	u32 dc3co_exitline;
>  	u16 su_y_granularity;
>  	struct drm_dp_vsc_sdp psr_vsc;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 26ad4365960f..9c416b301555 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1136,6 +1136,7 @@ static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
>  
>  /*
>   * Wa_16013835468
> + * Wa_14015648006
>   */
>  static void wm_optimization_wa(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state)
> @@ -1143,6 +1144,11 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	bool set_wa_bit = false;
>  
> +	/* Wa_14015648006 */
> +	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	    IS_DISPLAY_VER(dev_priv, 11, 13))
> +		set_wa_bit |= crtc_state->wm_level_disabled;
> +
>  	/* Wa_16013835468 */
>  	if (DISPLAY_VER(dev_priv) >= 12)
>  		set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start !=
> @@ -1197,6 +1203,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  
>  	/*
>  	 * Wa_16013835468
> +	 * Wa_14015648006
>  	 */
>  	wm_optimization_wa(intel_dp, crtc_state);
>  
> @@ -1374,8 +1381,9 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  
>  	/*
>  	 * Wa_16013835468
> +	 * Wa_14015648006
>  	 */
> -	if (DISPLAY_VER(dev_priv) >= 12)
> +	if (DISPLAY_VER(dev_priv) >= 11)
>  		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
>  			     wa_16013835468_bit_get(intel_dp), 0);
>  
> @@ -1949,6 +1957,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
>  
>  		if (psr->enabled && needs_to_disable)
>  			intel_psr_disable_locked(intel_dp);
> +		else if (psr->enabled && old_crtc_state->wm_level_disabled !=
> +			 new_crtc_state->wm_level_disabled)
> +			/* Wa_14015648006 */
> +			wm_optimization_wa(intel_dp, new_crtc_state);

This can now also clear the bit, which is the wrong thing
to do in pre_plane_update().

>  
>  		mutex_unlock(&psr->lock);
>  	}
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index ff70225c0263..7e2e76afbf2a 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2276,9 +2276,12 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
>  		return level;
>  
>  	/*
> -	 * FIXME PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
> +	 * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
>  	 * based on whether we're limited by the vblank duration.
> -	 *
> +	 */
> +	crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
> +
> +	/*
>  	 * FIXME also related to skl+ w/a 1136 (also unimplemented as of
>  	 * now) perhaps?
>  	 */
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v6 3/6] drm/i915/psr: Implement Wa_14015648006

[Hogander, Jouni]

On Wed, 2023-03-29 at 14:44 +0300, Ville Syrjälä wrote:
> On Wed, Mar 29, 2023 at 12:45:29PM +0300, Jouni Högander wrote:
> > PSR WM optimization should be disabled based on any wm level being
> > disabled. Also same WA should be applied for ICL as well.
> > 
> > Bspec: 71580
> > 
> > v4:
> >  - Handle mode change in psr enable/disable
> >  - Handle wm_level_disable changes separately in pre plane hook
> > v3:
> >  - Split patch
> > v2:
> >  - set/clear chicken bit in post_plane_update
> >  - apply for ICL as well
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
> >  drivers/gpu/drm/i915/display/intel_psr.c           | 14
> > +++++++++++++-
> >  drivers/gpu/drm/i915/display/skl_watermark.c       |  7 +++++--
> >  3 files changed, 19 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index ab146b5b68bd..4236ad751c2c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1157,6 +1157,7 @@ struct intel_crtc_state {
> >         bool has_psr2;
> >         bool enable_psr2_sel_fetch;
> >         bool req_psr2_sdp_prior_scanline;
> > +       bool wm_level_disabled;
> >         u32 dc3co_exitline;
> >         u16 su_y_granularity;
> >         struct drm_dp_vsc_sdp psr_vsc;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 26ad4365960f..9c416b301555 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1136,6 +1136,7 @@ static u32 wa_16013835468_bit_get(struct
> > intel_dp *intel_dp)
> >  
> >  /*
> >   * Wa_16013835468
> > + * Wa_14015648006
> >   */
> >  static void wm_optimization_wa(struct intel_dp *intel_dp,
> >                                const struct intel_crtc_state
> > *crtc_state)
> > @@ -1143,6 +1144,11 @@ static void wm_optimization_wa(struct
> > intel_dp *intel_dp,
> >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >         bool set_wa_bit = false;
> >  
> > +       /* Wa_14015648006 */
> > +       if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > +           IS_DISPLAY_VER(dev_priv, 11, 13))
> > +               set_wa_bit |= crtc_state->wm_level_disabled;
> > +
> >         /* Wa_16013835468 */
> >         if (DISPLAY_VER(dev_priv) >= 12)
> >                 set_wa_bit |= crtc_state-
> > >hw.adjusted_mode.crtc_vblank_start !=
> > @@ -1197,6 +1203,7 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> >  
> >         /*
> >          * Wa_16013835468
> > +        * Wa_14015648006
> >          */
> >         wm_optimization_wa(intel_dp, crtc_state);
> >  
> > @@ -1374,8 +1381,9 @@ static void intel_psr_disable_locked(struct
> > intel_dp *intel_dp)
> >  
> >         /*
> >          * Wa_16013835468
> > +        * Wa_14015648006
> >          */
> > -       if (DISPLAY_VER(dev_priv) >= 12)
> > +       if (DISPLAY_VER(dev_priv) >= 11)
> >                 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> >                              wa_16013835468_bit_get(intel_dp), 0);
> >  
> > @@ -1949,6 +1957,10 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> >  
> >                 if (psr->enabled && needs_to_disable)
> >                         intel_psr_disable_locked(intel_dp);
> > +               else if (psr->enabled && old_crtc_state-
> > >wm_level_disabled !=
> > +                        new_crtc_state->wm_level_disabled)
> > +                       /* Wa_14015648006 */
> > +                       wm_optimization_wa(intel_dp,
> > new_crtc_state);
> 
> This can now also clear the bit, which is the wrong thing
> to do in pre_plane_update().

Yes, you are right, I will fix this.
> 
> >  
> >                 mutex_unlock(&psr->lock);
> >         }
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index ff70225c0263..7e2e76afbf2a 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -2276,9 +2276,12 @@ static int skl_wm_check_vblank(struct
> > intel_crtc_state *crtc_state)
> >                 return level;
> >  
> >         /*
> > -        * FIXME PSR needs to toggle
> > LATENCY_REPORTING_REMOVED_PIPE_*
> > +        * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
> >          * based on whether we're limited by the vblank duration.
> > -        *
> > +        */
> > +       crtc_state->wm_level_disabled = level < i915-
> > >display.wm.num_levels - 1;
> > +
> > +       /*
> >          * FIXME also related to skl+ w/a 1136 (also unimplemented
> > as of
> >          * now) perhaps?
> >          */
> > -- 
> > 2.34.1
> 

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915/psr: Implement Display WA #1136

[Ville Syrjälä]

On Wed, Mar 29, 2023 at 12:45:32PM +0300, Jouni Högander wrote:
> Implement Display WA #1136 for SKL/BXT.

Pre-ICL is more accurate now.

Maybe also mention here that the chicken bit approach
might work for KBL+ but implementing that is left
out for the time being.

> 
> Bspec: 21664
> 
> v2: Handle disable psr in pre/post plane hooks
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c     | 7 +++++++
>  drivers/gpu/drm/i915/display/skl_watermark.c | 5 -----
>  2 files changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index f86d9f83429f..52f73c65d365 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1968,11 +1968,14 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
>  		 * - PSR disabled in new state
>  		 * - All planes will go inactive
>  		 * - Changing between PSR versions
> +		 * - Display WA #1136: skl, bxt
>  		 */
>  		needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
>  		needs_to_disable |= !new_crtc_state->has_psr;
>  		needs_to_disable |= !new_crtc_state->active_planes;
>  		needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;
> +		needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> +			new_crtc_state->wm_level_disabled;
>  
>  		if (psr->enabled && needs_to_disable)
>  			intel_psr_disable_locked(intel_dp);
> @@ -2007,6 +2010,10 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
>  		keep_disabled |= psr->sink_not_reliable;
>  		keep_disabled |= !crtc_state->active_planes;
>  
> +		/* Display WA #1136: skl, bxt */
> +		keep_disabled |= DISPLAY_VER(dev_priv) < 11 &&
> +			crtc_state->wm_level_disabled;
> +
>  		if (!psr->enabled && !keep_disabled)
>  			intel_psr_enable_locked(intel_dp, crtc_state);
>  
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 7e2e76afbf2a..5296a20d62d3 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2281,11 +2281,6 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
>  	 */
>  	crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
>  
> -	/*
> -	 * FIXME also related to skl+ w/a 1136 (also unimplemented as of
> -	 * now) perhaps?
> -	 */
> -
>  	for (level++; level < i915->display.wm.num_levels; level++) {
>  		enum plane_id plane_id;
>  
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v6 2/6] drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006

[Hogander, Jouni]

On Wed, 2023-03-29 at 14:40 +0300, Ville Syrjälä wrote:
> On Wed, Mar 29, 2023 at 12:45:28PM +0300, Jouni Högander wrote:
> > Wa_16013835468 is a separate from Wa_14015648006 and needs to be
> > applied for TGL onwards. Fix this by removing all the references to
> > Wa_14015648006 and apply Wa_16013835468 according to Bspec.
> > 
> > Also move workaround into separate function as a preparation for
> > Wa_14015648006 implementation.
> > 
> > Bspec: 55378
> > 
> > v2:
> >  - keep applying the wa in intel_psr_enable_source
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 35 ++++++++++++++++----
> > ----
> >  1 file changed, 24 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 8dbf452d63c2..26ad4365960f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1134,6 +1134,28 @@ static u32 wa_16013835468_bit_get(struct
> > intel_dp *intel_dp)
> >         }
> >  }
> >  
> > +/*
> > + * Wa_16013835468
> > + */
> > +static void wm_optimization_wa(struct intel_dp *intel_dp,
> > +                              const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +       struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +       bool set_wa_bit = false;
> > +
> > +       /* Wa_16013835468 */
> > +       if (DISPLAY_VER(dev_priv) >= 12)
> 
> Looks like this should actually be == 12

Ok,I will fix this. It seems I misread the Bspec on this.

> > +               set_wa_bit |= crtc_state-
> > >hw.adjusted_mode.crtc_vblank_start !=
> > +                       crtc_state->hw.adjusted_mode.crtc_vdisplay;
> > +
> > +       if (set_wa_bit)
> > +               intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> 
> Can you drop that 0 to the next line so the two branches
> at least looks a bit more alike?

I will change it.

> 
> Alternatively
> intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
>              wa_16013835468_bit_get(intel_dp),
>              set_wa_bit ? wa_16013835468_bit_get(intel_dp) : 0);
> or something along those lines.
> 
> > +                            wa_16013835468_bit_get(intel_dp));
> > +       else
> > +               intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> > +                            wa_16013835468_bit_get(intel_dp), 0);
> > +}
> > +
> >  static void intel_psr_enable_source(struct intel_dp *intel_dp,
> >                                     const struct intel_crtc_state
> > *crtc_state)
> >  {
> > @@ -1175,15 +1197,8 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> >  
> >         /*
> >          * Wa_16013835468
> > -        * Wa_14015648006
> >          */
> > -       if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > -           IS_DISPLAY_VER(dev_priv, 12, 13)) {
> > -               if (crtc_state->hw.adjusted_mode.crtc_vblank_start
> > !=
> > -                   crtc_state->hw.adjusted_mode.crtc_vdisplay)
> > -                       intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> > 0,
> > -                                   
> > wa_16013835468_bit_get(intel_dp));
> > -       }
> > +       wm_optimization_wa(intel_dp, crtc_state);
> >  
> >         if (intel_dp->psr.psr2_enabled) {
> >                 if (DISPLAY_VER(dev_priv) == 9)
> > @@ -1359,10 +1374,8 @@ static void intel_psr_disable_locked(struct
> > intel_dp *intel_dp)
> >  
> >         /*
> >          * Wa_16013835468
> > -        * Wa_14015648006
> >          */
> > -       if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > -           IS_DISPLAY_VER(dev_priv, 12, 13))
> > +       if (DISPLAY_VER(dev_priv) >= 12)
> >                 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> >                              wa_16013835468_bit_get(intel_dp), 0);
> >  
> > -- 
> > 2.34.1
> 

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915/psr: Implement Display WA #1136

[Hogander, Jouni]

On Wed, 2023-03-29 at 15:52 +0300, Ville Syrjälä wrote:
> On Wed, Mar 29, 2023 at 12:45:32PM +0300, Jouni Högander wrote:
> > Implement Display WA #1136 for SKL/BXT.
> 
> Pre-ICL is more accurate now.

Ok I will modify the commit message and add your rb.

> 
> Maybe also mention here that the chicken bit approach
> might work for KBL+ but implementing that is left
> out for the time being.
> 
> > 
> > Bspec: 21664
> > 
> > v2: Handle disable psr in pre/post plane hooks
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c     | 7 +++++++
> >  drivers/gpu/drm/i915/display/skl_watermark.c | 5 -----
> >  2 files changed, 7 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index f86d9f83429f..52f73c65d365 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1968,11 +1968,14 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> >                  * - PSR disabled in new state
> >                  * - All planes will go inactive
> >                  * - Changing between PSR versions
> > +                * - Display WA #1136: skl, bxt
> >                  */
> >                 needs_to_disable |=
> > intel_crtc_needs_modeset(new_crtc_state);
> >                 needs_to_disable |= !new_crtc_state->has_psr;
> >                 needs_to_disable |= !new_crtc_state->active_planes;
> >                 needs_to_disable |= new_crtc_state->has_psr2 !=
> > psr->psr2_enabled;
> > +               needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > +                       new_crtc_state->wm_level_disabled;
> >  
> >                 if (psr->enabled && needs_to_disable)
> >                         intel_psr_disable_locked(intel_dp);
> > @@ -2007,6 +2010,10 @@ static void
> > _intel_psr_post_plane_update(const struct intel_atomic_state
> > *state,
> >                 keep_disabled |= psr->sink_not_reliable;
> >                 keep_disabled |= !crtc_state->active_planes;
> >  
> > +               /* Display WA #1136: skl, bxt */
> > +               keep_disabled |= DISPLAY_VER(dev_priv) < 11 &&
> > +                       crtc_state->wm_level_disabled;
> > +
> >                 if (!psr->enabled && !keep_disabled)
> >                         intel_psr_enable_locked(intel_dp,
> > crtc_state);
> >  
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index 7e2e76afbf2a..5296a20d62d3 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -2281,11 +2281,6 @@ static int skl_wm_check_vblank(struct
> > intel_crtc_state *crtc_state)
> >          */
> >         crtc_state->wm_level_disabled = level < i915-
> > >display.wm.num_levels - 1;
> >  
> > -       /*
> > -        * FIXME also related to skl+ w/a 1136 (also unimplemented
> > as of
> > -        * now) perhaps?
> > -        */
> > -
> >         for (level++; level < i915->display.wm.num_levels; level++)
> > {
> >                 enum plane_id plane_id;
> >  
> > -- 
> > 2.34.1
>