From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com
Subject: [PATCH v9 0/8] Implement CMRR Support
Date: Fri, 24 May 2024 15:54:24 +0530 [thread overview]
Message-ID: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> (raw)
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.
enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.
--v6:
- CMRR handling in co-existatnce of LRR and DRRS
- Correct vtotal paramas accuracy and add 2 digit precision.
--v7:
- Rebased patches in-accordance to AS SDP merge.
- Add neccessary gaurd to prevent crtc_state mismatch
during intel_vrr_get_config.
-v8:
- Add support for AS SDP for CMRR.
- update palce holder for CMRR register(Jani).
- Make CMRR as subset of FAVT, as per comments in patch#3.
-v9:
- Add CMRR register definitions to separate intel_vrr_reg.h.
- Remove cmrr_enabling/disabling, use vrr.enable instead.
- Update AS SDP pack function to accomodate target_rr_divider.
- Remove duplicated lines to compute vrr_vsync params.
- Set cmrr.enable with a separate patch at last.
Mitul Golani (8):
drm/i915: Define and compute Transcoder CMRR registers
drm/i915: Update trans_vrr_ctl flag when cmrr is computed
drm/i915: Compute CMRR and calculate vtotal
Add refresh rate divider to struct representing AS SDP
drm/i915/display: Add support for pack and unpack
drm/i915/display: Compute Adaptive sync SDP params
drm/i915/display: Compute vrr vsync params
drm/i915/display: Compute cmrr.enable flag
drivers/gpu/drm/i915/display/intel_display.c | 24 ++-
.../drm/i915/display/intel_display_device.h | 1 +
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_dp.c | 21 ++-
drivers/gpu/drm/i915/display/intel_vrr.c | 139 +++++++++++++++---
drivers/gpu/drm/i915/intel_vrr_reg.h | 21 +++
include/drm/display/drm_dp_helper.h | 1 +
7 files changed, 191 insertions(+), 22 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_vrr_reg.h
--
2.25.1
next reply other threads:[~2024-05-24 10:30 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-24 10:24 Mitul Golani [this message]
2024-05-24 10:24 ` [PATCH v9 1/8] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2024-05-27 10:50 ` Jani Nikula
2024-05-27 10:52 ` Jani Nikula
2024-05-24 10:24 ` [PATCH v9 2/8] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Mitul Golani
2024-05-28 9:06 ` Nautiyal, Ankit K
2024-05-24 10:24 ` [PATCH v9 3/8] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
2024-05-28 9:34 ` Nautiyal, Ankit K
2024-05-29 11:43 ` Nautiyal, Ankit K
2024-05-24 10:24 ` [PATCH v9 4/8] Add refresh rate divider to struct representing AS SDP Mitul Golani
2024-05-28 9:35 ` Nautiyal, Ankit K
2024-05-24 10:24 ` [PATCH v9 5/8] drm/i915/display: Add support for pack and unpack Mitul Golani
2024-05-28 9:37 ` Nautiyal, Ankit K
2024-05-24 10:24 ` [PATCH v9 6/8] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
2024-05-28 9:39 ` Nautiyal, Ankit K
2024-05-24 10:24 ` [PATCH v9 7/8] drm/i915/display: Compute vrr vsync params Mitul Golani
2024-05-24 10:24 ` [PATCH v9 8/8] drm/i915/display: Compute cmrr.enable flag Mitul Golani
2024-05-24 11:02 ` ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev9) Patchwork
2024-05-24 11:02 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-24 11:13 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-05-27 10:10 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-27 15:15 ` ✗ Fi.CI.IGT: failure " Patchwork
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