From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH v9 2/8] drm/i915: Update trans_vrr_ctl flag when cmrr is computed
Date: Tue, 28 May 2024 14:36:45 +0530 [thread overview]
Message-ID: <c4cd829c-9120-4c8b-b1b2-124257052873@intel.com> (raw)
In-Reply-To: <20240524102432.2499104-3-mitulkumar.ajitkumar.golani@intel.com>
On 5/24/2024 3:54 PM, Mitul Golani wrote:
> Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
> is set, With this commit setting the stage for subsequent
> CMRR enablement.
>
> --v2:
> - Check pipe active state in cmrr enabling. [Jani]
> - Remove usage of bitwise OR on booleans. [Jani]
> - Revert unrelated changes. [Jani]
> - Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
> - Simplify whole if-ladder in intel_vrr_enable. [Jani]
> - Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]
>
> --v3:
> - Check pipe active state in cmrr disabling.[Jani]
> - Correct messed up condition in intel_vrr_enable. [Jani]
>
> --v4:
> - Removing RFC tag.
>
> --v5:
> - CMRR handling in co-existatnce of LRR and DRRS.
>
> --v7:
> - Rebase on top of AS SDP merge.
>
> --v8:
> - Remove cmrr_enabling/disabling and update commit message. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index b96a8b2e7083..3b250e92af98 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -277,15 +277,20 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>
> intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder),
> TRANS_PUSH_EN);
> -
Line removed from here.
Otherwise looks good.
Regards,
Ankit
> if (HAS_AS_SDP(dev_priv))
> intel_de_write(dev_priv,
> TRANS_VRR_VSYNC(dev_priv, cpu_transcoder),
> VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
> VRR_VSYNC_START(crtc_state->vrr.vsync_start));
>
> - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> + if (crtc_state->cmrr.enable) {
> + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
> + trans_vrr_ctl(crtc_state));
> + } else {
> + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> + }
> }
>
> void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
next prev parent reply other threads:[~2024-05-28 9:07 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-24 10:24 [PATCH v9 0/8] Implement CMRR Support Mitul Golani
2024-05-24 10:24 ` [PATCH v9 1/8] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2024-05-27 10:50 ` Jani Nikula
2024-05-27 10:52 ` Jani Nikula
2024-05-24 10:24 ` [PATCH v9 2/8] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Mitul Golani
2024-05-28 9:06 ` Nautiyal, Ankit K [this message]
2024-05-24 10:24 ` [PATCH v9 3/8] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
2024-05-28 9:34 ` Nautiyal, Ankit K
2024-05-29 11:43 ` Nautiyal, Ankit K
2024-05-24 10:24 ` [PATCH v9 4/8] Add refresh rate divider to struct representing AS SDP Mitul Golani
2024-05-28 9:35 ` Nautiyal, Ankit K
2024-05-24 10:24 ` [PATCH v9 5/8] drm/i915/display: Add support for pack and unpack Mitul Golani
2024-05-28 9:37 ` Nautiyal, Ankit K
2024-05-24 10:24 ` [PATCH v9 6/8] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
2024-05-28 9:39 ` Nautiyal, Ankit K
2024-05-24 10:24 ` [PATCH v9 7/8] drm/i915/display: Compute vrr vsync params Mitul Golani
2024-05-24 10:24 ` [PATCH v9 8/8] drm/i915/display: Compute cmrr.enable flag Mitul Golani
2024-05-24 11:02 ` ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev9) Patchwork
2024-05-24 11:02 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-24 11:13 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-05-27 10:10 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-27 15:15 ` ✗ Fi.CI.IGT: failure " Patchwork
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