Re: [PATCH v9 1/8] drm/i915: Define and compute Transcoder CMRR registers

[Jani Nikula <jani.nikula@linux.intel.com>]

On Fri, 24 May 2024, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/intel_vrr_reg.h b/drivers/gpu/drm/i915/intel_vrr_reg.h
> new file mode 100644
> index 000000000000..e1273b4e1b9b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_vrr_reg.h

We'll want to call this intel_vrr_regs.h, not _reg.h.

$ find drivers/gpu/drm/i915/ -name "*_reg*.h" | grep -o "regs*.h" | sort | uniq -c
      4 reg.h
     38 regs.h

> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __INTEL_VRR_REG_H__
> +#define __INTEL_VRR_REG_H__
> +
> +#define   VRR_CTL_CMRR_ENABLE			REG_BIT(27)
> +
> +#define	_TRANS_CMRR_M_LO_A                  0x604F0
> +#define	_TRANS_CMRR_M_HI_A		            0x604F4
> +#define	_TRANS_CMRR_N_LO_A		            0x604F8
> +#define	_TRANS_CMRR_N_HI_A		            0x604FC
> +#define	TRANS_CMRR_M_LO(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A)
> +#define	TRANS_CMRR_M_HI(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A)
> +#define	TRANS_CMRR_N_LO(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A)
> +#define	TRANS_CMRR_N_HI(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)

Please read the big comment near the top of i915_reg.h about ordering
and indenting and all that stuff.

See what Ville's doing here [1] to clean up.


BR,
Jani.

[1] https://lore.kernel.org/r/20240516135622.3498-3-ville.syrjala@linux.intel.com


-- 
Jani Nikula, Intel