[PATCH 0/3] Some correction in the DP Link Training dequence

[PATCH 0/3] Some correction in the DP Link Training dequence

[Arun R Murthy]

Arun R Murthy (3):
  drm/i915/dp: use fsleep instead of usleep_rage for LT
  drm/i915/dp: read Aux RD interval after reading the FFE preset
  drm/i915/dp: Include the time taken by AUX Tx for timeout

 .../drm/i915/display/intel_dp_link_training.c | 20 +++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

-- 
2.25.1

[PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Arun R Murthy]

Aux RD Interval value depends on the value read from the dpcd register
which is updated from the sink device use flseep thereby we adhere to
the Documentation/timers/timers-howto.rst

Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 397cc4ebae52..f41b69840ad9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -898,7 +898,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 
 	voltage_tries = 1;
 	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
-		usleep_range(delay_us, 2 * delay_us);
+		fsleep(delay_us);
 
 		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
 						     link_status) < 0) {
@@ -1040,7 +1040,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
 	}
 
 	for (tries = 0; tries < 5; tries++) {
-		usleep_range(delay_us, 2 * delay_us);
+		fsleep(delay_us);
 
 		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
 						     link_status) < 0) {
@@ -1417,7 +1417,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
 	deadline = jiffies + msecs_to_jiffies_timeout(400);
 
 	for (try = 0; try < max_tries; try++) {
-		usleep_range(delay_us, 2 * delay_us);
+		fsleep(delay_us);
 
 		/*
 		 * The delay may get updated. The transmitter shall read the
-- 
2.25.1

Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Jani Nikula]

On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> Aux RD Interval value depends on the value read from the dpcd register
> which is updated from the sink device use flseep thereby we adhere to
> the Documentation/timers/timers-howto.rst

Please explain why instead of just referencing a file.

BR,
Jani.

> Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 397cc4ebae52..f41b69840ad9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -898,7 +898,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
>  
>  	voltage_tries = 1;
>  	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
> -		usleep_range(delay_us, 2 * delay_us);
> +		fsleep(delay_us);
>  
>  		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
>  						     link_status) < 0) {
> @@ -1040,7 +1040,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
>  	}
>  
>  	for (tries = 0; tries < 5; tries++) {
> -		usleep_range(delay_us, 2 * delay_us);
> +		fsleep(delay_us);
>  
>  		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
>  						     link_status) < 0) {
> @@ -1417,7 +1417,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
>  	deadline = jiffies + msecs_to_jiffies_timeout(400);
>  
>  	for (try = 0; try < max_tries; try++) {
> -		usleep_range(delay_us, 2 * delay_us);
> +		fsleep(delay_us);
>  
>  		/*
>  		 * The delay may get updated. The transmitter shall read the

-- 
Jani Nikula, Intel

RE: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Murthy, Arun R]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, September 12, 2024 2:32 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V, NagaVenkata
> <nagavenkata.srikanth.v@intel.com>
> Subject: Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT
> 
> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > Aux RD Interval value depends on the value read from the dpcd register
> > which is updated from the sink device use flseep thereby we adhere to
> > the Documentation/timers/timers-howto.rst
> 
> Please explain why instead of just referencing a file.

Sleeping for < 10us use udelay, for 10us to 20ms use usleep_range and for > 10ms use msleep.
fsleep() will call the particular api based on the above condition.

Thanks and Regards,
Arun R Murthy
--------------------

RE: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Srikanth V, NagaVenkata]

[-- Attachment #1.1: Type: text/plain, Size: 2025 bytes --]

Hi Jani,

AUX_RD interval can have maximum value of 256ms. usleep_range() is recommended to be used for 10uS-20ms range as per Documentation/timers/timers-howto.rst



[cid:image001.png@01DB0539.9751B230]



So, switched to fsleep() which takes care of calling respective functions according to the delay.



Regards

Srikanth



-----Original Message-----
From: Murthy, Arun R <arun.r.murthy@intel.com>
Sent: Thursday, September 12, 2024 3:34 PM
To: Jani Nikula <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Srikanth V, NagaVenkata <nagavenkata.srikanth.v@intel.com>
Subject: RE: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT



> -----Original Message-----

> From: Jani Nikula <jani.nikula@linux.intel.com<mailto:jani.nikula@linux.intel.com>>

> Sent: Thursday, September 12, 2024 2:32 PM

> To: Murthy, Arun R <arun.r.murthy@intel.com<mailto:arun.r.murthy@intel.com>>;

> intel-xe@lists.freedesktop.org<mailto:intel-xe@lists.freedesktop.org>; intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org>

> Cc: Murthy, Arun R <arun.r.murthy@intel.com<mailto:arun.r.murthy@intel.com>>; Srikanth V, NagaVenkata

> <nagavenkata.srikanth.v@intel.com<mailto:nagavenkata.srikanth.v@intel.com>>

> Subject: Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of

> usleep_rage for LT

>

> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com<mailto:arun.r.murthy@intel.com>> wrote:

> > Aux RD Interval value depends on the value read from the dpcd

> > register which is updated from the sink device use flseep thereby we

> > adhere to the Documentation/timers/timers-howto.rst

>

> Please explain why instead of just referencing a file.



Sleeping for < 10us use udelay, for 10us to 20ms use usleep_range and for > 10ms use msleep.

fsleep() will call the particular api based on the above condition.



Thanks and Regards,

Arun R Murthy

--------------------

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[-- Attachment #2: image001.png --]
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RE: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Jani Nikula]

On Thu, 12 Sep 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@linux.intel.com>
>> Sent: Thursday, September 12, 2024 2:32 PM
>> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-xe@lists.freedesktop.org;
>> intel-gfx@lists.freedesktop.org
>> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V, NagaVenkata
>> <nagavenkata.srikanth.v@intel.com>
>> Subject: Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT
>> 
>> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> > Aux RD Interval value depends on the value read from the dpcd register
>> > which is updated from the sink device use flseep thereby we adhere to
>> > the Documentation/timers/timers-howto.rst
>> 
>> Please explain why instead of just referencing a file.
>
> Sleeping for < 10us use udelay, for 10us to 20ms use usleep_range and for > 10ms use msleep.
> fsleep() will call the particular api based on the above condition.

Oh, I'm not asking to explain this specifically to me. I'm asking it to
be explained in the commit message, for posterity. A commit message
should always answer the question *why*.

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Jani Nikula]

On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> Aux RD Interval value depends on the value read from the dpcd register
> which is updated from the sink device use flseep thereby we adhere to
> the Documentation/timers/timers-howto.rst
>
> Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>

Why do all the patches have two Signed-off-by's?

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 397cc4ebae52..f41b69840ad9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -898,7 +898,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
>  
>  	voltage_tries = 1;
>  	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
> -		usleep_range(delay_us, 2 * delay_us);
> +		fsleep(delay_us);
>  
>  		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
>  						     link_status) < 0) {
> @@ -1040,7 +1040,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
>  	}
>  
>  	for (tries = 0; tries < 5; tries++) {
> -		usleep_range(delay_us, 2 * delay_us);
> +		fsleep(delay_us);
>  
>  		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
>  						     link_status) < 0) {
> @@ -1417,7 +1417,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
>  	deadline = jiffies + msecs_to_jiffies_timeout(400);
>  
>  	for (try = 0; try < max_tries; try++) {
> -		usleep_range(delay_us, 2 * delay_us);
> +		fsleep(delay_us);
>  
>  		/*
>  		 * The delay may get updated. The transmitter shall read the

-- 
Jani Nikula, Intel

RE: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Murthy, Arun R]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, September 12, 2024 2:36 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V, NagaVenkata
> <nagavenkata.srikanth.v@intel.com>
> Subject: Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT
> 
> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > Aux RD Interval value depends on the value read from the dpcd register
> > which is updated from the sink device use flseep thereby we adhere to
> > the Documentation/timers/timers-howto.rst
> >
> > Signed-off-by: Srikanth V NagaVenkata
> > <nagavenkata.srikanth.v@intel.com>
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> 
> Why do all the patches have two Signed-off-by's?
> 
Findings are from Srikanth so giving credits to him as well.

Thanks and Regards,
Arun R Murthy
--------------------

RE: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Jani Nikula]

On Thu, 12 Sep 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@linux.intel.com>
>> Sent: Thursday, September 12, 2024 2:36 PM
>> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-xe@lists.freedesktop.org;
>> intel-gfx@lists.freedesktop.org
>> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V, NagaVenkata
>> <nagavenkata.srikanth.v@intel.com>
>> Subject: Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT
>> 
>> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> > Aux RD Interval value depends on the value read from the dpcd register
>> > which is updated from the sink device use flseep thereby we adhere to
>> > the Documentation/timers/timers-howto.rst
>> >
>> > Signed-off-by: Srikanth V NagaVenkata
>> > <nagavenkata.srikanth.v@intel.com>
>> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> 
>> Why do all the patches have two Signed-off-by's?
>> 
> Findings are from Srikanth so giving credits to him as well.

Contrary to popular belief, Signed-off-by: actually has very little to
do with credits and authorship, and everything to do with certifying
that the work can be submitted and merged to the kernel [1].

What you're looking for is Co-developed-by: [2] in combination with
S-o-b.


BR,
Jani.


[1] https://docs.kernel.org/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin
[2] https://docs.kernel.org/process/submitting-patches.html#when-to-use-acked-by-cc-and-co-developed-by

-- 
Jani Nikula, Intel

Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Jani Nikula]

On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> Aux RD Interval value depends on the value read from the dpcd register
> which is updated from the sink device use flseep thereby we adhere to
> the Documentation/timers/timers-howto.rst
>
> Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>

With the commit message updated to explain why,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 397cc4ebae52..f41b69840ad9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -898,7 +898,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
>  
>  	voltage_tries = 1;
>  	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
> -		usleep_range(delay_us, 2 * delay_us);
> +		fsleep(delay_us);
>  
>  		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
>  						     link_status) < 0) {
> @@ -1040,7 +1040,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
>  	}
>  
>  	for (tries = 0; tries < 5; tries++) {
> -		usleep_range(delay_us, 2 * delay_us);
> +		fsleep(delay_us);
>  
>  		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
>  						     link_status) < 0) {
> @@ -1417,7 +1417,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
>  	deadline = jiffies + msecs_to_jiffies_timeout(400);
>  
>  	for (try = 0; try < max_tries; try++) {
> -		usleep_range(delay_us, 2 * delay_us);
> +		fsleep(delay_us);
>  
>  		/*
>  		 * The delay may get updated. The transmitter shall read the

-- 
Jani Nikula, Intel

Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Francois Dugast]

On Mon, Sep 23, 2024 at 01:24:27PM +0300, Jani Nikula wrote:
> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > Aux RD Interval value depends on the value read from the dpcd register
> > which is updated from the sink device use flseep thereby we adhere to
> > the Documentation/timers/timers-howto.rst
> >
> > Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> 
> With the commit message updated to explain why,

While at it, please also fix the typo s/usleep_rage/usleep_range/.

Francois

> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 397cc4ebae52..f41b69840ad9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -898,7 +898,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
> >  
> >  	voltage_tries = 1;
> >  	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
> > -		usleep_range(delay_us, 2 * delay_us);
> > +		fsleep(delay_us);
> >  
> >  		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
> >  						     link_status) < 0) {
> > @@ -1040,7 +1040,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
> >  	}
> >  
> >  	for (tries = 0; tries < 5; tries++) {
> > -		usleep_range(delay_us, 2 * delay_us);
> > +		fsleep(delay_us);
> >  
> >  		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
> >  						     link_status) < 0) {
> > @@ -1417,7 +1417,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
> >  	deadline = jiffies + msecs_to_jiffies_timeout(400);
> >  
> >  	for (try = 0; try < max_tries; try++) {
> > -		usleep_range(delay_us, 2 * delay_us);
> > +		fsleep(delay_us);
> >  
> >  		/*
> >  		 * The delay may get updated. The transmitter shall read the
> 
> -- 
> Jani Nikula, Intel

Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT

[Jani Nikula]

On Mon, 23 Sep 2024, Francois Dugast <francois.dugast@intel.com> wrote:
> On Mon, Sep 23, 2024 at 01:24:27PM +0300, Jani Nikula wrote:
>> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> > Aux RD Interval value depends on the value read from the dpcd register
>> > which is updated from the sink device use flseep thereby we adhere to
>> > the Documentation/timers/timers-howto.rst
>> >
>> > Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
>> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> 
>> With the commit message updated to explain why,
>
> While at it, please also fix the typo s/usleep_rage/usleep_range/.

usleep_rage does have a certain appeal to it, though... ;)

BR,
Jani.


-- 
Jani Nikula, Intel

[PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Arun R Murthy]

DP Source should be reading AUX_RD interval after we get adjusted
TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting
in DP Source)

Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index f41b69840ad9..ca179bed46ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
 	for (try = 0; try < max_tries; try++) {
 		fsleep(delay_us);
 
-		/*
-		 * The delay may get updated. The transmitter shall read the
-		 * delay before link status during link training.
-		 */
-		delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
-
 		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
 			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
 			return false;
@@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
 			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
 			return false;
 		}
+
+		/*
+		 * The delay may get updated. The transmitter shall read the
+		 * delay before link status during link training.
+		 */
+		delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
 	}
 
 	if (try == max_tries) {
-- 
2.25.1

Re: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Jani Nikula]

On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> DP Source should be reading AUX_RD interval after we get adjusted
> TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting
> in DP Source)

Please explain why.

BR,
Jani.

>
> Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index f41b69840ad9..ca179bed46ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
>  	for (try = 0; try < max_tries; try++) {
>  		fsleep(delay_us);
>  
> -		/*
> -		 * The delay may get updated. The transmitter shall read the
> -		 * delay before link status during link training.
> -		 */
> -		delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> -
>  		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
>  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
>  			return false;
> @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
>  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
>  			return false;
>  		}
> +
> +		/*
> +		 * The delay may get updated. The transmitter shall read the
> +		 * delay before link status during link training.
> +		 */
> +		delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
>  	}
>  
>  	if (try == max_tries) {

-- 
Jani Nikula, Intel

RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Murthy, Arun R]

> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > DP Source should be reading AUX_RD interval after we get adjusted
> > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in DP
> > Source)
> 
> Please explain why.
 As per the DP 2.1 spec section 3.5.2.16.1
"The transmitter shall finish reading
from DPCD 00202h through 00207h, DPCD 0200Ch through 0200Fh, and DPCD 02216h, and
writing to DPCD 00103h through 00106h (listed as "AUX TX response" in Figure 3-51) within
2.5 ms or less, such that the total duration for AUX TX responses with a 20-loop count does not
exceed 50 ms. "

Thanks and Regards,
Arun R Murthy
--------------------

RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Srikanth V, NagaVenkata]

[-- Attachment #1.1: Type: text/plain, Size: 1316 bytes --]

Hi Jani,



It's as per DP2.1 spec, where we should be reading AUX_RD interval at the loop before we wait.

[cid:image001.png@01DB0538.65998930]

Regards

Srikanth



-----Original Message-----
From: Murthy, Arun R <arun.r.murthy@intel.com>
Sent: Thursday, September 12, 2024 4:25 PM
To: Jani Nikula <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Srikanth V, NagaVenkata <nagavenkata.srikanth.v@intel.com>
Subject: RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset



> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com<mailto:arun.r.murthy@intel.com>> wrote:

> > DP Source should be reading AUX_RD interval after we get adjusted

> > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in

> > DP

> > Source)

>

> Please explain why.

As per the DP 2.1 spec section 3.5.2.16.1 "The transmitter shall finish reading from DPCD 00202h through 00207h, DPCD 0200Ch through 0200Fh, and DPCD 02216h, and writing to DPCD 00103h through 00106h (listed as "AUX TX response" in Figure 3-51) within

2.5 ms or less, such that the total duration for AUX TX responses with a 20-loop count does not exceed 50 ms. "



Thanks and Regards,

Arun R Murthy

--------------------

[-- Attachment #1.2: Type: text/html, Size: 4134 bytes --]

[-- Attachment #2: image001.png --]
[-- Type: image/png, Size: 50760 bytes --]

RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Arun R
> Murthy
> Sent: Thursday, September 12, 2024 10:36 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V, NagaVenkata
> <nagavenkata.srikanth.v@intel.com>
> Subject: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE
> preset
> 
> DP Source should be reading AUX_RD interval after we get adjusted
> TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in DP
> Source)

I think mentioning the dp spec reference here would be helpful

> 
> Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index f41b69840ad9..ca179bed46ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> *intel_dp,
>  	for (try = 0; try < max_tries; try++) {
>  		fsleep(delay_us);
> 
> -		/*
> -		 * The delay may get updated. The transmitter shall read the
> -		 * delay before link status during link training.
> -		 */
> -		delay_us =
> drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> -
>  		if (drm_dp_dpcd_read_link_status(&intel_dp->aux,
> link_status) < 0) {
>  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link
> status\n");
>  			return false;
> @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> *intel_dp,
>  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX
> FFE settings\n");
>  			return false;
>  		}
> +
> +		/*
> +		 * The delay may get updated. The transmitter shall read the
> +		 * delay before link status during link training.
> +		 */

The comment needs to be updated as this is not being done before link status 
Also a question does this not conflict with the requirement we previously had (reading it before link status) ?

Regards,
Suraj Kandpal

Regards,
Suraj Kandpal

> +		delay_us =
> drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
>  	}
> 
>  	if (try == max_tries) {
> --
> 2.25.1

RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Srikanth V, NagaVenkata]

> > -----Original Message-----
> > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> > Arun R Murthy
> > Sent: Thursday, September 12, 2024 10:36 AM
> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V, NagaVenkata
> > <nagavenkata.srikanth.v@intel.com>
> > Subject: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading
> > the FFE preset
> >
> > DP Source should be reading AUX_RD interval after we get adjusted
> > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in DP
> > Source)
> 
> I think mentioning the dp spec reference here would be helpful
> 
Please refer to Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence of DP2.1a spec.

> >
> > Signed-off-by: Srikanth V NagaVenkata
> > <nagavenkata.srikanth.v@intel.com>
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index f41b69840ad9..ca179bed46ad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > *intel_dp,
> >  	for (try = 0; try < max_tries; try++) {
> >  		fsleep(delay_us);
> >
> > -		/*
> > -		 * The delay may get updated. The transmitter shall read the
> > -		 * delay before link status during link training.
> > -		 */
> > -		delay_us =
> > drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> > -
> >  		if (drm_dp_dpcd_read_link_status(&intel_dp->aux,
> > link_status) < 0) {
> >  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link
> status\n");
> >  			return false;
> > @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > *intel_dp,
> >  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX
> FFE
> > settings\n");
> >  			return false;
> >  		}
> > +
> > +		/*
> > +		 * The delay may get updated. The transmitter shall read the
> > +		 * delay before link status during link training.
> > +		 */
> 
> The comment needs to be updated as this is not being done before link
> status Also a question does this not conflict with the requirement we
> previously had (reading it before link status) ?
> 
> Regards,
> Suraj Kandpal
> 
> Regards,
> Suraj Kandpal
> 
> > +		delay_us =
> > drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> >  	}
> >
> >  	if (try == max_tries) {
> > --
> > 2.25.1

RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Kandpal, Suraj]

> -----Original Message-----
> From: Srikanth V, NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Sent: Monday, September 23, 2024 11:59 AM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; intel-xe@lists.freedesktop.org; intel-
> gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the
> FFE preset
> 
> > > -----Original Message-----
> > > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> > > Arun R Murthy
> > > Sent: Thursday, September 12, 2024 10:36 AM
> > > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V,
> > > NagaVenkata <nagavenkata.srikanth.v@intel.com>
> > > Subject: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading
> > > the FFE preset
> > >
> > > DP Source should be reading AUX_RD interval after we get adjusted
> > > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in
> > > DP
> > > Source)
> >
> > I think mentioning the dp spec reference here would be helpful
> >
> Please refer to Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE
> Sequence of DP2.1a spec.

I think you can update your commit message to say DP2.1a spec Fig. 3-52

Regards,
Suraj Kandpal
> 
> > >
> > > Signed-off-by: Srikanth V NagaVenkata
> > > <nagavenkata.srikanth.v@intel.com>
> > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > > ---
> > >  .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++------
> > >  1 file changed, 6 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index f41b69840ad9..ca179bed46ad 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > > *intel_dp,
> > >  	for (try = 0; try < max_tries; try++) {
> > >  		fsleep(delay_us);
> > >
> > > -		/*
> > > -		 * The delay may get updated. The transmitter shall read the
> > > -		 * delay before link status during link training.
> > > -		 */
> > > -		delay_us =
> > > drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> > > -
> > >  		if (drm_dp_dpcd_read_link_status(&intel_dp->aux,
> > > link_status) < 0) {
> > >  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link
> > status\n");
> > >  			return false;
> > > @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > > *intel_dp,
> > >  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX
> > FFE
> > > settings\n");
> > >  			return false;
> > >  		}
> > > +
> > > +		/*
> > > +		 * The delay may get updated. The transmitter shall read the
> > > +		 * delay before link status during link training.
> > > +		 */
> >
> > The comment needs to be updated as this is not being done before link
> > status Also a question does this not conflict with the requirement we
> > previously had (reading it before link status) ?
> >
> > Regards,
> > Suraj Kandpal
> >
> > Regards,
> > Suraj Kandpal
> >
> > > +		delay_us =
> > > drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> > >  	}
> > >
> > >  	if (try == max_tries) {
> > > --
> > > 2.25.1

RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Kandpal, Suraj]

> -----Original Message-----
> From: Srikanth V, NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Sent: Monday, September 23, 2024 11:59 AM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; intel-xe@lists.freedesktop.org; intel-
> gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the
> FFE preset
> 
> > > -----Original Message-----
> > > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> > > Arun R Murthy
> > > Sent: Thursday, September 12, 2024 10:36 AM
> > > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V,
> > > NagaVenkata <nagavenkata.srikanth.v@intel.com>
> > > Subject: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading
> > > the FFE preset
> > >
> > > DP Source should be reading AUX_RD interval after we get adjusted
> > > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in
> > > DP
> > > Source)
> >
> > I think mentioning the dp spec reference here would be helpful
> >
> Please refer to Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE
> Sequence of DP2.1a spec.
> 
> > >
> > > Signed-off-by: Srikanth V NagaVenkata
> > > <nagavenkata.srikanth.v@intel.com>
> > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > > ---
> > >  .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++------
> > >  1 file changed, 6 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index f41b69840ad9..ca179bed46ad 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > > *intel_dp,
> > >  	for (try = 0; try < max_tries; try++) {
> > >  		fsleep(delay_us);
> > >
> > > -		/*
> > > -		 * The delay may get updated. The transmitter shall read the
> > > -		 * delay before link status during link training.
> > > -		 */
> > > -		delay_us =
> > > drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> > > -
> > >  		if (drm_dp_dpcd_read_link_status(&intel_dp->aux,
> > > link_status) < 0) {
> > >  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link
> > status\n");
> > >  			return false;
> > > @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > > *intel_dp,
> > >  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX
> > FFE
> > > settings\n");
> > >  			return false;
> > >  		}
> > > +
> > > +		/*
> > > +		 * The delay may get updated. The transmitter shall read the
> > > +		 * delay before link status during link training.
> > > +		 */
> >
> > The comment needs to be updated as this is not being done before link
> > status Also a question does this not conflict with the requirement we
> > previously had (reading it before link status) ?
> >

Also  this whole delay us read should be called much below in the sequence from what I can see
In the dp spec just before we adjust the ffe settings at this point

/* Update signal levels and training set as requested. */
                intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
                if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
                        lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
                        return false;
                }

Regards,
Suraj Kandpal

> > Regards,
> > Suraj Kandpal
> >
> > Regards,
> > Suraj Kandpal
> >
> > > +		delay_us =
> > > drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> > >  	}
> > >
> > >  	if (try == max_tries) {
> > > --
> > > 2.25.1

RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Murthy, Arun R]

> > > > -		/*
> > > > -		 * The delay may get updated. The transmitter shall read the
> > > > -		 * delay before link status during link training.
> > > > -		 */
> > > > -		delay_us =
> > > > drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> > > > -
> > > >  		if (drm_dp_dpcd_read_link_status(&intel_dp->aux,
> > > > link_status) < 0) {
> > > >  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link
> > > status\n");
> > > >  			return false;
> > > > @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > > > *intel_dp,
> > > >  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX
> > > FFE
> > > > settings\n");
> > > >  			return false;
> > > >  		}
> > > > +
> > > > +		/*
> > > > +		 * The delay may get updated. The transmitter shall read the
> > > > +		 * delay before link status during link training.
> > > > +		 */
> > >
> > > The comment needs to be updated as this is not being done before
> > > link status Also a question does this not conflict with the
> > > requirement we previously had (reading it before link status) ?
> > >
> 
> Also  this whole delay us read should be called much below in the sequence
> from what I can see In the dp spec just before we adjust the ffe settings at this
> point
> 
> /* Update signal levels and training set as requested. */
>                 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
> link_status);
>                 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
>                         lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE
> settings\n");
>                         return false;
>                 }
> 
Yes as per the spec,
" During LT, the transmitter shall read DPCD 02216h before DPCD 00202h through 00207h, and 0200Ch through 0200Fh."

Will change it accordingly.

Thanks and Regards,
Arun R Murthy
--------------------

Re: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Jani Nikula]

On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> DP Source should be reading AUX_RD interval after we get adjusted
> TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting
> in DP Source)

I don't think that's correct. See below.

> Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index f41b69840ad9..ca179bed46ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
>  	for (try = 0; try < max_tries; try++) {
>  		fsleep(delay_us);
>  
> -		/*
> -		 * The delay may get updated. The transmitter shall read the
> -		 * delay before link status during link training.
> -		 */
> -		delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> -
>  		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
>  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
>  			return false;
> @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
>  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
>  			return false;
>  		}
> +
> +		/*
> +		 * The delay may get updated. The transmitter shall read the
> +		 * delay before link status during link training.
> +		 */
> +		delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);

This is clearly an improvement, but Figure 3-52 of DP 2.1a has "Read
AUX_RD_INTERVAL value" before "Adjust requested the TX_FFE_PRESET_VALUE
by a DPRX/LTTPR_UFP setting". Yes, in the same box in the flow chart,
but before.

Sticking with the spec, the read should be placed above this comment:

	/* Update signal levels and training set as requested. */

Be sure to reference the spec in the commit message.


BR,
Jani.


>  	}
>  
>  	if (try == max_tries) {

-- 
Jani Nikula, Intel

RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset

[Murthy, Arun R]

> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > DP Source should be reading AUX_RD interval after we get adjusted
> > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in DP
> > Source)
> 
> I don't think that's correct. See below.
> 
Will correct the statement.

> > Signed-off-by: Srikanth V NagaVenkata
> > <nagavenkata.srikanth.v@intel.com>
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index f41b69840ad9..ca179bed46ad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> *intel_dp,
> >  	for (try = 0; try < max_tries; try++) {
> >  		fsleep(delay_us);
> >
> > -		/*
> > -		 * The delay may get updated. The transmitter shall read the
> > -		 * delay before link status during link training.
> > -		 */
> > -		delay_us =
> drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> > -
> >  		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status)
> < 0) {
> >  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link
> status\n");
> >  			return false;
> > @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> *intel_dp,
> >  			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX
> FFE settings\n");
> >  			return false;
> >  		}
> > +
> > +		/*
> > +		 * The delay may get updated. The transmitter shall read the
> > +		 * delay before link status during link training.
> > +		 */
> > +		delay_us =
> drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> 
> This is clearly an improvement, but Figure 3-52 of DP 2.1a has "Read
> AUX_RD_INTERVAL value" before "Adjust requested the TX_FFE_PRESET_VALUE
> by a DPRX/LTTPR_UFP setting". Yes, in the same box in the flow chart, but
> before.
> 
> Sticking with the spec, the read should be placed above this comment:
> 
> 	/* Update signal levels and training set as requested. */
> 
> Be sure to reference the spec in the commit message.
> 
Yes, agree Will update this in the next version.

Thanks and Regards,
Arun R Murthy
--------------------

[PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout

[Arun R Murthy]

As per DP spec the timeout for LANE_CHANNEL_EQ_DONE is 400ms. But this
timeout value is exclusively for the Aux RD Interval and excludes the
time consumed for the AUX Tx (i.e reading/writing FFE presets). Add
another 50ms for these AUX Tx to the 400ms timeout.

Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index ca179bed46ad..b6573934c6dd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1414,7 +1414,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
 	}
 
 	/* Time budget for the LANEx_EQ_DONE Sequence */
-	deadline = jiffies + msecs_to_jiffies_timeout(400);
+	deadline = jiffies + msecs_to_jiffies_timeout(450);
 
 	for (try = 0; try < max_tries; try++) {
 		fsleep(delay_us);
-- 
2.25.1

RE: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Arun R
> Murthy
> Sent: Thursday, September 12, 2024 10:36 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V, NagaVenkata
> <nagavenkata.srikanth.v@intel.com>
> Subject: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for
> timeout
> 
> As per DP spec the timeout for LANE_CHANNEL_EQ_DONE is 400ms. But this

Adding where in DP spec example dp2.1 section x.x is a good idea

> timeout value is exclusively for the Aux RD Interval and excludes the time
> consumed for the AUX Tx (i.e reading/writing FFE presets). Add another
> 50ms for these AUX Tx to the 400ms timeout.

Is this something we came up with by trial and error or is this also a part of spec

Regards,
Suraj Kandpal
> 
> Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index ca179bed46ad..b6573934c6dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1414,7 +1414,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> *intel_dp,
>  	}
> 
>  	/* Time budget for the LANEx_EQ_DONE Sequence */
> -	deadline = jiffies + msecs_to_jiffies_timeout(400);
> +	deadline = jiffies + msecs_to_jiffies_timeout(450);
> 
>  	for (try = 0; try < max_tries; try++) {
>  		fsleep(delay_us);
> --
> 2.25.1

RE: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout

[Srikanth V, NagaVenkata]

> > -----Original Message-----
> > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> > Arun R Murthy
> > Sent: Thursday, September 12, 2024 10:36 AM
> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V, NagaVenkata
> > <nagavenkata.srikanth.v@intel.com>
> > Subject: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for
> > timeout
> >
> > As per DP spec the timeout for LANE_CHANNEL_EQ_DONE is 400ms. But this
> 
> Adding where in DP spec example dp2.1 section x.x is a good idea
> 
Please refer to section 3.5.2.16.1 128b/132b DP LANEx_CHANNEL_EQ_DONE Sequnce
and Figure3-51: 128b/132b DP EQ Time Budget Illustration of DP2.1a spec.

> > timeout value is exclusively for the Aux RD Interval and excludes the
> > time consumed for the AUX Tx (i.e reading/writing FFE presets). Add
> > another 50ms for these AUX Tx to the 400ms timeout.
> 
> Is this something we came up with by trial and error or is this also a part of spec
> 
It's not by trail and erros. Timeout value of 450ms is part of DP.

> Regards,
> Suraj Kandpal
> >
> > Signed-off-by: Srikanth V NagaVenkata
> > <nagavenkata.srikanth.v@intel.com>
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index ca179bed46ad..b6573934c6dd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -1414,7 +1414,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > *intel_dp,
> >  	}
> >
> >  	/* Time budget for the LANEx_EQ_DONE Sequence */
> > -	deadline = jiffies + msecs_to_jiffies_timeout(400);
> > +	deadline = jiffies + msecs_to_jiffies_timeout(450);
> >
> >  	for (try = 0; try < max_tries; try++) {
> >  		fsleep(delay_us);
> > --
> > 2.25.1

RE: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout

[Kandpal, Suraj]

> -----Original Message-----
> From: Srikanth V, NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Sent: Monday, September 23, 2024 12:02 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; intel-xe@lists.freedesktop.org; intel-
> gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: RE: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for
> timeout
> 
> 
> > > -----Original Message-----
> > > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> > > Arun R Murthy
> > > Sent: Thursday, September 12, 2024 10:36 AM
> > > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V,
> > > NagaVenkata <nagavenkata.srikanth.v@intel.com>
> > > Subject: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx
> > > for timeout
> > >
> > > As per DP spec the timeout for LANE_CHANNEL_EQ_DONE is 400ms. But
> > > this
> >
> > Adding where in DP spec example dp2.1 section x.x is a good idea
> >
> Please refer to section 3.5.2.16.1 128b/132b DP LANEx_CHANNEL_EQ_DONE
> Sequnce and Figure3-51: 128b/132b DP EQ Time Budget Illustration of
> DP2.1a spec.
> 
> > > timeout value is exclusively for the Aux RD Interval and excludes
> > > the time consumed for the AUX Tx (i.e reading/writing FFE presets).
> > > Add another 50ms for these AUX Tx to the 400ms timeout.
> >
> > Is this something we came up with by trial and error or is this also a
> > part of spec
> >
> It's not by trail and erros. Timeout value of 450ms is part of DP.

Ahh okay I see it,
After adding the dp spec reference in the commit message this patch
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> > Regards,
> > Suraj Kandpal
> > >
> > > Signed-off-by: Srikanth V NagaVenkata
> > > <nagavenkata.srikanth.v@intel.com>
> > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index ca179bed46ad..b6573934c6dd 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -1414,7 +1414,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > > *intel_dp,
> > >  	}
> > >
> > >  	/* Time budget for the LANEx_EQ_DONE Sequence */
> > > -	deadline = jiffies + msecs_to_jiffies_timeout(400);
> > > +	deadline = jiffies + msecs_to_jiffies_timeout(450);
> > >
> > >  	for (try = 0; try < max_tries; try++) {
> > >  		fsleep(delay_us);
> > > --
> > > 2.25.1

RE: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout

[Jani Nikula]

On Mon, 23 Sep 2024, "Srikanth V, NagaVenkata" <nagavenkata.srikanth.v@intel.com> wrote:
>> > -----Original Message-----
>> > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
>> > Arun R Murthy
>> > Sent: Thursday, September 12, 2024 10:36 AM
>> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> > Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Srikanth V, NagaVenkata
>> > <nagavenkata.srikanth.v@intel.com>
>> > Subject: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for
>> > timeout
>> >
>> > As per DP spec the timeout for LANE_CHANNEL_EQ_DONE is 400ms. But this
>> 
>> Adding where in DP spec example dp2.1 section x.x is a good idea
>> 
> Please refer to section 3.5.2.16.1 128b/132b DP LANEx_CHANNEL_EQ_DONE Sequnce
> and Figure3-51: 128b/132b DP EQ Time Budget Illustration of DP2.1a spec.
>
>> > timeout value is exclusively for the Aux RD Interval and excludes the
>> > time consumed for the AUX Tx (i.e reading/writing FFE presets). Add
>> > another 50ms for these AUX Tx to the 400ms timeout.
>> 
>> Is this something we came up with by trial and error or is this also a part of spec
>> 
> It's not by trail and erros. Timeout value of 450ms is part of DP.

It's a very poorly written spec, and contradicts itself. The only place
where I see 450 ms even mentioned is Figure 3-52. But everywhere else it
seems to say many times 400 ms is the max, without a hint that it would
be exclusive of aux. It does not say anything about the sum of rd
interval being related to the max of 400 ms either.

Regardless, I have no qualms about relaxing the timeout by 50 ms.

With the commit message explaining the above, with references,

Acked-by: Jani Nikula <jani.nikula@intel.com>


>
>> Regards,
>> Suraj Kandpal
>> >
>> > Signed-off-by: Srikanth V NagaVenkata
>> > <nagavenkata.srikanth.v@intel.com>
>> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > index ca179bed46ad..b6573934c6dd 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > @@ -1414,7 +1414,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp
>> > *intel_dp,
>> >  	}
>> >
>> >  	/* Time budget for the LANEx_EQ_DONE Sequence */
>> > -	deadline = jiffies + msecs_to_jiffies_timeout(400);
>> > +	deadline = jiffies + msecs_to_jiffies_timeout(450);
>> >
>> >  	for (try = 0; try < max_tries; try++) {
>> >  		fsleep(delay_us);
>> > --
>> > 2.25.1
>

-- 
Jani Nikula, Intel

✓ Fi.CI.BAT: success for Some correction in the DP Link Training dequence

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4611 bytes --]

== Series Details ==

Series: Some correction in the DP Link Training dequence
URL   : https://patchwork.freedesktop.org/series/138552/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_15400 -> Patchwork_138552v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/index.html

Participating hosts (40 -> 38)
------------------------------

  Additional (1): fi-bsw-n3050 
  Missing    (3): bat-dg1-7 fi-snb-2520m fi-kbl-8809g 

Known issues
------------

  Here are the changes found in Patchwork_138552v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@nullptr:
    - bat-arls-1:         [PASS][1] -> [DMESG-WARN][2] ([i915#12102])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/bat-arls-1/igt@fbdev@nullptr.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/bat-arls-1/igt@fbdev@nullptr.html

  * igt@i915_module_load@reload:
    - fi-kbl-7567u:       [PASS][3] -> [DMESG-WARN][4] ([i915#180] / [i915#1982] / [i915#9925])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/fi-kbl-7567u/igt@i915_module_load@reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/fi-kbl-7567u/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-7567u:       [PASS][5] -> [DMESG-WARN][6] ([i915#11621] / [i915#180] / [i915#1982] / [i915#9925])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live:
    - bat-arls-2:         [PASS][7] -> [ABORT][8] ([i915#12175])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/bat-arls-2/igt@i915_selftest@live.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/bat-arls-2/igt@i915_selftest@live.html

  * igt@i915_selftest@live@sanitycheck:
    - fi-kbl-7567u:       [PASS][9] -> [DMESG-WARN][10] ([i915#11621]) +37 other tests dmesg-warn
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-2:         [PASS][11] -> [ABORT][12] ([i915#12061])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/bat-arls-2/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/bat-arls-2/igt@i915_selftest@live@workarounds.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][13] +20 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/fi-bsw-n3050/igt@kms_psr@psr-primary-mmap-gtt.html

  
#### Possible fixes ####

  * igt@fbdev@read:
    - bat-arls-1:         [DMESG-WARN][14] ([i915#12102]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/bat-arls-1/igt@fbdev@read.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/bat-arls-1/igt@fbdev@read.html

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [ABORT][16] ([i915#12061]) -> [PASS][17] +1 other test pass
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/bat-mtlp-8/igt@i915_selftest@live.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/bat-mtlp-8/igt@i915_selftest@live.html

  
  [i915#11621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11621
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12102
  [i915#12175]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12175
  [i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#9925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9925


Build changes
-------------

  * Linux: CI_DRM_15400 -> Patchwork_138552v1

  CI-20190529: 20190529
  CI_DRM_15400: 1b37d4587b45639327eeb4cce29f77d487f7700a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8013: 8013
  Patchwork_138552v1: 1b37d4587b45639327eeb4cce29f77d487f7700a @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/index.html

[-- Attachment #2: Type: text/html, Size: 5876 bytes --]

✗ Fi.CI.IGT: failure for Some correction in the DP Link Training dequence

[Patchwork]

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== Series Details ==

Series: Some correction in the DP Link Training dequence
URL   : https://patchwork.freedesktop.org/series/138552/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_15400_full -> Patchwork_138552v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_138552v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_138552v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_138552v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-glk6/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_selftest@live@hangcheck:
    - shard-dg2:          [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-11/igt@i915_selftest@live@hangcheck.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-6/igt@i915_selftest@live@hangcheck.html

  * igt@kms_cursor_crc@cursor-sliding-128x128:
    - shard-dg1:          [PASS][5] -> [DMESG-WARN][6] +1 other test dmesg-warn
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg1-18/igt@kms_cursor_crc@cursor-sliding-128x128.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-17/igt@kms_cursor_crc@cursor-sliding-128x128.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-glk:          NOTRUN -> [INCOMPLETE][7] +1 other test incomplete
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk4/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [INCOMPLETE][8] +1 other test incomplete
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-15/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-hdmi-a-4.html

  * igt@kms_vblank@wait-busy-hang:
    - shard-dg2:          [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-3/igt@kms_vblank@wait-busy-hang.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_vblank@wait-busy-hang.html

  * igt@kms_vblank@wait-busy-hang@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][11] +1 other test fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_vblank@wait-busy-hang@pipe-a-dp-4.html

  
Known issues
------------

  Here are the changes found in Patchwork_138552v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-dg1:          NOTRUN -> [SKIP][12] ([i915#8411])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@api_intel_bb@crc32:
    - shard-dg1:          NOTRUN -> [SKIP][13] ([i915#6230])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@api_intel_bb@crc32.html

  * igt@drm_fdinfo@idle@rcs0:
    - shard-rkl:          NOTRUN -> [FAIL][14] ([i915#7742]) +1 other test fail
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@drm_fdinfo@idle@rcs0.html

  * igt@gem_basic@multigpu-create-close:
    - shard-dg1:          NOTRUN -> [SKIP][15] ([i915#7697])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-tglu:         NOTRUN -> [SKIP][16] ([i915#3555] / [i915#9323])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_create@create-ext-set-pat:
    - shard-rkl:          NOTRUN -> [SKIP][17] ([i915#8562])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_engines@invalid-engines:
    - shard-rkl:          [PASS][18] -> [FAIL][19] ([i915#12027])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-rkl-2/igt@gem_ctx_engines@invalid-engines.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@gem_ctx_engines@invalid-engines.html

  * igt@gem_ctx_persistence@heartbeat-hostile:
    - shard-dg1:          NOTRUN -> [SKIP][20] ([i915#8555])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@gem_ctx_persistence@heartbeat-hostile.html

  * igt@gem_ctx_persistence@hostile:
    - shard-dg1:          [PASS][21] -> [FAIL][22] ([i915#11980])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg1-17/igt@gem_ctx_persistence@hostile.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-16/igt@gem_ctx_persistence@hostile.html

  * igt@gem_ctx_persistence@legacy-engines-persistence:
    - shard-snb:          NOTRUN -> [SKIP][23] ([i915#1099])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-snb7/igt@gem_ctx_persistence@legacy-engines-persistence.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-dg1:          NOTRUN -> [SKIP][24] ([i915#280])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-dg2:          NOTRUN -> [SKIP][25] ([i915#280])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-rkl:          NOTRUN -> [SKIP][26] ([i915#4525])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-dg1:          NOTRUN -> [SKIP][27] ([i915#3539] / [i915#4852]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#3539] / [i915#4852]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gem_exec_fair@basic-none-share.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglu:         NOTRUN -> [FAIL][29] ([i915#2842]) +1 other test fail
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-rkl:          NOTRUN -> [FAIL][30] ([i915#2842]) +3 other tests fail
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fence@syncobj-timeline-wait:
    - shard-glk:          NOTRUN -> [INCOMPLETE][31] ([i915#2295])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk8/igt@gem_exec_fence@syncobj-timeline-wait.html

  * igt@gem_exec_reloc@basic-cpu-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][32] ([i915#3281]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gem_exec_reloc@basic-cpu-gtt.html

  * igt@gem_exec_reloc@basic-gtt-wc-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][33] ([i915#3281]) +4 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html

  * igt@gem_exec_reloc@basic-write-wc-noreloc:
    - shard-dg1:          NOTRUN -> [SKIP][34] ([i915#3281]) +3 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@gem_exec_reloc@basic-write-wc-noreloc.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#4537] / [i915#4812])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gem_exec_schedule@preempt-queue-contexts.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - shard-rkl:          NOTRUN -> [ABORT][36] ([i915#7975] / [i915#8213]) +1 other test abort
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-5/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@gem_fence_thrash@bo-write-verify-threaded-none:
    - shard-dg1:          NOTRUN -> [SKIP][37] ([i915#4860]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@gem_fence_thrash@bo-write-verify-threaded-none.html

  * igt@gem_huc_copy@huc-copy:
    - shard-rkl:          NOTRUN -> [SKIP][38] ([i915#2190])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][39] ([i915#12193]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs@lmem0:
    - shard-dg1:          NOTRUN -> [SKIP][40] ([i915#4565]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@gem_lmem_swapping@parallel-random-verify-ccs@lmem0.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-glk:          NOTRUN -> [SKIP][41] ([i915#4613]) +2 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk2/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          [PASS][42] -> [TIMEOUT][43] ([i915#5493]) +1 other test timeout
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-5/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-rkl:          NOTRUN -> [SKIP][44] ([i915#4613])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-5/igt@gem_lmem_swapping@verify-random.html
    - shard-tglu:         NOTRUN -> [SKIP][45] ([i915#4613])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap_gtt@big-bo:
    - shard-dg1:          NOTRUN -> [SKIP][46] ([i915#4077]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@gem_mmap_gtt@big-bo.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
    - shard-dg2:          NOTRUN -> [SKIP][47] ([i915#4077]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gem_mmap_gtt@fault-concurrent-y.html

  * igt@gem_mmap_wc@pf-nonblock:
    - shard-dg1:          NOTRUN -> [SKIP][48] ([i915#4083])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@gem_mmap_wc@pf-nonblock.html

  * igt@gem_mmap_wc@read-write:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#4083])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gem_mmap_wc@read-write.html

  * igt@gem_partial_pwrite_pread@reads-snoop:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([i915#3282]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gem_partial_pwrite_pread@reads-snoop.html

  * igt@gem_partial_pwrite_pread@write-uncached:
    - shard-dg1:          NOTRUN -> [SKIP][51] ([i915#3282]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@gem_partial_pwrite_pread@write-uncached.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-tglu:         NOTRUN -> [WARN][52] ([i915#2658])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@create-protected-buffer:
    - shard-dg2:          NOTRUN -> [SKIP][53] ([i915#4270])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gem_pxp@create-protected-buffer.html

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
    - shard-rkl:          NOTRUN -> [SKIP][54] ([i915#4270]) +2 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-tglu:         NOTRUN -> [SKIP][55] ([i915#4270])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-dg1:          NOTRUN -> [SKIP][56] ([i915#4270]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][57] ([i915#5190] / [i915#8428]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_render_tiled_blits@basic:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#4079])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gem_render_tiled_blits@basic.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#8411]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_tiled_partial_pwrite_pread@reads:
    - shard-rkl:          NOTRUN -> [SKIP][60] ([i915#3282]) +3 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@gem_tiled_partial_pwrite_pread@reads.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][61] ([i915#3297]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_userptr_blits@unsync-unmap-after-close:
    - shard-rkl:          NOTRUN -> [SKIP][62] ([i915#3297]) +2 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@gem_userptr_blits@unsync-unmap-after-close.html

  * igt@gen9_exec_parse@bb-large:
    - shard-dg1:          NOTRUN -> [SKIP][63] ([i915#2527]) +2 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-15/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-dg2:          NOTRUN -> [SKIP][64] ([i915#2856])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@gen9_exec_parse@bb-start-far.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-rkl:          NOTRUN -> [SKIP][65] ([i915#2527]) +3 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@gen9_exec_parse@bb-start-param.html

  * igt@i915_pm_rps@basic-api:
    - shard-dg2:          NOTRUN -> [SKIP][66] ([i915#11681] / [i915#6621])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live:
    - shard-dg2:          [PASS][67] -> [INCOMPLETE][68] ([i915#1982])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-11/igt@i915_selftest@live.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-6/igt@i915_selftest@live.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-rkl:          NOTRUN -> [SKIP][69] ([i915#3826])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][70] ([i915#8709]) +7 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-glk:          NOTRUN -> [SKIP][71] ([i915#1769])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
    - shard-rkl:          NOTRUN -> [SKIP][72] ([i915#1769] / [i915#3555])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
    - shard-snb:          [PASS][73] -> [FAIL][74] ([i915#5956]) +1 other test fail
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-snb5/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [FAIL][75] ([i915#11808]) +1 other test fail
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-2.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - shard-dg1:          NOTRUN -> [SKIP][76] ([i915#4538] / [i915#5286]) +3 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][77] ([i915#5286]) +4 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-tglu:         NOTRUN -> [SKIP][78] ([i915#5286])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][79] ([i915#3638]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][80] -> [FAIL][81] ([i915#5138])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-mtlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-mtlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-0:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#4538] / [i915#5190]) +2 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][83] ([i915#3638])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][84] +17 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][85] ([i915#4538]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_joiner@basic:
    - shard-dg1:          NOTRUN -> [SKIP][86] ([i915#10656])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_big_joiner@basic.html

  * igt@kms_big_joiner@basic-force-joiner:
    - shard-dg2:          [PASS][87] -> [SKIP][88] ([i915#10656])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-11/igt@kms_big_joiner@basic-force-joiner.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-6/igt@kms_big_joiner@basic-force-joiner.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-rkl:          NOTRUN -> [SKIP][89] ([i915#10656]) +1 other test skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][90] ([i915#6095]) +88 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][91] ([i915#6095]) +34 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#10307] / [i915#10434] / [i915#6095])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-8/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#12042]) +1 other test skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
    - shard-tglu:         NOTRUN -> [SKIP][94] ([i915#12042])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][95] ([i915#6095]) +9 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#10307] / [i915#6095]) +129 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#7213]) +3 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-5/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_cdclk@plane-scaling:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#3742])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_cdclk@plane-scaling.html

  * igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#4087]) +3 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-4/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k:
    - shard-tglu:         NOTRUN -> [SKIP][100] ([i915#7828]) +2 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-dg1:          NOTRUN -> [SKIP][101] ([i915#7828]) +3 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
    - shard-dg2:          NOTRUN -> [SKIP][102] ([i915#7828]) +2 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm:
    - shard-rkl:          NOTRUN -> [SKIP][103] ([i915#7828]) +3 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@kms_chamelium_hpd@hdmi-hpd-storm.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][104] ([i915#7118] / [i915#9424])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@atomic@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][105] ([i915#7173]) +1 other test timeout
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_content_protection@atomic@pipe-a-dp-4.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-rkl:          NOTRUN -> [SKIP][106] ([i915#3116])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-dg2:          NOTRUN -> [SKIP][107] ([i915#3299])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@type1:
    - shard-dg1:          NOTRUN -> [SKIP][108] ([i915#7116] / [i915#9424])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-dg1:          NOTRUN -> [SKIP][109] ([i915#11453]) +1 other test skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#11453]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-glk:          NOTRUN -> [SKIP][111] +228 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk2/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x32:
    - shard-rkl:          NOTRUN -> [SKIP][112] ([i915#3555]) +3 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#3555])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-tglu:         NOTRUN -> [SKIP][114] +18 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-tglu:         NOTRUN -> [SKIP][115] ([i915#4103])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#9723])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-rkl:          NOTRUN -> [SKIP][117] ([i915#8588])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-5/igt@kms_display_modes@mst-extended-mode-negative.html
    - shard-tglu:         NOTRUN -> [SKIP][118] ([i915#8588])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          [PASS][119] -> [SKIP][120] ([i915#3555])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-7/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_draw_crc@draw-method-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([i915#8812])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_draw_crc@draw-method-mmap-wc.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][122] ([i915#3555] / [i915#3840])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglu:         [PASS][123] -> [FAIL][124] ([i915#4767])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-tglu-3/igt@kms_fbcon_fbt@fbc-suspend.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-6/igt@kms_fbcon_fbt@fbc-suspend.html
    - shard-glk:          [PASS][125] -> [FAIL][126] ([i915#4767])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-glk4/igt@kms_fbcon_fbt@fbc-suspend.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk9/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_fbcon_fbt@psr:
    - shard-rkl:          NOTRUN -> [SKIP][127] ([i915#3955])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@display-2x:
    - shard-dg1:          NOTRUN -> [SKIP][128] ([i915#1839])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-rkl:          NOTRUN -> [SKIP][129] ([i915#1839])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-flip-vs-panning:
    - shard-dg1:          NOTRUN -> [SKIP][130] ([i915#9934])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@kms_flip@2x-flip-vs-panning.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][131] ([i915#3637]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-dg2:          [PASS][132] -> [FAIL][133] ([i915#79])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-fences:
    - shard-dg2:          NOTRUN -> [SKIP][134] ([i915#8381])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#2672]) +3 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][136] ([i915#2672] / [i915#3555]) +3 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-dg1:          NOTRUN -> [SKIP][137] ([i915#2672] / [i915#3555])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][138] ([i915#2587] / [i915#2672])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][139] ([i915#2672] / [i915#3555])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][140] ([i915#2587] / [i915#2672])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#5354]) +12 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-dg1:          NOTRUN -> [SKIP][142] ([i915#5439]) +1 other test skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][143] ([i915#3023]) +19 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-snb:          NOTRUN -> [SKIP][144] +54 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-snb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][145] ([i915#1825]) +28 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][146] ([i915#8708]) +9 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-dg2:          NOTRUN -> [SKIP][147] ([i915#3458]) +3 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
    - shard-dg1:          NOTRUN -> [SKIP][148] ([i915#3458]) +7 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][149] ([i915#8708]) +1 other test skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch:
    - shard-rkl:          NOTRUN -> [SKIP][150] ([i915#3555] / [i915#8228])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg1:          NOTRUN -> [SKIP][151] ([i915#3555] / [i915#8228])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_hdr@invalid-hdr.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-rkl:          NOTRUN -> [SKIP][152] ([i915#6301])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
    - shard-dg1:          NOTRUN -> [SKIP][153] +18 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html

  * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
    - shard-dg2:          NOTRUN -> [SKIP][154] +3 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][155] ([i915#12169])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][156] ([i915#10647]) +1 other test fail
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([i915#3555] / [i915#9423])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#9423]) +1 other test skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][159] ([i915#9423]) +11 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-13/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#5235] / [i915#9423]) +2 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-7/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][161] ([i915#5235]) +1 other test skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
    - shard-dg1:          NOTRUN -> [SKIP][162] ([i915#6953])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#9423]) +8 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][164] ([i915#9728]) +3 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-rkl:          NOTRUN -> [SKIP][165] ([i915#9685]) +2 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-3/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2:          [PASS][166] -> [SKIP][167] ([i915#9340])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-8/igt@kms_pm_lpsp@kms-lpsp.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-7/igt@kms_pm_lpsp@kms-lpsp.html
    - shard-rkl:          [PASS][168] -> [SKIP][169] ([i915#9340])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-rkl-2/igt@kms_pm_lpsp@kms-lpsp.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-1/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][170] ([i915#9519]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-dg2:          [PASS][171] -> [SKIP][172] ([i915#9519])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-3/igt@kms_pm_rpm@dpms-non-lpsp.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-4/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg1:          NOTRUN -> [SKIP][173] ([i915#9519])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg2:          NOTRUN -> [SKIP][174] ([i915#9519])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
    - shard-dg2:          NOTRUN -> [SKIP][175] ([i915#11520]) +1 other test skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#11520]) +3 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-sf:
    - shard-dg1:          NOTRUN -> [SKIP][177] ([i915#11520]) +1 other test skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-pr-sprite-plane-onoff:
    - shard-dg1:          NOTRUN -> [SKIP][178] ([i915#1072] / [i915#9732]) +9 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_psr@fbc-pr-sprite-plane-onoff.html

  * igt@kms_psr@pr-cursor-plane-onoff:
    - shard-rkl:          NOTRUN -> [SKIP][179] ([i915#1072] / [i915#9732]) +18 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@kms_psr@pr-cursor-plane-onoff.html

  * igt@kms_psr@psr-primary-blt:
    - shard-dg2:          NOTRUN -> [SKIP][180] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_psr@psr-primary-blt.html

  * igt@kms_psr@psr-sprite-blt:
    - shard-tglu:         NOTRUN -> [SKIP][181] ([i915#9732]) +5 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_psr@psr-sprite-blt.html

  * igt@kms_rotation_crc@sprite-rotation-270:
    - shard-dg2:          NOTRUN -> [SKIP][182] ([i915#11131] / [i915#4235])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-270.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - shard-dg2:          NOTRUN -> [SKIP][183] ([i915#3555])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-rkl:          NOTRUN -> [SKIP][184] ([i915#8623])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-basic:
    - shard-tglu:         NOTRUN -> [SKIP][185] ([i915#3555]) +1 other test skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-8/igt@kms_vrr@flip-basic.html

  * igt@kms_vrr@max-min:
    - shard-rkl:          NOTRUN -> [SKIP][186] ([i915#9906]) +1 other test skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_vrr@max-min.html

  * igt@kms_vrr@negative-basic:
    - shard-dg1:          NOTRUN -> [SKIP][187] ([i915#3555] / [i915#9906])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@kms_vrr@negative-basic.html

  * igt@kms_writeback@writeback-check-output:
    - shard-dg2:          NOTRUN -> [SKIP][188] ([i915#2437])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-dg1:          NOTRUN -> [SKIP][189] ([i915#2437] / [i915#9412])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@mi-rpc:
    - shard-rkl:          NOTRUN -> [SKIP][190] ([i915#2434])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@perf@mi-rpc.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-dg2:          NOTRUN -> [SKIP][191] ([i915#8516])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-dg1:          NOTRUN -> [SKIP][192] ([i915#3708])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@prime_vgem@fence-flip-hang.html

  * igt@prime_vgem@fence-write-hang:
    - shard-rkl:          NOTRUN -> [SKIP][193] ([i915#3708])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-rkl:          NOTRUN -> [SKIP][194] ([i915#9917])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@sriov_basic@bind-unbind-vf.html

  * igt@syncobj_wait@invalid-wait-zero-handles:
    - shard-dg1:          NOTRUN -> [FAIL][195] ([i915#9781])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-18/igt@syncobj_wait@invalid-wait-zero-handles.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@hostile:
    - shard-tglu:         [FAIL][196] ([i915#11980]) -> [PASS][197]
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-tglu-10/igt@gem_ctx_persistence@hostile.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-3/igt@gem_ctx_persistence@hostile.html

  * igt@gem_exec_fair@basic-none-share:
    - shard-rkl:          [FAIL][198] ([i915#2842]) -> [PASS][199] +1 other test pass
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-rkl-5/igt@gem_exec_fair@basic-none-share.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@gem_exec_fair@basic-none-share.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [TIMEOUT][200] ([i915#5493]) -> [PASS][201] +1 other test pass
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-snb:          [ABORT][202] ([i915#9820]) -> [PASS][203]
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-snb1/igt@i915_module_load@reload-with-fault-injection.html
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [INCOMPLETE][204] ([i915#7790]) -> [PASS][205]
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-snb6/igt@i915_pm_rps@reset.html
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-snb7/igt@i915_pm_rps@reset.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
    - shard-dg2:          [FAIL][206] ([i915#5956]) -> [PASS][207]
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-11/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-6/igt@kms_atomic_transition@plane-toggle-modeset-transition.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-mtlp:         [DMESG-FAIL][208] ([i915#11627]) -> [PASS][209]
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
    - shard-rkl:          [ABORT][210] ([i915#10354]) -> [PASS][211]
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-rkl-4/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1:
    - shard-snb:          [FAIL][212] ([i915#2122]) -> [PASS][213] +1 other test pass
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-snb7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1.html
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-snb6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-glk:          [INCOMPLETE][214] ([i915#4839]) -> [PASS][215]
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-glk4/igt@kms_flip@flip-vs-suspend-interruptible.html
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk8/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a2:
    - shard-glk:          [INCOMPLETE][216] ([i915#9878]) -> [PASS][217]
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-glk4/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a2.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk8/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a2.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu:         [FAIL][218] ([i915#9295]) -> [PASS][219]
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-tglu-8/igt@kms_pm_dc@dc6-dpms.html
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-6/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@i2c:
    - shard-dg2:          [FAIL][220] ([i915#8717]) -> [PASS][221]
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-2/igt@kms_pm_rpm@i2c.html
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-6/igt@kms_pm_rpm@i2c.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-dg2:          [SKIP][222] ([i915#9519]) -> [PASS][223]
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-10/igt@kms_pm_rpm@modeset-non-lpsp.html
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg2:          [FAIL][224] ([IGT#2]) -> [PASS][225]
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-5/igt@kms_sysfs_edid_timing.html
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_sysfs_edid_timing.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-rkl:          [FAIL][226] ([i915#9196]) -> [PASS][227]
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-rkl-2/igt@kms_universal_plane@cursor-fb-leak.html
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-6/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
    - shard-tglu:         [FAIL][228] ([i915#9196]) -> [PASS][229] +1 other test pass
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-tglu:         [WARN][230] ([i915#2681]) -> [FAIL][231] ([i915#3591]) +1 other test fail
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-idle.html
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_selftest@mock:
    - shard-glk:          [DMESG-WARN][232] ([i915#1982] / [i915#9311]) -> [DMESG-WARN][233] ([i915#9311])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-glk9/igt@i915_selftest@mock.html
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-glk2/igt@i915_selftest@mock.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          [SKIP][234] ([i915#7118] / [i915#9424]) -> [TIMEOUT][235] ([i915#7173]) +1 other test timeout
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-3/igt@kms_content_protection@legacy.html
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-dg2:          [SKIP][236] ([i915#11453]) -> [SKIP][237] ([i915#11453] / [i915#3359])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-5/igt@kms_cursor_crc@cursor-sliding-512x170.html
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
    - shard-dg2:          [SKIP][238] ([i915#3458]) -> [SKIP][239] ([i915#10433] / [i915#3458]) +1 other test skip
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2:          [SKIP][240] ([i915#10433] / [i915#3458]) -> [SKIP][241] ([i915#3458]) +3 other tests skip
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][242] ([i915#4070] / [i915#4816]) -> [SKIP][243] ([i915#4816])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_psr@fbc-psr-primary-blt:
    - shard-dg2:          [SKIP][244] ([i915#1072] / [i915#9732]) -> [SKIP][245] ([i915#1072] / [i915#9673] / [i915#9732]) +9 other tests skip
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-3/igt@kms_psr@fbc-psr-primary-blt.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_psr@fbc-psr-primary-blt.html

  * igt@kms_psr@psr-suspend:
    - shard-dg2:          [SKIP][246] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][247] ([i915#1072] / [i915#9732]) +9 other tests skip
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-11/igt@kms_psr@psr-suspend.html
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-7/igt@kms_psr@psr-suspend.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2:          [SKIP][248] ([i915#11131]) -> [SKIP][249] ([i915#11131] / [i915#4235])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-3/igt@kms_rotation_crc@bad-tiling.html
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-11/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-dg2:          [SKIP][250] ([i915#11131] / [i915#4235]) -> [SKIP][251] ([i915#11131])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15400/shard-dg2-11/igt@kms_rotation_crc@primary-rotation-270.html
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/shard-dg2-6/igt@kms_rotation_crc@primary-rotation-270.html

  
  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10354
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
  [i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11627]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11627
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808
  [i915#11980]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11980
  [i915#12027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12027
  [i915#12042]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12042
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12193
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2295
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3826
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4767
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
  [i915#7790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7790
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/79
  [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
  [i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8717
  [i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
  [i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
  [i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
  [i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
  [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
  [i915#9878]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9878
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_15400 -> Patchwork_138552v1

  CI-20190529: 20190529
  CI_DRM_15400: 1b37d4587b45639327eeb4cce29f77d487f7700a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8013: 8013
  Patchwork_138552v1: 1b37d4587b45639327eeb4cce29f77d487f7700a @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138552v1/index.html

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RE: [PATCH 0/3] Some correction in the DP Link Training dequence

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Arun R
> Murthy
> Sent: Thursday, September 12, 2024 10:36 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: [PATCH 0/3] Some correction in the DP Link Training dequence

Typo : sequence

Regards,
Suraj Kandpal
> 
> 
> Arun R Murthy (3):
>   drm/i915/dp: use fsleep instead of usleep_rage for LT
>   drm/i915/dp: read Aux RD interval after reading the FFE preset
>   drm/i915/dp: Include the time taken by AUX Tx for timeout
> 
>  .../drm/i915/display/intel_dp_link_training.c | 20 +++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> --
> 2.25.1