From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 4/7] drm/i915: Enable 10bpc + CCS on ICL
Date: Wed, 18 Sep 2024 17:44:42 +0300 [thread overview]
Message-ID: <20240918144445.5716-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20240918144445.5716-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
ICL also supports compressed 10bpc scanout. Enable it.
v2: Set .depth=30 for all variants to match drm_fourcc.c
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 8 +++
.../drm/i915/display/skl_universal_plane.c | 65 +++++++++++++++++++
2 files changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 9b9da4f71f73..83495e165da7 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -45,6 +45,14 @@ static const struct drm_format_info skl_ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
+ { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
+ { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
+ { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
+ { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
};
/*
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 9f34df60b112..8817758ef10d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2302,6 +2302,60 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
}
}
+static bool icl_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ struct intel_plane *plane = to_intel_plane(_plane);
+
+ if (!intel_fb_plane_supports_modifier(plane, modifier))
+ return false;
+
+ switch (format) {
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ if (intel_fb_is_ccs_modifier(modifier))
+ return true;
+ fallthrough;
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_YUYV:
+ case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
+ case DRM_FORMAT_XVYU2101010:
+ if (modifier == I915_FORMAT_MOD_Yf_TILED)
+ return true;
+ fallthrough;
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
+ case DRM_FORMAT_XVYU12_16161616:
+ case DRM_FORMAT_XVYU16161616:
+ if (modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED ||
+ modifier == I915_FORMAT_MOD_Y_TILED)
+ return true;
+ fallthrough;
+ default:
+ return false;
+ }
+}
+
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
@@ -2363,6 +2417,15 @@ static const struct drm_plane_funcs skl_plane_funcs = {
.format_mod_supported = skl_plane_format_mod_supported,
};
+static const struct drm_plane_funcs icl_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = intel_plane_destroy,
+ .atomic_duplicate_state = intel_plane_duplicate_state,
+ .atomic_destroy_state = intel_plane_destroy_state,
+ .format_mod_supported = icl_plane_format_mod_supported,
+};
+
static const struct drm_plane_funcs gen12_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -2542,6 +2605,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
if (DISPLAY_VER(dev_priv) >= 12)
plane_funcs = &gen12_plane_funcs;
+ else if (DISPLAY_VER(dev_priv) == 11)
+ plane_funcs = &icl_plane_funcs;
else
plane_funcs = &skl_plane_funcs;
--
2.44.2
next prev parent reply other threads:[~2024-09-18 14:45 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-18 14:44 [PATCH 0/7] drm/i915: 10bpc/fp16 + CCS support Ville Syrjala
2024-09-18 14:44 ` [PATCH 1/7] drm/i915: Set clear color block size to 0x0 Ville Syrjala
2024-09-23 14:58 ` Imre Deak
2024-09-18 14:44 ` [PATCH 2/7] drm/i915: Disable compression tricks on JSL Ville Syrjala
2024-10-04 13:22 ` Juha-Pekka Heikkila
2024-10-04 17:54 ` Ville Syrjälä
2024-11-27 15:56 ` Sebastian Brzezinka
2024-11-28 12:34 ` Ville Syrjälä
2024-11-28 13:20 ` Sebastian Brzezinka
2024-09-18 14:44 ` [PATCH 3/7] drm/i915: Enable 10bpc + CCS on TGL+ Ville Syrjala
2024-10-04 13:35 ` Juha-Pekka Heikkila
2024-10-04 18:03 ` Ville Syrjälä
2024-10-08 9:01 ` Juha-Pekka Heikkila
2024-11-25 6:55 ` Xi Ruoyao
2024-11-27 5:57 ` Ville Syrjälä
2024-11-27 6:58 ` Xi Ruoyao
2024-09-18 14:44 ` Ville Syrjala [this message]
2024-10-04 13:36 ` [PATCH 4/7] drm/i915: Enable 10bpc + CCS on ICL Juha-Pekka Heikkila
2024-09-18 14:44 ` [PATCH 5/7] drm/i915: Enable fp16 + CCS on TGL+ Ville Syrjala
2024-10-04 13:50 ` Juha-Pekka Heikkila
2024-09-18 14:44 ` [PATCH 6/7] drm/i915: Drop GEN12_MC_CCS check from skl_plane_max_width() Ville Syrjala
2024-10-04 13:52 ` Juha-Pekka Heikkila
2024-09-18 14:44 ` [PATCH 7/7] drm/i915: s/gen12/tgl/ in the universal plane code Ville Syrjala
2024-10-04 13:54 ` Juha-Pekka Heikkila
2024-09-18 15:50 ` ✗ Fi.CI.SPARSE: warning for drm/i915: 10bpc/fp16 + CCS support Patchwork
2024-09-18 15:59 ` ✓ Fi.CI.BAT: success " Patchwork
2024-09-19 5:19 ` ✗ Fi.CI.IGT: failure " Patchwork
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