From: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/7] drm/i915: Enable fp16 + CCS on TGL+
Date: Fri, 4 Oct 2024 16:50:07 +0300 [thread overview]
Message-ID: <f9389193-557c-49ad-8ab3-6b8dd7899403@gmail.com> (raw)
In-Reply-To: <20240918144445.5716-6-ville.syrjala@linux.intel.com>
Here the same question on depth as on those two other patches, I think
that field should have value other than zero. Otherwise all did look ok.
On 18.9.2024 17.44, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> TGL+ support compressed fp16 scanout. Enable it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 36 +++++++++++++++++++
> .../drm/i915/display/skl_universal_plane.c | 8 ++---
> 2 files changed, 40 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index 83495e165da7..2d384092416e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -87,6 +87,18 @@ static const struct drm_format_info gen12_ccs_formats[] = {
> { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
> .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2,
> + .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2,
> + .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2,
> + .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2,
> + .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_YUYV, .num_planes = 2,
> .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> .hsub = 2, .vsub = 1, .is_yuv = true },
> @@ -145,6 +157,18 @@ static const struct drm_format_info gen12_ccs_cc_formats[] = {
> { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
> .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 },
> .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 3,
> + .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 3,
> + .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 3,
> + .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 3,
> + .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> };
>
> static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
> @@ -172,6 +196,18 @@ static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
> { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
> .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
> .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2,
> + .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2,
> + .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2,
> + .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2,
> + .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> };
>
> struct intel_modifier_desc {
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 8817758ef10d..afaa92a6d91c 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2373,6 +2373,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_XBGR2101010:
> case DRM_FORMAT_ARGB2101010:
> case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> if (intel_fb_is_ccs_modifier(modifier))
> return true;
> fallthrough;
> @@ -2391,10 +2395,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XVYU2101010:
> case DRM_FORMAT_C8:
> - case DRM_FORMAT_XBGR16161616F:
> - case DRM_FORMAT_ABGR16161616F:
> - case DRM_FORMAT_XRGB16161616F:
> - case DRM_FORMAT_ARGB16161616F:
> case DRM_FORMAT_Y210:
> case DRM_FORMAT_Y212:
> case DRM_FORMAT_Y216:
next prev parent reply other threads:[~2024-10-04 13:50 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-18 14:44 [PATCH 0/7] drm/i915: 10bpc/fp16 + CCS support Ville Syrjala
2024-09-18 14:44 ` [PATCH 1/7] drm/i915: Set clear color block size to 0x0 Ville Syrjala
2024-09-23 14:58 ` Imre Deak
2024-09-18 14:44 ` [PATCH 2/7] drm/i915: Disable compression tricks on JSL Ville Syrjala
2024-10-04 13:22 ` Juha-Pekka Heikkila
2024-10-04 17:54 ` Ville Syrjälä
2024-11-27 15:56 ` Sebastian Brzezinka
2024-11-28 12:34 ` Ville Syrjälä
2024-11-28 13:20 ` Sebastian Brzezinka
2024-09-18 14:44 ` [PATCH 3/7] drm/i915: Enable 10bpc + CCS on TGL+ Ville Syrjala
2024-10-04 13:35 ` Juha-Pekka Heikkila
2024-10-04 18:03 ` Ville Syrjälä
2024-10-08 9:01 ` Juha-Pekka Heikkila
2024-11-25 6:55 ` Xi Ruoyao
2024-11-27 5:57 ` Ville Syrjälä
2024-11-27 6:58 ` Xi Ruoyao
2024-09-18 14:44 ` [PATCH 4/7] drm/i915: Enable 10bpc + CCS on ICL Ville Syrjala
2024-10-04 13:36 ` Juha-Pekka Heikkila
2024-09-18 14:44 ` [PATCH 5/7] drm/i915: Enable fp16 + CCS on TGL+ Ville Syrjala
2024-10-04 13:50 ` Juha-Pekka Heikkila [this message]
2024-09-18 14:44 ` [PATCH 6/7] drm/i915: Drop GEN12_MC_CCS check from skl_plane_max_width() Ville Syrjala
2024-10-04 13:52 ` Juha-Pekka Heikkila
2024-09-18 14:44 ` [PATCH 7/7] drm/i915: s/gen12/tgl/ in the universal plane code Ville Syrjala
2024-10-04 13:54 ` Juha-Pekka Heikkila
2024-09-18 15:50 ` ✗ Fi.CI.SPARSE: warning for drm/i915: 10bpc/fp16 + CCS support Patchwork
2024-09-18 15:59 ` ✓ Fi.CI.BAT: success " Patchwork
2024-09-19 5:19 ` ✗ Fi.CI.IGT: failure " Patchwork
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